library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

Library UNIMACRO;
use UNIMACRO.vcomponents.all;

entity mult is
    generic (
        A_WIDTH         : integer := 12;
        B_WIDTH         : integer := 4;
        PIPELINE_STAGES : integer := 1
    );
    port (
        clk : in std_logic;  
        A   : in std_logic_vector(A_WIDTH-1 downto 0);
        B   : in std_logic_vector(B_WIDTH-1 downto 0);
        P   : out std_logic_vector(A_WIDTH+B_WIDTH-1 downto 0)
    );
end entity;

architecture arch of mult is
    
    
begin

    MULT_MACRO_inst : MULT_MACRO
    generic map (
        DEVICE  => "7SERIES",       -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6" 
        LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
        WIDTH_A => A_WIDTH,         -- Multiplier A-input bus width, 1-25 
        WIDTH_B => B_WIDTH)         -- Multiplier B-input bus width, 1-18
    port map (
        P   => P,       -- Multiplier ouput bus, width determined by WIDTH_P generic 
        A   => A,       -- Multiplier input A bus, width determined by WIDTH_A generic 
        B   => B,       -- Multiplier input B bus, width determined by WIDTH_B generic 
        CE  => '1',     -- 1-bit active high input clock enable
        CLK => clk,     -- 1-bit positive edge clock input
        RST => '0'      -- 1-bit input active high reset
    );

end architecture;