create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports sys_clk]
create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000}
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1]
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -5.000 [get_ports adc_cs_n]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_cs_n]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_cs_n]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000 [get_ports dac_cs_n]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out]
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out]

set_property PACKAGE_PIN Y9 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]

set_property PACKAGE_PIN P16 [get_ports areset]
set_property PACKAGE_PIN Y11 [get_ports adc_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports adc_cs_n]
set_property PACKAGE_PIN AA11 [get_ports adc_data_in1]
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in1]
set_property PACKAGE_PIN Y19 [get_ports adc_data_in2]
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in2]
set_property PACKAGE_PIN AA9 [get_ports adc_sclk]
set_property IOSTANDARD LVCMOS33 [get_ports adc_sclk]
set_property PACKAGE_PIN W12 [get_ports dac_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports dac_cs_n]
set_property PACKAGE_PIN W11 [get_ports dac_data_out]
set_property IOSTANDARD LVCMOS33 [get_ports dac_data_out]
set_property PACKAGE_PIN V10 [get_ports dac_ldac]
set_property IOSTANDARD LVCMOS33 [get_ports dac_ldac]
set_property PACKAGE_PIN W8 [get_ports dac_sclk]
set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk]

set_property IOSTANDARD LVCMOS33 [get_ports areset]
