library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.typedef_package.all;

entity open_loop is
    port (
        clk             : in std_logic;
        areset          : in std_logic;
        adc_data_in     : in std_logic;
        adc_cs_n        : out std_logic;
        dac_data_out    : out std_logic;
        dac_cs_n        : out std_logic;
        dac_ldac        : out std_logic
    );
end entity;

architecture arch of open_loop is
    
    --*****SIGNAL DECLARATION*****
    signal interconnect : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
    signal adc_done : std_logic := '0';
    
    --*****COMPONENT DECLARATION*****
    component pmod_ad1_ctrl is
        generic(
            TRANSFER_CLK_COUNT  : integer := 16;
            DELAY_CLK_CNT       : integer := 2;
            DATA_WIDTH          : integer := 12
        );
        port (
            sclk    : in std_logic; -- PMOD-AD1
            reset   : in std_logic;
            sdata1  : in std_logic; -- PMOD-AD1
            sdata2  : in std_logic; -- PMOD-AD1
            enable  : in std_logic;
            cs_n    : out std_logic;-- PMOD-AD1
            data1   : out std_logic_vector(DATA_WIDTH-1 downto 0);
            data2   : out std_logic_vector(DATA_WIDTH-1 downto 0);
            done    : out std_logic
        );
    end component;
    
    component pmod_da3_ctrl is
        generic(
            TRANSFER_CLK_COUNT  : integer := 16;
            DATA_WIDTH          : integer := 16
        );
        port (
            sclk    : in std_logic; -- PMOD-DA3
            reset   : in std_logic;
            start   : in std_logic;
            data    : in std_logic_vector(DATA_WIDTH-1 downto 0);
            cs_n    : out std_logic;-- PMOD-DA3
            sdata   : out std_logic;-- PMOD-DA3
            ldac    : out std_logic;-- PMOD-DA3
            done    : out std_logic
        );
    end component;
    
begin

    --*****COMPONENT INSTANTIATION*****
    adc : pmod_ad1_ctrl
    generic map(
        TRANSFER_CLK_COUNT  => ADC_TRANSFER_CLK_COUNT,
        DELAY_CLK_CNT       => ADC_DELAY_CLK_CNT,
        DATA_WIDTH          => ADC_DATA_WIDTH
    )
    port map(
        sclk    => clk,
        reset   => areset,
        sdata1  => adc_data_in,
        sdata2  => '0',
        enable  => '1',
        cs_n    => adc_cs_n,
        data1   => interconnect(DAC_DATA_WIDTH-1 downto DAC_DATA_WIDTH-ADC_DATA_WIDTH),
        data2   => open,
        done    => adc_done
    );
    
    dac : pmod_da3_ctrl
    generic map(
        TRANSFER_CLK_COUNT  => DAC_TRANSFER_CLK_COUNT,
        DATA_WIDTH          => DAC_DATA_WIDTH
    )
    port map(
        sclk    => clk,
        reset   => areset,
        start   => adc_done,
        data    => interconnect,
        cs_n    => dac_cs_n,
        sdata   => dac_data_out,
        ldac    => dac_ldac,
        done    => open
    );
    
end architecture;