library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

Library UNIMACRO;
use UNIMACRO.vcomponents.all;

entity mult is
    generic (
        A_WIDTH         : integer := 12;
        B_WIDTH         : integer := 4;
        PIPELINE_STAGES : integer := 1;
        UNSIGNED        : boolean := true
    );
    port (
        clk : in std_logic;  
        A   : in std_logic_vector(A_WIDTH-1 downto 0);
        B   : in std_logic_vector(B_WIDTH-1 downto 0);
        P   : out std_logic_vector(A_WIDTH+B_WIDTH-1 downto 0)
    );
end entity;

architecture arch of mult is
    
    
begin

    mult_gen : if (UNSIGNED = true) generate
        MULT_MACRO_inst : MULT_MACRO
            generic map (
                DEVICE  => "7SERIES",       -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6" 
                LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
                WIDTH_A => A_WIDTH+1,       -- Multiplier A-input bus width, 1-25 
                WIDTH_B => B_WIDTH+1)       -- Multiplier B-input bus width, 1-18
            port map (
                P(A_WIDTH+B_WIDTH+1 downto A_WIDTH+B_WIDTH) => open,
                P(A_WIDTH+B_WIDTH-1 downto 0)               => P,
                A   => "0" & A,
                B   => "0" & B,
                CE  => '1',
                CLK => clk,
                RST => '0'
            );
    else generate
        MULT_MACRO_inst : MULT_MACRO
            generic map (
                DEVICE  => "7SERIES",       -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6" 
                LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
                WIDTH_A => A_WIDTH,         -- Multiplier A-input bus width, 1-25 
                WIDTH_B => B_WIDTH)         -- Multiplier B-input bus width, 1-18
            port map (
                P   => P,
                A   => A,
                B   => B,
                CE  => '1',
                CLK => clk,
                RST => '0'
            );
    end generate;
    
end architecture;