library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity synchronizer is
    generic (
        SYNC_STAGES : integer := 2
    );
    port (
        clk     : in std_logic;
        input   : in std_logic;
        output  : out std_logic
    );
end entity;

architecture arch of synchronizer is
    
    --*****SIGNAl DECLARATION*****
    signal sync_array : std_logic_vector(SYNC_STAGES-1 downto 0) := (others => '0');
    
begin

    sync : process(clk)
    begin
        if rising_edge(clk) then
            output      <= sync_array(SYNC_STAGES-1);
            sync_array  <= sync_array(SYNC_STAGES-2 downto 0) & input;
        end if;
    end process;
    
end architecture;