library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pmod_ad1_tb is
end entity;

architecture beh of pmod_ad1_tb is
    
    --*****COMPONENT DECLARATION*****
    component AD1_controller is
        port (	
            --General usage
            CLK     : in std_logic;	-- System Clock (50MHz)     
            RST     : in std_logic;
            --Pmod interface signals
            SDATA1  : in std_logic;
            SDATA2  : in std_logic;
            SCLK    : out std_logic;
            CS      : out std_logic;
            --User interface signals
            DATA1   : out std_logic_vector(11 downto 0);
            DATA2   : out std_logic_vector(11 downto 0);
            START   : in std_logic; 
            DONE    : out std_logic
        );
    end component;
    
    --*****SIGNAL DEFINITIONS*****
    signal clk, reset, cs_n, done, sclk : std_logic := '0';
    signal sdata1, sdata2 : std_logic := '0';
    signal data1, data2 : std_logic_vector(11 downto 0);
    
begin
    
    uut : AD1_controller
        port map (	
            --General usage
            CLK     => clk,
            RST     => reset,
            --Pmod interface signals
            SDATA1  => sdata1,
            SDATA2  => sdata2,
            SCLK    => sclk,
            CS      => cs_n,
            --User interface signals
            DATA1   => data1,
            DATA2   => data2,
            START   => done,
            DONE    => done
        );
        
    clk_prc : process
    begin
        clk <= '1';
        wait for 25 ns;
        clk <= '0';
        wait for 25 ns;
    end process;
    
    data_prc : process
    begin
        wait until falling_edge(sclk);
        sdata1  <= not sdata1;
        sdata2  <= not sdata2;
    end process;
    
    process
    begin
        --INITIALISE SIGNALS
        reset   <= '1';
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        wait;
    end process;
    
end architecture;
