library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pmod_da3_ctrl_tb is
    generic(
        TRANSFER_CLK_COUNT  : integer := 16;
        DATA_BITS           : integer := 16
    );
end entity;

architecture beh of pmod_da3_ctrl_tb is
    
    --*****COMPONENT DECLARATION*****
    component pmod_da3_ctrl is
        generic(
            TRANSFER_CLK_COUNT  : integer := 16;
            DATA_BITS           : integer := 16
        );
        port (
            sclk    : in std_logic; -- PMOD-DA3
            reset   : in std_logic;
            start   : in std_logic;
            data    : in std_logic_vector(DATA_BITS-1 downto 0);
            cs_n    : out std_logic;-- PMOD-DA3
            sdata   : out std_logic;-- PMOD-DA3
            ldac    : out std_logic;-- PMOD-DA3
            done    : out std_logic
        );
    end component;
    
    --*****SIGNAL DEFINITIONS*****
    signal clk, reset, cs_n, start, done, sdata, ldac : std_logic := '0';
    signal data : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
    
begin
    
    uut : pmod_da3_ctrl
        generic map(
            TRANSFER_CLK_COUNT  => TRANSFER_CLK_COUNT,
            DATA_BITS           => DATA_BITS
        )
        port map(
            sclk    => clk,
            reset   => reset,
            start   => start,
            data    => data,
            cs_n    => cs_n,
            sdata   => sdata,
            ldac    => ldac,
            done    => done
        );
        
    clk_prc : process
    begin
        clk <= '1';
        wait for 25 ns;
        clk <= '0';
        wait for 25 ns;
    end process;
    
    process
    begin
        --INITIALISE SIGNALS
        reset   <= '0';
        wait for 5 ns;
        wait until rising_edge(clk);
        start   <= '1';
        data    <= (others => '1');
        wait until rising_edge(clk);
        start   <= '0';
        data    <= (others => '0');
        wait until rising_edge(done);
        wait;
    end process;
    
end architecture;
