library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
    port (
        sys_clk         : in std_logic;
        areset          : in std_logic;
        adc_data_in1    : in std_logic;
        adc_data_in2    : in std_logic;
        adc_cs_n        : out std_logic;
        adc_sclk        : out std_logic;
        dac_data_out    : out std_logic;
        dac_cs_n        : out std_logic;
        dac_ldac        : out std_logic;
        dac_sclk        : out std_logic
    );
end entity;

architecture arch of top is
    
    --*****COMPONENT DECLARATION*****
    component clockgen is
        port (
            clk_in  : in std_logic;
            clk_out : out std_logic
        );
    end component;
    
    component open_loop is
        port (
            clk             : in std_logic;
            areset          : in std_logic;
            adc_data_in     : in std_logic;
            adc_cs_n        : out std_logic;
            dac_data_out    : out std_logic;
            dac_cs_n        : out std_logic;
            dac_ldac        : out std_logic
        );
    end component;
    
    --*****SIGNAL DECLARATION*****
    signal clk_20 : std_logic := '0';
    
begin
    
    clockgen_inst : clockgen
        port map(
            clk_in  => sys_clk,
            clk_out => clk_20
        );

    open_loop_inst : open_loop
        port map(
            clk             => clk_20,
            areset          => areset,
            adc_data_in     => adc_data_in1,
            adc_cs_n        => adc_cs_n,
            dac_data_out    => dac_data_out,
            dac_cs_n        => dac_cs_n,
            dac_ldac        => dac_ldac
        );
        
    adc_sclk    <= clk_20;
    dac_sclk    <= clk_20;
end architecture;