library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pmod_ad1_ctrl_tb is
    generic(
        TRANSFER_CLK_COUNT  : integer := 16;
        DELAY_CLK_CNT       : integer := 2;
        DATA_WIDTH          : integer := 12
    );
end entity;

architecture beh of pmod_ad1_ctrl_tb is
    
    --*****COMPONENT DECLARATION*****
    component pmod_ad1_ctrl is
        generic(
            TRANSFER_CLK_COUNT  : integer := 16;
            DELAY_CLK_CNT       : integer := 2;
            DATA_WIDTH          : integer := 12
        );
        port (
            sclk    : in std_logic; -- PMOD-AD1
            reset   : in std_logic;
            sdata1  : in std_logic; -- PMOD-AD1
            sdata2  : in std_logic; -- PMOD-AD1
            enable  : in std_logic;
            cs_n    : out std_logic;-- PMOD-AD1
            data1   : out std_logic_vector(DATA_WIDTH-1 downto 0);
            data2   : out std_logic_vector(DATA_WIDTH-1 downto 0);
            done    : out std_logic
        );
    end component;
    
    --*****SIGNAL DEFINITIONS*****
    signal clk, reset, cs_n, done, sdata1, sdata2 : std_logic := '0';
    signal data1, data2 : std_logic_vector(DATA_WIDTH-1 downto 0);
    
begin
    
    uut : pmod_ad1_ctrl
        generic map(
            TRANSFER_CLK_COUNT  => TRANSFER_CLK_COUNT,
            DELAY_CLK_CNT       => DELAY_CLK_CNT,
            DATA_WIDTH          => DATA_WIDTH
        )
        port map(
            sclk    => clk,
            reset   => reset,
            sdata1  => sdata1,
            sdata2  => sdata2,
            enable  => '1',
            cs_n    => cs_n,
            data1   => data1,
            data2   => data2,
            done    => done
        );
        
    clk_prc : process
    begin
        clk <= '1';
        wait for 25 ns;
        clk <= '0';
        wait for 25 ns;
    end process;
    
    data_prc : process
    begin
        wait until rising_edge(clk);
        sdata1  <= not sdata1;
        sdata2  <= not sdata2;
    end process;
    
    process
    begin
        --INITIALISE SIGNALS
        reset   <= '1';
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        wait;
    end process;
    
end architecture;
