library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity clockgen is
    generic (
        CLKFBOUT_MULT   : integer := 41;
        CLKIN1_PERIOD   : real := 10.000000;
        CLKOUT0_DIVIDE  : integer := 41;
        DIVCLK_DIVIDE   : integer := 5
    );
    port (
        clk_in  : in std_logic;
        clk_out : out std_logic
    );
end entity;

architecture inst of clockgen is
    
    signal clkfbout, clkfbout_buf : std_logic := '0';
    
begin
    
    --*****FEEDBACK*****
    clkf_buf: unisim.vcomponents.BUFG
    port map (
        I => clkfbout,
        O => clkfbout_buf
    );
    
    --*****PLL*****
    plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
    generic map(
        BANDWIDTH => "OPTIMIZED",
        CLKFBOUT_MULT => CLKFBOUT_MULT,
        CLKFBOUT_PHASE => 0.000000,
        CLKIN1_PERIOD => CLKIN1_PERIOD,
        CLKIN2_PERIOD => 0.000000,
        CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
        CLKOUT0_DUTY_CYCLE => 0.500000,
        CLKOUT0_PHASE => 0.000000,
        CLKOUT1_DIVIDE => 1,
        CLKOUT1_DUTY_CYCLE => 0.500000,
        CLKOUT1_PHASE => 0.000000,
        CLKOUT2_DIVIDE => 1,
        CLKOUT2_DUTY_CYCLE => 0.500000,
        CLKOUT2_PHASE => 0.000000,
        CLKOUT3_DIVIDE => 1,
        CLKOUT3_DUTY_CYCLE => 0.500000,
        CLKOUT3_PHASE => 0.000000,
        CLKOUT4_DIVIDE => 1,
        CLKOUT4_DUTY_CYCLE => 0.500000,
        CLKOUT4_PHASE => 0.000000,
        CLKOUT5_DIVIDE => 1,
        CLKOUT5_DUTY_CYCLE => 0.500000,
        CLKOUT5_PHASE => 0.000000,
        COMPENSATION => "ZHOLD",
        DIVCLK_DIVIDE => DIVCLK_DIVIDE,
        IS_CLKINSEL_INVERTED => '0',
        IS_PWRDWN_INVERTED => '0',
        IS_RST_INVERTED => '0',
        REF_JITTER1 => 0.010000,
        REF_JITTER2 => 0.010000,
        STARTUP_WAIT => "FALSE"
    )
    port map (
        CLKFBIN => clkfbout_buf,
        CLKFBOUT => clkfbout,
        CLKIN1 => clk_in,
        CLKIN2 => '0',
        CLKINSEL => '1',
        CLKOUT0 => clk_out,
        CLKOUT1 => open,
        CLKOUT2 => open,
        CLKOUT3 => open,
        CLKOUT4 => open,
        CLKOUT5 => open,
        DADDR(6 downto 0) => B"0000000",
        DCLK => '0',
        DEN => '0',
        DI => (others => '0'),
        DO => open,
        DRDY => open,
        DWE => '0',
        LOCKED => open,
        PWRDWN => '0',
        RST => '0'
    );
    
end architecture;