diff --git a/xillinux-syn/vhdl/src/xillybus.v b/xillinux-syn/vhdl/src/xillybus.v index a8736f5..326451e 100644 --- a/xillinux-syn/vhdl/src/xillybus.v +++ b/xillinux-syn/vhdl/src/xillybus.v @@ -3,7 +3,7 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, - DDR_VRP, bus_clk, PS_GPIO, otg_oc, clk_100, vga4_red, vga4_green, vga4_blue, + DDR_VRP, bus_clk, otg_oc, clk_100, vga4_red, vga4_green, vga4_blue, vga_hsync, vga_vsync, user_clk, user_wren, user_wstrb, user_rden, user_rd_data, user_wr_data, user_addr, user_irq, user_r_debug_rden, user_r_debug_data, user_r_debug_empty, user_r_debug_eof, user_r_debug_open, @@ -83,7 +83,6 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk, inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; - inout [55:0] PS_GPIO; wire bus_rst_n; wire [31:0] S_AXI_AWADDR; wire S_AXI_AWVALID; @@ -177,7 +176,6 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk, .processing_system7_0_DDR_DQS_n ( DDR_DQS_n ), .processing_system7_0_DDR_VRN ( DDR_VRN ), .processing_system7_0_DDR_VRP ( DDR_VRP ), - .processing_system7_0_GPIO ( PS_GPIO ), .processing_system7_0_USB0_VBUS_PWRFAULT ( USB0_VBUS_PWRFAULT ), .xillybus_bus_clk ( bus_clk ), diff --git a/xillinux-syn/vhdl/src/xillydemo.vhd b/xillinux-syn/vhdl/src/xillydemo.vhd index 327864f..f8488c9 100644 --- a/xillinux-syn/vhdl/src/xillydemo.vhd +++ b/xillinux-syn/vhdl/src/xillydemo.vhd @@ -9,7 +9,6 @@ entity xillydemo is port ( clk_100 : IN std_logic; otg_oc : IN std_logic; - PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0); GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); vga4_blue : OUT std_logic_vector(3 DOWNTO 0); vga4_green : OUT std_logic_vector(3 DOWNTO 0); @@ -67,7 +66,6 @@ architecture sample_arch of xillydemo is DDR_VRN : INOUT std_logic; DDR_VRP : INOUT std_logic; MIO : INOUT std_logic_vector(53 DOWNTO 0); - PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0); DDR_WEB : OUT std_logic; GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); bus_clk : OUT std_logic; @@ -322,7 +320,6 @@ begin DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, MIO => MIO, - PS_GPIO => PS_GPIO, DDR_WEB => DDR_WEB, GPIO_LED => GPIO_LED, bus_clk => bus_clk, diff --git a/xillinux-syn/vivado-essentials/system.v b/xillinux-syn/vivado-essentials/system.v index 73da52f..34f53b2 100644 --- a/xillinux-syn/vivado-essentials/system.v +++ b/xillinux-syn/vivado-essentials/system.v @@ -80,7 +80,6 @@ module system ( output [7:0] xillyvga_0_vga_green, output [7:0] xillyvga_0_vga_blue, output xillyvga_0_vga_clk, - inout [55:0] processing_system7_0_GPIO, input processing_system7_0_USB0_VBUS_PWRFAULT, output xillybus_lite_0_user_clk_pin, output xillybus_lite_0_user_wren_pin, @@ -91,18 +90,6 @@ module system ( output [31:0] xillybus_lite_0_user_addr_pin, input xillybus_lite_0_user_irq_pin ); - - wire [55:0] gpio_tri_i, gpio_tri_o, gpio_tri_t; - genvar i; - - generate - for (i=0; i<56; i=i+1) - begin: gpio - assign gpio_tri_i[i] = processing_system7_0_GPIO[i]; - assign processing_system7_0_GPIO[i] = gpio_tri_t[i] ? 1'bz : - gpio_tri_o[i]; - end - endgenerate vivado_system vivado_system_i (.DDR_addr(processing_system7_0_DDR_Addr), @@ -126,9 +113,6 @@ vivado_system vivado_system_i .FIXED_IO_ps_clk(processing_system7_0_PS_CLK), .FIXED_IO_ps_porb(processing_system7_0_PS_PORB), .FIXED_IO_ps_srstb(processing_system7_0_PS_SRSTB), - .GPIO_0_tri_i(gpio_tri_i), - .GPIO_0_tri_o(gpio_tri_o), - .GPIO_0_tri_t(gpio_tri_t), .USBIND_0_port_indctl(), .USBIND_0_vbus_pwrfault(processing_system7_0_USB0_VBUS_PWRFAULT), .USBIND_0_vbus_pwrselect(), diff --git a/xillinux-syn/vivado-essentials/vivado_system/vivado_system.bd b/xillinux-syn/vivado-essentials/vivado_system/vivado_system.bd index 99b8989..9d6876c 100644 --- a/xillinux-syn/vivado-essentials/vivado_system/vivado_system.bd +++ b/xillinux-syn/vivado-essentials/vivado_system/vivado_system.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0x8FB8F73D359E6BB8", + "boundary_crc": "0xC016311925EE174E", "device": "xc7z020clg484-1", "name": "vivado_system", "synth_flow_mode": "None", @@ -313,10 +313,6 @@ "USBIND_0": { "mode": "Master", "vlnv": "xilinx.com:display_processing_system7:usbctrl_rtl:1.0" - }, - "GPIO_0": { - "mode": "Master", - "vlnv": "xilinx.com:interface:gpio_rtl:1.0" } }, "ports": { @@ -533,7 +529,7 @@ "value": "0" }, "PCW_EN_EMIO_GPIO": { - "value": "1" + "value": "0" }, "PCW_EN_EMIO_I2C0": { "value": "0" @@ -590,13 +586,7 @@ "value": "1" }, "PCW_GPIO_EMIO_GPIO_ENABLE": { - "value": "1" - }, - "PCW_GPIO_EMIO_GPIO_IO": { - "value": "56" - }, - "PCW_GPIO_EMIO_GPIO_WIDTH": { - "value": "56" + "value": "0" }, "PCW_GPIO_MIO_GPIO_ENABLE": { "value": "0" @@ -1616,6 +1606,12 @@ "xbar/S00_AXI" ] }, + "m00_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, "xbar_to_m00_couplers": { "interface_ports": [ "xbar/M00_AXI", @@ -1628,16 +1624,10 @@ "m01_couplers/M_AXI" ] }, - "xbar_to_m01_couplers": { + "xbar_to_m02_couplers": { "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" - ] - }, - "m00_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M02_AXI", + "m02_couplers/S_AXI" ] }, "m02_couplers_to_ps7_0_axi_periph": { @@ -1646,10 +1636,10 @@ "m02_couplers/M_AXI" ] }, - "xbar_to_m02_couplers": { + "xbar_to_m01_couplers": { "interface_ports": [ - "xbar/M02_AXI", - "m02_couplers/S_AXI" + "xbar/M01_AXI", + "m01_couplers/S_AXI" ] } }, @@ -1746,12 +1736,6 @@ "processing_system7_0/USBIND_0" ] }, - "processing_system7_0_GPIO_0": { - "interface_ports": [ - "GPIO_0", - "processing_system7_0/GPIO_0" - ] - }, "xillybus_ip_0_xillybus_S_AXI": { "interface_ports": [ "xillybus_S_AXI", diff --git a/xillinux-syn/vivado-essentials/xillydemo.xdc b/xillinux-syn/vivado-essentials/xillydemo.xdc index ec7e06e..aca6261 100644 --- a/xillinux-syn/vivado-essentials/xillydemo.xdc +++ b/xillinux-syn/vivado-essentials/xillydemo.xdc @@ -34,93 +34,7 @@ set_property -dict "PACKAGE_PIN AA19 IOSTANDARD LVCMOS33" [get_ports "vga_hsync" # IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin # placement doesn't match the one given by Digilent. -# GPIO pin to reset the USB OTG PHY - -set_property -dict "PACKAGE_PIN G17 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[0]"] - -# On-board OLED - -set_property -dict "PACKAGE_PIN U11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[1]"] -set_property -dict "PACKAGE_PIN U12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[2]"] -set_property -dict "PACKAGE_PIN U9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[3]"] -set_property -dict "PACKAGE_PIN U10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[4]"] -set_property -dict "PACKAGE_PIN AB12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[5]"] -set_property -dict "PACKAGE_PIN AA12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[6]"] - -# On-board LEDs. Note that only for LEDs are allocated, as opposed to -# Digilent's eight, and all placements that follow are shifted by four. -# There was no other choice, as the tools don't allow unplaced PS GPIO pins. - -set_property -dict "PACKAGE_PIN V22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[7]"] -set_property -dict "PACKAGE_PIN W22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[8]"] -set_property -dict "PACKAGE_PIN U19 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[9]"] -set_property -dict "PACKAGE_PIN U14 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[10]"] - -# On-board Slide Switches - -set_property -dict "PACKAGE_PIN F22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[11]"] -set_property -dict "PACKAGE_PIN G22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[12]"] -set_property -dict "PACKAGE_PIN H22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[13]"] -set_property -dict "PACKAGE_PIN F21 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[14]"] -set_property -dict "PACKAGE_PIN H19 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[15]"] -set_property -dict "PACKAGE_PIN H18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[16]"] -set_property -dict "PACKAGE_PIN H17 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[17]"] -set_property -dict "PACKAGE_PIN M15 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[18]"] - -# On-board Left, Right, Up, Down, and Select Pushbuttons - -set_property -dict "PACKAGE_PIN N15 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[19]"] -set_property -dict "PACKAGE_PIN R18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[20]"] -set_property -dict "PACKAGE_PIN T18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[21]"] -set_property -dict "PACKAGE_PIN R16 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[22]"] -set_property -dict "PACKAGE_PIN P16 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[23]"] - -# Pmod JA - -set_property -dict "PACKAGE_PIN Y11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[24]"] -set_property -dict "PACKAGE_PIN AA11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[25]"] -set_property -dict "PACKAGE_PIN Y10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[26]"] -set_property -dict "PACKAGE_PIN AA9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[27]"] -set_property -dict "PACKAGE_PIN AB11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[28]"] -set_property -dict "PACKAGE_PIN AB10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[29]"] -set_property -dict "PACKAGE_PIN AB9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[30]"] -set_property -dict "PACKAGE_PIN AA8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[31]"] - -# Pmod JB - -set_property -dict "PACKAGE_PIN W12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[32]"] -set_property -dict "PACKAGE_PIN W11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[33]"] -set_property -dict "PACKAGE_PIN V10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[34]"] -set_property -dict "PACKAGE_PIN W8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[35]"] -set_property -dict "PACKAGE_PIN V12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[36]"] -set_property -dict "PACKAGE_PIN W10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[37]"] -set_property -dict "PACKAGE_PIN V9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[38]"] -set_property -dict "PACKAGE_PIN V8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[39]"] - -# Pmod JC - -set_property -dict "PACKAGE_PIN AB7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[40]"] -set_property -dict "PACKAGE_PIN AB6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[41]"] -set_property -dict "PACKAGE_PIN Y4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[42]"] -set_property -dict "PACKAGE_PIN AA4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[43]"] -set_property -dict "PACKAGE_PIN R6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[44]"] -set_property -dict "PACKAGE_PIN T6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[45]"] -set_property -dict "PACKAGE_PIN T4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[46]"] -set_property -dict "PACKAGE_PIN U4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[47]"] - -# Pmod JD - -set_property -dict "PACKAGE_PIN V7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[48]"] -set_property -dict "PACKAGE_PIN W7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[49]"] -set_property -dict "PACKAGE_PIN V5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[50]"] -set_property -dict "PACKAGE_PIN V4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[51]"] -set_property -dict "PACKAGE_PIN W6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[52]"] -set_property -dict "PACKAGE_PIN W5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[53]"] -set_property -dict "PACKAGE_PIN U6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[54]"] -set_property -dict "PACKAGE_PIN U5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[55]"] - # Pin for detecting USB OTG over-current condition - set_property -dict "PACKAGE_PIN L16 IOSTANDARD LVCMOS33" [get_ports "otg_oc"] # Pins connected to sound chip