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* Fix scaler

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- Add generic to select between signed and unsigned
This commit is contained in:
Greek 2020-04-29 17:34:16 +02:00
parent 89182e8060
commit 29036ded6f
2 changed files with 39 additions and 18 deletions
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49
src/mult.vhd
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@ -12,7 +12,8 @@ entity mult is
generic (
A_WIDTH : integer := 12;
B_WIDTH : integer := 4;
PIPELINE_STAGES : integer := 1
PIPELINE_STAGES : integer := 1;
UNSIGNED : boolean := true
);
port (
clk : in std_logic;
@ -27,19 +28,37 @@ architecture arch of mult is
begin
MULT_MACRO_inst : MULT_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
WIDTH_A => A_WIDTH, -- Multiplier A-input bus width, 1-25
WIDTH_B => B_WIDTH) -- Multiplier B-input bus width, 1-18
port map (
P => P, -- Multiplier ouput bus, width determined by WIDTH_P generic
A => A, -- Multiplier input A bus, width determined by WIDTH_A generic
B => B, -- Multiplier input B bus, width determined by WIDTH_B generic
CE => '1', -- 1-bit active high input clock enable
CLK => clk, -- 1-bit positive edge clock input
RST => '0' -- 1-bit input active high reset
);
mult_gen : if (UNSIGNED = true) generate
MULT_MACRO_inst : MULT_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
WIDTH_A => A_WIDTH+1, -- Multiplier A-input bus width, 1-25
WIDTH_B => B_WIDTH+1) -- Multiplier B-input bus width, 1-18
port map (
P(A_WIDTH+B_WIDTH+1 downto A_WIDTH+B_WIDTH) => open,
P(A_WIDTH+B_WIDTH-1 downto 0) => P,
A => "0" & A,
B => "0" & B,
CE => '1',
CLK => clk,
RST => '0'
);
else generate
MULT_MACRO_inst : MULT_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-4
WIDTH_A => A_WIDTH, -- Multiplier A-input bus width, 1-25
WIDTH_B => B_WIDTH) -- Multiplier B-input bus width, 1-18
port map (
P => P,
A => A,
B => B,
CE => '1',
CLK => clk,
RST => '0'
);
end generate;
end architecture;

6
src/scaler.vhd
View File

@ -26,7 +26,8 @@ architecture arch of scaler is
generic (
A_WIDTH : integer := 12;
B_WIDTH : integer := 4;
PIPELINE_STAGES : integer := 1
PIPELINE_STAGES : integer := 1;
UNSIGNED : boolean := true
);
port (
clk : in std_logic;
@ -42,7 +43,8 @@ begin
generic map(
A_WIDTH => DATA_WIDTH,
B_WIDTH => FACTOR_WIDTH,
PIPELINE_STAGES => PIPELINE_STAGES
PIPELINE_STAGES => PIPELINE_STAGES,
UNSIGNED => true
)
port map(
clk => clk,