From 365e95d3a08a910cd787c5a971fc9a178709bfca Mon Sep 17 00:00:00 2001 From: John Ring Date: Sun, 28 Mar 2021 15:24:00 +0200 Subject: [PATCH] Update 'Readme.md' --- Readme.md | 58 +++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 19 deletions(-) diff --git a/Readme.md b/Readme.md index de22f35..e1e4582 100644 --- a/Readme.md +++ b/Readme.md @@ -33,10 +33,11 @@ Zedboard Pin | Description --------------------------------|--------------- JC1 PMOD Connector (Upper Row) | PMOD-AD1 Board JD1 PMOD Connector (Upper Row) | PMOD-DA3 Board -JA1 PMOD JA1 Pin | Optional External Clock [NOTE: Clk has to be connected in VHDL and PLL has to be reconfigured accordingly] -JA1 PMOD JA4 Pin | External SYNC Pulse [NOTE: if pin is left unconnected (floating), it will register as a pulse] -SW7 | Standby / Write Mode (Allows xillinux to write configuration) -LED7 | Standby Status +JA1 PMOD JA4 Pin | (Optional) External Clock [NOTE: Clk has to be connected in VHDL and PLL has to be reconfigured accordingly] +JA1 PMOD JA1 Pin | External SYNC Pulse [NOTE: if pin is left unconnected (floating), it will register as a pulse] +SW7 | Standby / Operation Mode (Allows xillinux to write configuration if in Standby Mode) +LED7 | Standby Mode Status (ON if FPGA in Standby Mode) +LED6 | Sync Status (ON if Sync Pulse was registered) BTNC | Global reset BTNU | Debug value reset @@ -45,20 +46,36 @@ BTNU | Debug value reset ![alt text](feedback.png "Feed back Loop") -This project implements the above feedback loop in FPGA logic. The components of the feedback loop are analysed below: +This project implements the above feedback loop in FPGA logic. The components of the feedback loop are detailed below: * **ADC** The ADC (PMOD-AD1) is capable of operating at a maximum frequency of 20 MHz, and converting an analog signal every 18 clock cycles (ca 1.1 MHz Sampling Frequency). All PMOD Connectors on the Zedboard are fixed to 3.3V, hence the ADC can convert analog signals in the range 0V-3.3V to 12-bits. * **DAC** The DAC (PMOD-DA3) is capable of operating at a maximum frequency of 50 MHz, and converting a digital signal every 16 clock cycles (ca 1.25 MHz). The DAC uses an internal 2.5 V Voltage reference (uncorrelated to the used VCC Voltage), and can thus convert 16-bits to 0V-2.5V. * **DELAY LINE** The delay line allows to delay the converted ADC values by a pre-specified amount of clock cycles. -* **SCALER** The scaler allows the converted ADC values to be downscaled. It uses a 5-bit multiplication factor that is intepreted as a 1Q4 (1-Bit Integer, 4-Bit Fractional) fixed point number. Note that the factor should only take values between 0 and 16 (decimal), as due to the internal connection (truncat highest bit) using higher numbers can (and will) result to overflow conditions. -e.g. A value of 16(decimal) is intepreted as scaling by 1, a value of 15 (decimal) is intepreted as scaling by 0.9375, and a value of 8 is is intepreted as scaling by 0.5. -* **ADD/SUB** The ADD/SUB allows to either add or subtract the scaler output from the MUX output. (Allowing to either implement a positive, or negative feedback loop). -* **MUX** The MUX selects between the second ADC channel or zero (GND), allowing a "neutral" feedback. +* **SCALER** The scaler allows the converted ADC values to be scaled. It uses a 5-bit multiplication factor that is intepreted as a Q1.4 (1-Bit Integer, 4-Bit Fractional) fixed point number. The signals are scaled with respect to the configured *Bias Offset*. Note that when scaling up the signal may be capped due to overflow conditions in the internal representation. See *Overflow Considerations* +e.g. A value of 16(decimal) is intepreted as scaling by 1, a value of 15(decimal) is intepreted as scaling by 0.9375, and a value of 24(decimal) is is intepreted as scaling by 1.5. +* **ADD/SUB** The ADD/SUB allows to either add or subtract the input signals (Sig0 +/- Sig1). +* **INV** The INV inverts the input signal 0. The negated signal 0 is used if the loop is in *Single Input Mode* configured as *Negative Feedback*. +* **MUX** The MUX selects between the signals, allowing either input signal 0 passthrough, or feedback result to be outputted. ## Timing Considerations The whole system is clocked at 20 MHz (highest supported frequency of ADC). -The *ADD/SUB* and *Scaler* have a 1-stage pipeline, meaning that if the *Delay Line* is configured with 0 delay, the feedback loop follows the 18 clock cycle cadence of the ADC without additional delay. -In order to re-align the inputs of the *ADD/SUB*, the second channel of the ADC is latched (delayed) for one clock cycle (not shown in diagram) to compensate for the Scaler pipeline. +The logic between the ADC and DAC is implemented in a 2-stage pipeline format, so that the whole feedback loop follows the 18 clock cycle cadence of the ADC. + +## Bias Offset + +Because both the used ADC and DAC are unipolar, signals have to be biased accordingly on input and output. In order to have correct processing of biased signals, the bias offset has to be configured in the *typedef_package*. +The default configured bias is 2048 (1.65V), and is in the middle of the ADC input range. + +## Input/Output Voltage Range + +Because the input range is 0-3.3V but the output range is 0-2.5V, the output signal amplitude is approx. 75% of the input signal amplitude when using a scaling of 1 (16 in config). In order to compensate for that you have to scale by a factor of 1.32 (21 in config). Note that when using the factor 1.32 to compensate this reduces the effective input range to 0.4-2.9V (with default bias). + +## Overflow Considerations + +Due to the internal representation signals may be capped to their maximum value in-between arithmetic operations, leading to unwanted signal distortion in the output. The user has to take into account that no signal is exceeding the output voltage range. +e.g. The below simulation shows a negative feedback loop, where Input 2 is scaled by 1 and subtracted by Input 1 scaled by 1.32. Because the scaling of Input 1 is capped before the subtraction of Input 2 we get an unwanted distortion. + +![alt text](overflow_issue.png "Overflow Issue") # USAGE @@ -74,27 +91,30 @@ In order to re-align the inputs of the *ADD/SUB*, the second channel of the ADC ## Boot The UART should automatically connect to a root shell (after U-Boot did it's thing). The root user has no password set. -The system should be halted (using the `halt` or `shutdown now` command) before powering off the board. +The system should be halted (using the `halt` or `shutdown now` command) before powering off the board, to prevent SD Card corruption. ## Configuration The FPGA logic contains a configuration memory with a pre-defined (changable in `typedef_package.vhd`) number of configuration "slots". Each slot contains the configuration for the feedback loop (Delay Line clock count, scaler factor, add/sub selection, MUX selection), and a timestamp. The timestamp defines the number of clock cycles from the rising edge of the SYNC pulse signal after which the configuration described by the slot is applied. It makes sense for the first configuration slot to have a timestamp of 0. The slots are processed in write order, and not in timestamp order. (Thus slots should have increasing timestamp values). NOTE: It is valid for a configuration slot to have a timestamp lower than the previous. The slot will be applied for at least 1 clock cycle before the next slot can be applied. -The `xillybus_config` linux device file is used to write to the configuration memory of the FPGA. Note that the standby switch has to be enabled (Standby status led on). As long as the standby switch is enabled, the feedback loop is held in reset. +The `xillybus_config` linux device file is used to write to the configuration memory of the FPGA. Note that the standby switch has to be enabled (Standby status led on) in order to write the configuration to the FPGA. As long as the standby switch is enabled, the feedback loop is held in reset. -The `write_config.c` C program can be used to write the configuration memory of the FPGA. +The `write_config.c` C program can be used to write the configuration onto the FPGA. e.g. `./write_config config /dev/xillybus_config` ### Config File Each line of this file defines a configuration slot and consists of integer numbers delimited by white spaces in the following order: -ADDSUB_MODE ADD_INPUT_MUX DELAY FACTOR TIMESTAMP +ADDSUB_MODE ADD_INPUT_MUX DELAY FACTOR0 FACTOR1 TIMESTAMP -* ADDSUB_MODE: Select feedback mode (0=negative, 1=positive) -* ADD_INPUT_MUX: Select feedback input (0=GND[only ADC Input 1], 1=ADC Input 2[Both ADC inputs are used]) -* DELAY: Clock cycle counts (50 ns period) to delay the feedback signal [0-255] -* FACTOR: Multiplication factor to apply to the feedback signal [0-16] (NOTE: Integer is intepreted as a 1Q4 Fixed Point Number!) +* ADDSUB_MODE: Select feedback mode (0=Negative, 1=Positive) +* ADD_INPUT_MUX: Select feedback input (0=Single Input Mode [ADC0], 1=Double Input Mode) +* DELAY: Clock cycles counts (50 ns period) to delay the feedback signal [0-65535] +* FACTOR0: Multiplication factor to apply to the ADC Signal0 [0-32] (NOTE: Integer is intepreted as a Q1.4 Fixed Point Number!) +* FACTOR1: Multiplication factor to apply to the ADC Signal1 [0-32] (NOTE: Integer is intepreted as a Q1.4 Fixed Point Number!) * TIMESTAMP: Defines the clock count number from the sync pulse from which on the configurations settings will be applied. [32-bit unsigned integer] +NOTE: In *Single Input Mode* the feedback mode (Positive/Negative) selects if the input signal 0 is passed through as is, or negated. + ## Debug The FPGA logic allows debug values to be sent to the Linux via the `xillybus_debug` device file.