From 3f111508c110c92a4cb1aca4dd2ee543b1ee7bff Mon Sep 17 00:00:00 2001 From: Greek64 Date: Wed, 24 Mar 2021 10:52:36 +0100 Subject: [PATCH] Day 2 Labor Fixes --- src/feedback_loop.vhd | 157 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 127 insertions(+), 30 deletions(-) diff --git a/src/feedback_loop.vhd b/src/feedback_loop.vhd index 04af8d7..21950c4 100644 --- a/src/feedback_loop.vhd +++ b/src/feedback_loop.vhd @@ -136,13 +136,18 @@ architecture arch of feedback_loop is ); end component; + --*****CONSTANT DECLARATION***** + constant CONST_MAX : unsigned(DAC_DATA_WIDTH-1 downto 0) := (others => '1'); + constant CONST_HALF : unsigned(DAC_DATA_WIDTH-1 downto 0) := (DAC_DATA_WIDTH-1 => '1', others => '0'); + --*****SIGNAL DECLARATION***** signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal inputA_wide, inputB_wide : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal scaler_out, scaler_offset : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); + signal scaler_1_out, scaler_2_out, scaler_offset_1, scaler_offset_2 : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); signal scaler_done, addsub_done : std_logic := '0'; - signal offset_factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal offset_factor, tmp : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); begin @@ -183,7 +188,7 @@ begin addsub_offset_inst : addsub generic map( - PIPELINE_STAGES => 1, + PIPELINE_STAGES => 0, DATA_WIDTH => FACTOR_WIDTH ) port map( @@ -193,11 +198,14 @@ begin cap => '0', A => (FACTOR_WIDTH-1 => '1', others => '0'), B => factor, - RES => offset_factor + RES => tmp ); + --TODO: Fix me + offset_factor <= tmp when (factor(FACTOR_WIDTH-1) = '0') else ("0" & factor(FACTOR_WIDTH-2 downto 0)); + --*****STAGE III***** - scaler_A_inst : scaler + scaler_1_inst : scaler generic map( DATA_WIDTH => ADC_DATA_WIDTH, FACTOR_WIDTH => FACTOR_WIDTH, @@ -207,10 +215,23 @@ begin clk => clk, data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), factor => factor, - data_out => scaler_out + data_out => scaler_1_out ); - scaler_offset_inst : scaler + scaler_2_inst : scaler + generic map( + DATA_WIDTH => ADC_DATA_WIDTH, + FACTOR_WIDTH => FACTOR_WIDTH, + PIPELINE_STAGES => 1 + ) + port map( + clk => clk, + data_in => adc_data2, + factor => "10101", --1.32 + data_out => scaler_2_out + ); + + scaler_offset_1_inst : scaler generic map( DATA_WIDTH => ADC_DATA_WIDTH, FACTOR_WIDTH => FACTOR_WIDTH, @@ -220,7 +241,20 @@ begin clk => clk, data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), factor => offset_factor, - data_out => scaler_offset + data_out => scaler_offset_1 + ); + + scaler_offset_2_inst : scaler + generic map( + DATA_WIDTH => ADC_DATA_WIDTH, + FACTOR_WIDTH => FACTOR_WIDTH, + PIPELINE_STAGES => 1 + ) + port map( + clk => clk, + data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), + factor => "00101", --0.32 + data_out => scaler_offset_2 ); process(clk) @@ -245,7 +279,7 @@ begin end if; end process; - addsub_instB : addsub + addsub_1_inst : addsub generic map( PIPELINE_STAGES => 0, DATA_WIDTH => DAC_DATA_WIDTH+1 @@ -255,18 +289,50 @@ begin reset => reset, mode => not factor(FACTOR_WIDTH-1), cap => '0', - A => scaler_out, - B => scaler_offset, - RES(DAC_DATA_WIDTH) => open, --Truncate Carry Bit - RES(DAC_DATA_WIDTH-1 downto 0) => inputB + A => scaler_1_out, + B => scaler_offset_1, + RES => inputB_wide ); + addsub_2_inst : addsub + generic map( + PIPELINE_STAGES => 0, + DATA_WIDTH => DAC_DATA_WIDTH+1 + ) + port map( + clk => clk, + reset => reset, + mode => '0', + cap => '0', + A => scaler_2_out, + B => scaler_offset_2, + RES => inputA_wide + ); + + cap_B_prc : process(all) + begin + if (inputB_wide(DAC_DATA_WIDTH) = '1') then + if (factor(FACTOR_WIDTH-1) = '1') then + inputB <= (others => '0'); + else + inputB <= (others => '1'); + end if; + else + inputB <= inputB_wide(DAC_DATA_WIDTH-1 downto 0); + end if; + end process; + --*****STAGE IV***** mux: process(all) begin if (add_input_mux = '1') then - inputA <= latch_out & "0000"; + if (inputA_wide(DAC_DATA_WIDTH) = '1') then + --TODO: CAP Needed? + inputA <= (others => '0'); + else + inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0); + end if; else if (addsub_mode = '1') then inputA <= (others => '0'); @@ -276,20 +342,51 @@ begin end if; end process; - addsub_instA : addsub - generic map( - PIPELINE_STAGES => 1, - DATA_WIDTH => DAC_DATA_WIDTH - ) - port map( - clk => clk, - reset => reset, - mode => addsub_mode, - cap => add_input_mux, - A => inputA, - B => inputB, - RES => addsub_out - ); + add_sub_prc : process (all) + variable tmp_res : unsigned(inputB'length-1 downto 0) := (others => '0'); + begin + if rising_edge(clk) then + if (reset = '1') then + addsub_out <= (others => '0'); + else + -- Both Inputs + if (add_input_mux = '1') then + -- ADD + if (addsub_mode = '1') then + tmp_res := unsigned(inputB) + unsigned(inputA); + -- SUB + else + tmp_res := unsigned(inputB) - unsigned(inputA); + end if; + addsub_out <= std_logic_vector(tmp_res + CONST_HALF); + -- Single Input + else + -- ADD + if (addsub_mode = '1') then + addsub_out <= inputB; + -- SUB + else + addsub_out <= std_logic_vector(CONST_MAX - unsigned(inputB)); + end if; + end if; + end if; + end if; + end process; + +-- addsub_instA : addsub +-- generic map( +-- PIPELINE_STAGES => 1, +-- DATA_WIDTH => DAC_DATA_WIDTH +-- ) +-- port map( +-- clk => clk, +-- reset => reset, +-- mode => addsub_mode, +-- cap => add_input_mux, +-- A => inputA, +-- B => inputB, +-- RES => addsub_out +-- ); process(clk) begin @@ -343,8 +440,8 @@ begin end if; -- SCALER MAX VALUES elsif (scaler_done = '1') then - if (to_integer(unsigned(scaler_out)) >= to_integer(unsigned(scaler_max))) then - scaler_max <= scaler_out; + if (to_integer(unsigned(scaler_1_out)) >= to_integer(unsigned(scaler_max))) then + scaler_max <= scaler_1_out(DAC_DATA_WIDTH-1 downto 0); end if; end if; end if;