diff --git a/overflow_issue.png b/overflow_issue.png
new file mode 100644
index 0000000..bc5363d
Binary files /dev/null and b/overflow_issue.png differ
diff --git a/src/feedback_loop.vhd b/src/feedback_loop.vhd
index d598eac..d3d2a25 100644
--- a/src/feedback_loop.vhd
+++ b/src/feedback_loop.vhd
@@ -119,8 +119,7 @@ architecture arch of feedback_loop is
     end component;
     
     --*****CONSTANT DECLARATION*****
-    constant CONST_MAX  : unsigned(DAC_DATA_WIDTH-1 downto 0) := (others => '1');
-    constant CONST_HALF : unsigned(DAC_DATA_WIDTH-1 downto 0) := (DAC_DATA_WIDTH-1 => '1', others => '0');
+    constant CONST_BIAS : unsigned(DAC_DATA_WIDTH-1 downto 0) := unsigned(BIAS_OFFSET & "0000");
     constant FACTOR_ONE : unsigned(FACTOR_WIDTH-1 downto 0) := (FACTOR_WIDTH-1 => '1', others => '0');
     
     --*****SIGNAL DECLARATION*****
@@ -251,7 +250,7 @@ begin
         )
         port map(
             clk         => clk,
-            data_in     => (ADC_DATA_WIDTH-1 => '0', others => '1'),
+            data_in     => BIAS_OFFSET,
             factor      => offset_factor1,
             data_out    => scaler_offset_1
         );
@@ -299,7 +298,7 @@ begin
         )
         port map(
             clk         => clk,
-            data_in     => (ADC_DATA_WIDTH-1 => '0', others => '1'),
+            data_in     => BIAS_OFFSET,
             factor      => offset_factor2,
             data_out    => scaler_offset_2
         );
@@ -358,7 +357,7 @@ begin
                     -- ADD
                     if (addsub_mode_latch = '1') then
                         tmp_res := unsigned("00" & data1_D) + unsigned("00" & data2_D);
-                        tmp_res := tmp_res + ("00" & CONST_HALF);
+                        tmp_res := tmp_res + ("00" & CONST_BIAS);
                         -- Overflow
                         if (tmp_res(DAC_DATA_WIDTH+1) = '1') then
                             data_out  <= (others => '1');
@@ -371,7 +370,7 @@ begin
                     -- SUB
                     else
                         tmp_res := unsigned("00" & data1_D) - unsigned("00" & data2_D);
-                        tmp_res := tmp_res + ("00" & CONST_HALF);
+                        tmp_res := tmp_res + ("00" & CONST_BIAS);
                         -- Underflow
                         if (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "11") then
                             data_out  <= (others => '0');
diff --git a/src/typedef_package.vhd b/src/typedef_package.vhd
index 42d45cf..7ad89ea 100644
--- a/src/typedef_package.vhd
+++ b/src/typedef_package.vhd
@@ -21,6 +21,8 @@ package typedef_package is
     
     constant TIMESTAMP_WIDTH : integer := 32;
     
+    constant BIAS_OFFSET : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (ADC_DATA_WIDTH-1 => '1', others => '0');
+    
     --XILLYBUS
     constant DEBUG_FIFO_DATA_WIDTH  : integer := 32;
     constant DEBUG_FIFO_DEPTH       : integer := 16;