* Add Project Description and Documentation (Readme.md)
* Add diagram * Modify counters of PMOD-AD1 and PMOD-DA3 controllers to use less bits * Increase factor width to 5 bits - Highest bit is truncated * Add download directory to git repo
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doc/*.pdf filter=lfs diff=lfs merge=lfs -text
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download/* filter=lfs diff=lfs merge=lfs -text
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#Ignore List
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/syn/**
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/modelsim/**
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/download/**
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#Unignore Directories (Needed to unignore files in Subdirectories)
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Readme.md
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Readme.md
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# Project Structure
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* **doc** Contains all releavnt documentation need for this project
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* **download** Contains various files downloaded for this project
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* **corebundle-mst_lab.zip** First version of Custom Xillybus IP Core implementation generated by "IP Core Factory"
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* `xillybus_debug`: Upstream, 32-bits, 256 B/s, General Purpose
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* `xillybus_config`: Downstream, 16-bits, 204.8 kB/s, Address/Data Interface (16 address bits)
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* `xillybus_audio`: Upstream/Downstream, 32-bits, 204.8 kB/s, Data acquisition/Playback
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* `xillybus_smb`: Upstream/Downstream, 8-bits, 10.24 kB/s, Command and Status
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* **corebundle-mst_lab2.zip** Second version of Custom Xillybus IP Core implementation generated by "IP Core Factory". Currently in use
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* `xillybus_debug`: Upstream, 32-bits, 256 B/s, General Purpose
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* `xillybus_config`: Downstream, 32-bits, 204.8 kB/s, Address/Data Interface (16 address bits)
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* `xillybus_audio`: Upstream/Downstream, 32-bits, 204.8 kB/s, Data acquisition/Playback
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* `xillybus_smb`: Upstream/Downstream, 8-bits, 10.24 kB/s, Command and Status
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* **CypressDriverInstaller_1.exe** Windows drivers for zedboard USB-UART
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* **xillinux-2.0.img.gz** Xillinux SD Card image
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* **xillinux-eval-zedboard-2.0c.zip** Zedboard Xillybus demo project
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* **modelsim** Contains .do files for modelsim simulation
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* **src** Constains the actual vhdl source files for this project
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* **sim** Contains the simulation testbenches
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* **UNUSED** Contains (partially) implemented logic that is not used in the final version
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* **sw** Contains the software that allows to communicate with the FPGA logic from Linux through the Xillybus API
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* **syn** Contains a zedboard Vivado test project used to test various parts of the VHDL implementation
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* **xillinux-syn** Contains the final Vivado project implementing the xillybus IP core, ZYNQ System, and instantiating our FPGA logic. This is a modified version of the xillybus-demo project
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* **vivado** Contains the actual Vivado Project file
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* **vhdl/src** Cotains the project top entity (`xillydemo.vhd`). The FPGA logic in instantiated in this file
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* The rest of the directories are taken verbatim from the demo project and are necessary for all the peripheral components used by xillinux.
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# Board Mapping
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JC1 PMOD Connector (Upper Row) | PMOD-AD1 Board
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JD1 PMOD Connector (Upper Row) | PMOD-DA3 Board
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JA1 PMOD JA1 Pin | Optional External Clock [NOTE: Clk has to be connected in VHDl and PLL has to be reconfigured accordingly]
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JA1 PMOD JA4 Pin | External SYNC Pulse [NOTE: if pin is left unconnected (floating), it will register as a pulse]
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SW7 | Standby / Write Mode (Allows xillinux to write configuration)
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LED7 | Standby Status
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BTNC | Global reset
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BTNU | Debug value reset
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# Project Description
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This project implements the above feedback loop in FPGA logic. The components of the feedback loop are analysed below:
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* **ADC** The ADC (PMOD-AD1) is capable of operating at a maximum frequency of 20 MHz, and converting an analog signal every 18 clock cycles (ca 1.1 MHz Sampling Frequency). All PMOD Connectors on the Zedboard are fixed to 3.3V, hence the ADC can convert analog signals in the range 0V-3.3V to 12-bits.
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* **ADC** The DAC (PMOD-DA3) is capable of operating at a maximum frequency of 50 MHz, and converting a digital signal every 16 clock cycles (ca 1.25 MHz). The DAC uses an internal 2.5 V Voltage reference (uncorrelated to the used VCC Voltage), and can thus convert 16-bits to 0V-2.5V.
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* **DELAY LINE** The delay line allows to delay the converted ADC values by a pre-specified amount of clock cycles.
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* **SCALER** The scaler allows the converted ADc values to be downscaled. It uses a 5-bit multiplication factor that is intepreted as a 1Q4 (1-Bit Integer, 4-Bit Fractional) fixed point number. Note that the factor should only take values between 0 and 16 (decimal), as due to the internal connection (truncat highest bit) using higher numbers can (and will) result to overflow conditions.
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e.g. A value of 16(decimal) is intepreted as scaling by 1, a value of 15 (decimal) is intepreted as scaling by 0.9375, and a value of 8 is is intepreted as scaling by 0.5.
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* **ADD/SUB** The ADD/SUB allows to either add or subtract the scaler output from the MUX output. (Allowing to either implement a positive, or negative feedback loop).
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* **MUX** The MUX selects between the second ADC channel or zero (GND), allowing a "neutral" feedback.
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## Timing Considerations
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The whole system is clocked at 20 MHz (highest supported frequency of ADC).
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The *ADD/SUB* and *Scaler* have a 1-stage pipeline, meaning that if the *Delay Line* is configured with 0 delay, the feedback loop follows the 18 clock cycle cadence of the ADC without additional delay.
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In order to re-align the inputs of the *ADD/SUB*, the second channel of the ADC is latched (delayed) for one clock cycle (not shown in diagram).
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# USAGE
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## Preperation
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* Write the image contained in `download/xillinux-2.0.img.gz` to the SD card.
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* Copy the files in the `xillinux-syn/bootfiles` directory into the first partition of the SD Card
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* Open the Vivado Project under `xillinux-syn/vivado/xillydemo.xpr` and generate the Bitstreamfile
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* Copy the Bitstreamfile into the first partition of the SD Card
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* Follow the instruction in Chapter 4 of `doc/Xillybus/xillybus_getting_started_zynq.pdf` to set the correct switch/jumper positions
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* Connect SD Card to Zedboard
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* Connect the USB cable to the *UART* port. The UART uses the 8N1 format and a baudrate of 115200.
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* Optionally you can also connect VGA monitor, audio, keyboard/mouse (using USB-OTG), as the xillinux is a fully fledged Linux OS.
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## Boot
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The UART should automatically connect to a root shell (after U-Boot did it's thing). The root user has no password set.
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The system should be halted (using the `halt` or `shutdown now` command) before powering off the board.
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## Configuration
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The FPGA logic contains a configuration memory with a pre-defined (changable in `typedef_package.vhd`) number of configuration "slots". Each slot contains the configuration for the feedback loop (Delay Line clock count, scaler factor, add/sub selection, MUX selection), and a timestamp. The timestamp defines the number of clock cycles from the rising edge of the SYNC pulse signal after which the configuration described by the slot is applied. It makes sense for the first configuration slot to have a timestamp of 0. The slots are processed in write order, and not in timestamp order. (Thus slots should have increasing timestamp values).
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NOTE: It is valid for a configuration slot to have a timestamp lower than the previous. The slot will be applied for at least 1 clock cycle before the next slot can be applied.
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The `xillybus_config` linux device file is used to write to the configuration memory of the FPGA. Note that the standby switch has to be enabled (Standby status led on). As long as the standby switch is enabled, the feedback loop is held in reset.
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The `write_config.c` C program can be used to write the configuration memory of the FPGA.
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e.g. `./write_config config /dev/xillybus_config`
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### Config File
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Each line of this file defines a configuration slot and consists of integer numbers delimited by white spaces in the following order:
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ADDSUB_MODE ADD_INPUT_MUX DELAY FACTOR TIMESTAMP
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* ADDSUB_MODE: Select feedback mode (0=negative, 1=positive)
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* ADD_INPUT_MUX: Select feedback input (0=GND[only ADC Input 1], 1=ADC Input 2[Both ADC inputs are used])
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* DELAY: Clock cycles counts (50 ns period) to delay the feedback signal [0-255]
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* FACTOR: Multiplication factor to apply to the feedback signal [0-16] (NOTE: Integer is intepreted as a 1Q4 Fixed Point Number!)
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* TIMESTAMP: Defines the clock count number from the sync pulse from which on the configurations settings will be applied. [32-bit unsigned integer]
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## Debug
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The FPGA logic allows debug values to be sent to the Linux via the `xillybus_debug` device file.
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Currently the FPGA logic sends every second the max values of the both ADC channels, Scaler output, and DAC. The max values can be externally reset (see Mapping).
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The `read_debug.c` C program can be used to read the debug values. Since the program enters an endless loop, a signal handler has beeen implemented and the program can be safely terminated with `CTRL-C` and co.
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e.g. `./read_debug /dev/xillybus_debug`
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375
doc/zedboard_master_XDC_RevC_D_v3.xdc
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375
doc/zedboard_master_XDC_RevC_D_v3.xdc
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# ----------------------------------------------------------------------------
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# _____
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# / \
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# /____ \____
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# / \===\ \==/
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# /___\===\___\/ AVNET Design Resource Center
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# \======/ www.em.avnet.com/drc
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# \====/
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# ----------------------------------------------------------------------------
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#
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# Created With Avnet UCF Generator V0.4.0
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# Date: Saturday, June 30, 2012
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# Time: 12:18:55 AM
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#
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# This design is the property of Avnet. Publication of this
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# design is not authorized without written consent from Avnet.
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#
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# Please direct any questions to:
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# ZedBoard.org Community Forums
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# http://www.zedboard.org
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#
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# Disclaimer:
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# Avnet, Inc. makes no warranty for the use of this code or design.
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# This code is provided "As Is". Avnet, Inc assumes no responsibility for
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# any errors, which may appear in this code, nor does it make a commitment
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||||
# to update the information contained herein. Avnet, Inc specifically
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||||
# disclaims any implied warranties of fitness for a particular purpose.
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# Copyright(c) 2012 Avnet, Inc.
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# All rights reserved.
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#
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# ----------------------------------------------------------------------------
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#
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# Notes:
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#
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# 10 August 2012
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# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
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# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
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# By default, Vadj is expected to be set to 1.8V but if a different
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# voltage is used for a particular design, then the corresponding IO
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# standard within this UCF should also be updated to reflect the actual
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# Vadj jumper selection.
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#
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# 09 September 2012
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# Net names are not allowed to contain hyphen characters '-' since this
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# is not a legal VHDL87 or Verilog character within an identifier.
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||||
# HDL net names are adjusted to contain no hyphen characters '-' but
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||||
# rather use underscore '_' characters. Comment net name with the hyphen
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||||
# characters will remain in place since these are intended to match the
|
||||
# schematic net names in order to better enable schematic search.
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||||
#
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# 17 April 2014
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# Pin constraint for toggle switch SW7 was corrected to M15 location.
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||||
#
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||||
# 16 April 2015
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||||
# Corrected the way that entire banks are assigned to a particular IO
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||||
# standard so that it works with more recent versions of Vivado Design
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||||
# Suite and moved the IO standard constraints to the end of the file
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# along with some better organization and notes like we do with our SOMs.
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||||
#
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# 6 June 2016
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# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
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#
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#
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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# Audio Codec - Bank 13
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# ----------------------------------------------------------------------------
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set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
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set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
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set_property PACKAGE_PIN Y8 [get_ports {AC_GPIO0}]; # "AC-GPIO0"
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set_property PACKAGE_PIN AA7 [get_ports {AC_GPIO1}]; # "AC-GPIO1"
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set_property PACKAGE_PIN AA6 [get_ports {AC_GPIO2}]; # "AC-GPIO2"
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set_property PACKAGE_PIN Y6 [get_ports {AC_GPIO3}]; # "AC-GPIO3"
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set_property PACKAGE_PIN AB2 [get_ports {AC_MCLK}]; # "AC-MCLK"
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set_property PACKAGE_PIN AB4 [get_ports {AC_SCK}]; # "AC-SCK"
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set_property PACKAGE_PIN AB5 [get_ports {AC_SDA}]; # "AC-SDA"
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# ----------------------------------------------------------------------------
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# Clock Source - Bank 13
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# ----------------------------------------------------------------------------
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set_property PACKAGE_PIN Y9 [get_ports {GCLK}]; # "GCLK"
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# ----------------------------------------------------------------------------
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# JA Pmod - Bank 13
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# ----------------------------------------------------------------------------
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set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
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set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
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set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
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set_property PACKAGE_PIN Y10 [get_ports {JA3}]; # "JA3"
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set_property PACKAGE_PIN AA9 [get_ports {JA4}]; # "JA4"
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set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
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set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
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set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
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||||
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||||
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||||
# ----------------------------------------------------------------------------
|
||||
# JB Pmod - Bank 13
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||||
# ----------------------------------------------------------------------------
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||||
set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
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set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
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set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
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set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
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||||
set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
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||||
set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
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||||
set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
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set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
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||||
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||||
# ----------------------------------------------------------------------------
|
||||
# JC Pmod - Bank 13
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||||
# ----------------------------------------------------------------------------
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set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
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set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
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||||
set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
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||||
set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
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||||
set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
|
||||
set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
|
||||
set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
|
||||
set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
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||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JA Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
|
||||
set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
|
||||
set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
|
||||
set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
|
||||
set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
|
||||
set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
|
||||
set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
|
||||
set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# OLED Display - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
|
||||
set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
|
||||
set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
|
||||
set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
|
||||
set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
|
||||
set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# HDMI Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
|
||||
set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
|
||||
set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
|
||||
set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
|
||||
set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
|
||||
set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
|
||||
set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
|
||||
set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
|
||||
set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
|
||||
set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
|
||||
set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
|
||||
set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
|
||||
set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
|
||||
set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
|
||||
set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
|
||||
set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
|
||||
set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
|
||||
set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
|
||||
set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
|
||||
set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
|
||||
set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
|
||||
set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
|
||||
set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
|
||||
set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
|
||||
set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User LEDs - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
|
||||
set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
|
||||
set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
|
||||
set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
|
||||
set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
|
||||
set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
|
||||
set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
|
||||
set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# VGA Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
|
||||
set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
|
||||
set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
|
||||
set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
|
||||
set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
|
||||
set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
|
||||
set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
|
||||
set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
|
||||
set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
|
||||
set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
|
||||
set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
|
||||
set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
|
||||
set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
|
||||
set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User Push Buttons - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC"
|
||||
set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
|
||||
set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
|
||||
set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
|
||||
set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# USB OTG Reset - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# XADC GIO - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
|
||||
set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
|
||||
set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
|
||||
set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Miscellaneous - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# USB OTG Reset - Bank 35
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User DIP Switches - Bank 35
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
|
||||
set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
|
||||
set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
|
||||
set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
|
||||
set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
|
||||
set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
|
||||
set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
|
||||
set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# XADC AD Channels - Bank 35
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
|
||||
set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
|
||||
set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
|
||||
set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# FMC Expansion Connector - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
|
||||
set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# FMC Expansion Connector - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# FMC Expansion Connector - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
|
||||
set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
|
||||
set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
|
||||
set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
|
||||
set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
|
||||
set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
|
||||
set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
|
||||
set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
|
||||
set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
|
||||
set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
|
||||
set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
|
||||
set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
|
||||
set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
|
||||
set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
|
||||
set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
|
||||
set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
|
||||
set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
|
||||
set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
|
||||
set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
|
||||
set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
|
||||
set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
|
||||
set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
|
||||
set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
|
||||
set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
|
||||
set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
|
||||
set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
|
||||
set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
|
||||
set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
|
||||
set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
|
||||
set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
|
||||
set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
|
||||
set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
|
||||
set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
|
||||
set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
|
||||
set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
|
||||
set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# FMC Expansion Connector - Bank 35
|
||||
# ----------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
|
||||
set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
|
||||
set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
|
||||
set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
|
||||
set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
|
||||
set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
|
||||
set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
|
||||
set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
|
||||
set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
|
||||
set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
|
||||
set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
|
||||
set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
|
||||
set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
|
||||
set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
|
||||
set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
|
||||
set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
|
||||
set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
|
||||
set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
|
||||
set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
|
||||
set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
|
||||
set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
|
||||
set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
|
||||
set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
|
||||
set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
|
||||
set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
|
||||
set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
|
||||
set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
|
||||
set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
|
||||
set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
|
||||
set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
|
||||
set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
|
||||
set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
|
||||
set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
|
||||
set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
|
||||
set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
|
||||
set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# IOSTANDARD Constraints
|
||||
#
|
||||
# Note that these IOSTANDARD constraints are applied to all IOs currently
|
||||
# assigned within an I/O bank. If these IOSTANDARD constraints are
|
||||
# evaluated prior to other PACKAGE_PIN constraints being applied, then
|
||||
# the IOSTANDARD specified will likely not be applied properly to those
|
||||
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
|
||||
# within the XDC file in a location that is evaluated AFTER all
|
||||
# PACKAGE_PIN constraints within the target bank have been evaluated.
|
||||
#
|
||||
# Un-comment one or more of the following IOSTANDARD constraints according to
|
||||
# the bank pin assignments that are required within a design.
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
|
||||
|
||||
# Set the bank voltage for IO Bank 34 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
|
||||
|
||||
# Set the bank voltage for IO Bank 35 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
|
||||
|
||||
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
|
||||
BIN
download/CypressDriverInstaller_1.exe
(Stored with Git LFS)
Normal file
BIN
download/CypressDriverInstaller_1.exe
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
download/corebundle-mst_lab.zip
(Stored with Git LFS)
Normal file
BIN
download/corebundle-mst_lab.zip
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
download/corebundle-mst_lab2.zip
(Stored with Git LFS)
Normal file
BIN
download/corebundle-mst_lab2.zip
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
download/xillinux-2.0.img.gz
(Stored with Git LFS)
Normal file
BIN
download/xillinux-2.0.img.gz
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
download/xillinux-eval-zedboard-2.0c.zip
(Stored with Git LFS)
Normal file
BIN
download/xillinux-eval-zedboard-2.0c.zip
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
feedback.png
Normal file
BIN
feedback.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 8.5 KiB |
1
feedback.xml
Normal file
1
feedback.xml
Normal file
@ -0,0 +1 @@
|
||||
<mxfile host="www.draw.io" modified="2020-04-29T16:58:52.772Z" agent="5.0 (Windows)" version="13.0.3" etag="cTyPEfKk6Dbk87byXYzn"><diagram id="XXEXLVUDAfSVulWw4Scs" name="Page-1">7ZnbcpswEIafxpfNADKYXBLbSTvjdDL1dJpcKqCAWhlRIR/o01eAsACRxHVsXGdyZfbXAaT9VivJAzBebG4YTKJbGiAysIxgMwCTgWVZhuWKn1zJSsW+tEshZDgoJVMJc/wHSdGQ6hIHKG1U5JQSjpOm6NM4Rj5vaJAxum5We6Kk+dYEhkgT5j4kuvoDBzwqVdc2lP4Z4TCq3mwasmQBq8pSSCMY0HVNAtMBGDNKefm02IwRySevmpey3fUzpdsPYyjmOzUYyu/gWTU4FIixSpMyHtGQxpBMlXrF6DIOUN6DISxVZ0ZpIkRTiD8R55l0HFxyKqSIL4gsRRvM72vPD3lXF7a0JhvZc2FklRFzlt3XjbLVyK5s1a6wqoblAPNRPTtHUkrpkvmyliWxgixEspa79Y8AG9EFEm8RVRgikONVs3coCQu39ZQTxIP0Q7dP5KtXkCxlp95krLmp6YR1hDmaJ7D4/LWIuuaEP2FCxpRQVrQFT66PfF/oKWf0F6qVPLr20FaztkKMo83L86bPiGzgSsZlkJuOtNcqZIZSimrRUmlvmcLLc6f6OFADHWq7J6jB+4R6S2sPUG89ekZUX7hqfd6N7MK6QwyL+UFMigFMo2IQ5t7sD3X2axl3P/iLph5jMKtVSCiOeVrr+S4XFEF2GyGnlaJfqQ9GRoua8gsUQ9uh7ITVUIvMiXeOkWlbpwvNamN6TqHZR8Kx9aBzeko4to71dOY9CGn25ev0bXwfgNbtbugFWt1j0XqGiaQPWh2d1lFPtDoarfOxN5t+Ozmnu2x4jsap9cFpF6cjndNhT5yONE4HlkN4vkXDK/EY5o/eRBRcz79fVWXCqhWfnOmhcUKmwSmZVhw/1Epe3cQ3t/BHYdo93drr7sL07ff7/5Xm1r7XtHbb97qHoHl07iu0dZwl2uzY+fZ1f2jqW1/9eCJ4481ZbR7OYhqj1klOSpDgMBamL8afH9CvcnqxD4knCxY4CApHd7HfdP4B8AeghT/Q8bc68LcOgf/HPWM3/W9FvfsmpH2h3F7BymCTjVpe/Lc7EVPPCdcM/V6i2M+qNPDIqhRwg2LEIBdB8m6j7FM7yTi2FmVOR5SBA0SZddJjgHFhOs1AeyXShNG+vtw3+g5w7Vn5rZ6IQE+JqHp3Y2fV9iQhOElzj6URTHLRJ3QZ9HO2bd3BgI7UYXbljj22TsJU/+qWK5L6bxxM/wI=</diagram></mxfile>
|
||||
@ -1,6 +0,0 @@
|
||||
JA4 ext_clk
|
||||
JA1 sync_pulse [NOTE: If pin is left floating, it will register as a pulse]
|
||||
SW7 standby
|
||||
LED7 standy_status
|
||||
BTNC reset
|
||||
BTNU reset_debug
|
||||
@ -15,7 +15,7 @@ use work.typedef_package.all;
|
||||
-- mem_data(62) : Addsub_mode
|
||||
-- mem_data(61) : Add_input_mux
|
||||
-- mem_data(47-40) : delay
|
||||
-- mem_data(35-32) : factor
|
||||
-- mem_data(36-32) : factor
|
||||
-- mem_data(31-0) : timestamp
|
||||
|
||||
|
||||
|
||||
@ -187,10 +187,11 @@ begin
|
||||
PIPELINE_STAGES => 1
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
data_in => delay_out(ADC_DATA_WIDTH-1 downto 0),
|
||||
factor => factor,
|
||||
data_out => scaler_out
|
||||
clk => clk,
|
||||
data_in => delay_out(ADC_DATA_WIDTH-1 downto 0),
|
||||
factor => factor,
|
||||
data_out(DAC_DATA_WIDTH) => open, --Truncate result
|
||||
data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_out
|
||||
);
|
||||
|
||||
process(clk)
|
||||
|
||||
@ -39,7 +39,7 @@ architecture arch of pmod_ad1_ctrl is
|
||||
--*****SIGNAL DECLARATIONS*****
|
||||
signal buf1, buf2, buf1_next, buf2_next : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal stage, stage_next : STAGE_TYPE := IDLE;
|
||||
signal count, count_next : integer range 0 to TRANSFER_CLK_COUNT := 0;
|
||||
signal count, count_next : integer range 0 to TRANSFER_CLK_COUNT-1 := 0;
|
||||
-- Output Signals
|
||||
signal cs_n_next : std_logic := '1';
|
||||
signal done_next : std_logic := '0';
|
||||
@ -61,7 +61,7 @@ begin
|
||||
if (enable = '1') then
|
||||
stage_next <= TRANSFER;
|
||||
cs_n_next <= '0';
|
||||
count_next <= 1;
|
||||
count_next <= 0;
|
||||
end if;
|
||||
-- NOTE: This state remains longer than the width of the data word. This is by design
|
||||
-- to shift out the initial zero bits of the tranfer.
|
||||
@ -70,20 +70,20 @@ begin
|
||||
buf1_next <= buf1(DATA_WIDTH-2 downto 0) & sdata1;
|
||||
buf2_next <= buf2(DATA_WIDTH-2 downto 0) & sdata2;
|
||||
cs_n_next <= '0';
|
||||
if (count = TRANSFER_CLK_COUNT) then
|
||||
if (count = TRANSFER_CLK_COUNT-1) then
|
||||
stage_next <= DELAY;
|
||||
count_next <= 1;
|
||||
count_next <= 0;
|
||||
cs_n_next <= '1';
|
||||
done_next <= '1';
|
||||
else
|
||||
count_next <= count + 1;
|
||||
end if;
|
||||
when DELAY =>
|
||||
if (count = DELAY_CLK_CNT) then
|
||||
if (count = DELAY_CLK_CNT-1) then
|
||||
if(enable = '1') then
|
||||
stage_next <= TRANSFER;
|
||||
cs_n_next <= '0';
|
||||
count_next <= 1;
|
||||
count_next <= 0;
|
||||
else
|
||||
stage_next <= IDLE;
|
||||
end if;
|
||||
|
||||
@ -37,7 +37,7 @@ architecture arch of pmod_da3_ctrl is
|
||||
--*****SIGNAL DECLARATIONS*****
|
||||
signal buf, buf_next : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal stage, stage_next : STAGE_TYPE := IDLE;
|
||||
signal count, count_next : integer range 0 to TRANSFER_CLK_COUNT := 0;
|
||||
signal count, count_next : integer range 0 to TRANSFER_CLK_COUNT-1 := 0;
|
||||
-- Output Signals
|
||||
signal cs_n_next : std_logic := '1';
|
||||
signal sdata_next : std_logic := '0';
|
||||
@ -63,7 +63,7 @@ begin
|
||||
if (start = '1') then
|
||||
stage_next <= TRANSFER;
|
||||
cs_n_next <= '0';
|
||||
count_next <= 1;
|
||||
count_next <= 0;
|
||||
-- Shift first bit into DAC
|
||||
buf_next <= data(DATA_WIDTH-2 downto 0) & '0';
|
||||
sdata_next <= data(DATA_WIDTH-1);
|
||||
@ -73,7 +73,7 @@ begin
|
||||
buf_next <= buf(DATA_WIDTH-2 downto 0) & '0';
|
||||
sdata_next <= buf(DATA_WIDTH-1);
|
||||
cs_n_next <= '0';
|
||||
if (count = TRANSFER_CLK_COUNT) then
|
||||
if (count = TRANSFER_CLK_COUNT-1) then
|
||||
cs_n_next <= '1';
|
||||
stage_next <= IDLE;
|
||||
done_next <= '1';
|
||||
@ -88,7 +88,7 @@ begin
|
||||
|
||||
sync : process(clk)
|
||||
begin
|
||||
if (rising_edge(sclk)) then
|
||||
if (rising_edge(clk)) then
|
||||
if (reset = '1') then
|
||||
-- Internal Signals
|
||||
buf <= (others => '0');
|
||||
|
||||
@ -17,7 +17,7 @@ package typedef_package is
|
||||
|
||||
constant MAX_DELAY : integer := 200;
|
||||
constant DELAY_WIDTH : integer := 8; --at least log2(MAX_DELAY)
|
||||
constant FACTOR_WIDTH : integer := 4;
|
||||
constant FACTOR_WIDTH : integer := 5;
|
||||
|
||||
constant TIMESTAMP_WIDTH : integer := 32;
|
||||
|
||||
|
||||
@ -1,12 +1,13 @@
|
||||
#Feedback Loop Configuration File
|
||||
#
|
||||
#Each line of this file defines a configuration slot and consists of integer numbers delimited by white spaces in the following order:
|
||||
#Each line of this file defines a configuration slot and consists of integer numbers delimited by white
|
||||
#spaces in the following order:
|
||||
#ADDSUB_MODE ADD_INPUT_MUX DELAY FACTOR TIMESTAMP
|
||||
#
|
||||
#ADDSUB_MODE: Select feedback mode (0=negative, 1=positive)
|
||||
#ADD_INPUT_MUX: Select feedback input (0=GND[only ADC Input 1], 1=ADC Input 2[Both ADC inputs are used])
|
||||
#DELAY: Clock cycles counts (50 ns period) to delay the feedback signal [0-255]
|
||||
#FACTOR: Multiplication factor to apply to the feedback signal [0-15] (NOTE: Integer is intepreted as a 1Q3 Fixed Point Number!)
|
||||
#FACTOR: Multiplication factor to apply to the feedback signal [0-16] (NOTE: Integer is intepreted as a 1Q4 Fixed Point Number!)
|
||||
#TIMESTAMP: Defines the clock count number from the sync pulse from which on the configurations settings will be applied. [32-bit unsigned integer]
|
||||
# First Config slot should have a timestamp equal to zero.
|
||||
1 0 0 8 0
|
||||
|
||||
@ -55,7 +55,7 @@ int main(int argc, char *argv[]){
|
||||
|
||||
data = 0x0;
|
||||
data |= ((uint64_t)0x1 << 63) | ((addsub_mode & 0x1) << 62) | ((add_input_mode & 0x1) << 61) | ((delay & 0xFF) << 40) |
|
||||
((factor & 0xF) << 32) | (timestamp & 0xFFFFFFFF);
|
||||
((factor & 0x1F) << 32) | (timestamp & 0xFFFFFFFF);
|
||||
if(write(dest, &data, sizeof(uint64_t)) != sizeof(uint64_t)){
|
||||
perror("Failed to write data");
|
||||
bail();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user