diff --git a/doc/ZedBoard_RevD.2_Errata_151222.pdf b/doc/ZedBoard_RevD.2_Errata_151222.pdf new file mode 100644 index 0000000..540d4ed --- /dev/null +++ b/doc/ZedBoard_RevD.2_Errata_151222.pdf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7fe6163d6eb2e258b0efbf788ff589f8a1f65415d708fac342af0bc096071648 +size 1116052 diff --git a/src/feedback_top.vhd b/src/feedback_top.vhd index c8a544d..0db9a5c 100644 --- a/src/feedback_top.vhd +++ b/src/feedback_top.vhd @@ -29,7 +29,9 @@ entity feedback_top is dac_data_out : out std_logic; dac_cs_n : out std_logic; dac_ldac : out std_logic; - dac_sclk : out std_logic + dac_sclk : out std_logic; + --DEBUG + leds : out std_logic_vector(LED_WIDTH-1 downto 0) ); end entity; @@ -262,4 +264,11 @@ begin dac_sclk <= clk_20; -- Connect standy to mem_full signal, to prevent simutanuoys read/writing on memory mem_full <= not standby; + -- Connect leds + led_prc : process(all) + begin + leds <= (others => '0'); + leds(LED_WIDTH-1) <= standby; + end process; + end architecture; \ No newline at end of file diff --git a/src/top.xdc b/src/top.xdc index 9b19b2b..19a61fb 100644 --- a/src/top.xdc +++ b/src/top.xdc @@ -31,3 +31,4 @@ set_property PACKAGE_PIN W8 [get_ports dac_sclk] set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk] set_property IOSTANDARD LVCMOS33 [get_ports areset] + diff --git a/src/typedef_package.vhd b/src/typedef_package.vhd index 8f7ad44..25df037 100644 --- a/src/typedef_package.vhd +++ b/src/typedef_package.vhd @@ -41,6 +41,8 @@ package typedef_package is constant DEBUG_SEND_INTERVAL : integer := 20000000; + constant LED_WIDTH : integer := 4; + --TODO: 3-stage sync to delay write-mode 1 clk cycle --*****FUNCTION DECLARATIONS***** diff --git a/xillinux-syn/vhdl/src/xillydemo.ucf b/xillinux-syn/vhdl/src/xillydemo.ucf deleted file mode 100644 index 9b17a05..0000000 --- a/xillinux-syn/vhdl/src/xillydemo.ucf +++ /dev/null @@ -1,134 +0,0 @@ -NET "clk_100" TNM_NET = "TN_gclk"; -TIMESPEC "TS_gclk" = PERIOD "TN_gclk" 10 ns HIGH 50 %; - -# The VGA outputs are turned into an analog voltage by virtue of a resistor -# network, so the flip flops driving these must sit in the IOBs to minimize -# timing skew. The RTL code should handle this, but the constraint below -# is there to fail if something goes wrong about this. - -INST "xillybus_ins/vga_iob_ff[*]" TNM = "tgrp_vga_pads_ffs"; -TIMESPEC "TS_force_iob_ffs" = FROM "tgrp_vga_pads_ffs" 5.5 ns ; - -NET "clk_100" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK" -NET "GPIO_LED[0]" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0" -NET "GPIO_LED[1]" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1" -NET "GPIO_LED[2]" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2" -NET "GPIO_LED[3]" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3" -NET "vga4_blue[0]" LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1" -NET "vga4_blue[1]" LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2" -NET "vga4_blue[2]" LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3" -NET "vga4_blue[3]" LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4" -NET "vga4_green[0]" LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1" -NET "vga4_green[1]" LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2" -NET "vga4_green[2]" LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3" -NET "vga4_green[3]" LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4" -NET "vga4_red[0]" LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1" -NET "vga4_red[1]" LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2" -NET "vga4_red[2]" LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3" -NET "vga4_red[3]" LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4" -NET "vga_vsync" LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS" -NET "vga_hsync" LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS" - -# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin -# placement doesn't match the one given by Digilent. - -# GPIO pin to reset the USB OTG PHY - -NET PS_GPIO[0] LOC = G17 | IOSTANDARD = LVCMOS33; # USB-Reset - -# On-board OLED - -NET PS_GPIO[1] LOC = U11 | IOSTANDARD = LVCMOS33; # OLED-VBAT -NET PS_GPIO[2] LOC = U12 | IOSTANDARD = LVCMOS33; # OLED-VDD -NET PS_GPIO[3] LOC = U9 | IOSTANDARD = LVCMOS33; # OLED-RES -NET PS_GPIO[4] LOC = U10 | IOSTANDARD = LVCMOS33; # OLED-DC -NET PS_GPIO[5] LOC = AB12 | IOSTANDARD = LVCMOS33; # OLED-SCLK -NET PS_GPIO[6] LOC = AA12 | IOSTANDARD = LVCMOS33; # OLED-SDIN - -# On-board LEDs. Note that only for LEDs are allocated, as opposed to -# Digilent's eight, and all placements that follow are shifted by four. -# There was no other choice, as the tools don't allow unplaced PS GPIO pins. - -NET PS_GPIO[7] LOC = V22 | IOSTANDARD = LVCMOS33; # LD4 -NET PS_GPIO[8] LOC = W22 | IOSTANDARD = LVCMOS33; # LD5 -NET PS_GPIO[9] LOC = U19 | IOSTANDARD = LVCMOS33; # LD6 -NET PS_GPIO[10] LOC = U14 | IOSTANDARD = LVCMOS33; # LD7 - -# On-board Slide Switches - -NET PS_GPIO[11] LOC = F22 | IOSTANDARD = LVCMOS33; # SW0 -NET PS_GPIO[12] LOC = G22 | IOSTANDARD = LVCMOS33; # SW1 -NET PS_GPIO[13] LOC = H22 | IOSTANDARD = LVCMOS33; # SW2 -NET PS_GPIO[14] LOC = F21 | IOSTANDARD = LVCMOS33; # SW3 -NET PS_GPIO[15] LOC = H19 | IOSTANDARD = LVCMOS33; # SW4 -NET PS_GPIO[16] LOC = H18 | IOSTANDARD = LVCMOS33; # SW5 -NET PS_GPIO[17] LOC = H17 | IOSTANDARD = LVCMOS33; # SW6 -NET PS_GPIO[18] LOC = M15 | IOSTANDARD = LVCMOS33; # SW7 - -# On-board Left, Right, Up, Down, and Select Pushbuttons - -NET PS_GPIO[19] LOC = N15 | IOSTANDARD = LVCMOS33; # BTNL -NET PS_GPIO[20] LOC = R18 | IOSTANDARD = LVCMOS33; # BTNR -NET PS_GPIO[21] LOC = T18 | IOSTANDARD = LVCMOS33; # BTNU -NET PS_GPIO[22] LOC = R16 | IOSTANDARD = LVCMOS33; # BTND -NET PS_GPIO[23] LOC = P16 | IOSTANDARD = LVCMOS33; # BTNS - -# Pmod JA - -NET PS_GPIO[24] LOC = Y11 | IOSTANDARD = LVCMOS33; # JA1 -NET PS_GPIO[25] LOC = AA11 | IOSTANDARD = LVCMOS33; # JA2 -NET PS_GPIO[26] LOC = Y10 | IOSTANDARD = LVCMOS33; # JA3 -NET PS_GPIO[27] LOC = AA9 | IOSTANDARD = LVCMOS33; # JA4 -NET PS_GPIO[28] LOC = AB11 | IOSTANDARD = LVCMOS33; # JA7 -NET PS_GPIO[29] LOC = AB10 | IOSTANDARD = LVCMOS33; # JA8 -NET PS_GPIO[30] LOC = AB9 | IOSTANDARD = LVCMOS33; # JA9 -NET PS_GPIO[31] LOC = AA8 | IOSTANDARD = LVCMOS33; # JA10 - -# Pmod JB - -NET PS_GPIO[32] LOC = W12 | IOSTANDARD = LVCMOS33; # JB1 -NET PS_GPIO[33] LOC = W11 | IOSTANDARD = LVCMOS33; # JB2 -NET PS_GPIO[34] LOC = V10 | IOSTANDARD = LVCMOS33; # JB3 -NET PS_GPIO[35] LOC = W8 | IOSTANDARD = LVCMOS33; # JB4 -NET PS_GPIO[36] LOC = V12 | IOSTANDARD = LVCMOS33; # JB7 -NET PS_GPIO[37] LOC = W10 | IOSTANDARD = LVCMOS33; # JB8 -NET PS_GPIO[38] LOC = V9 | IOSTANDARD = LVCMOS33; # JB9 -NET PS_GPIO[39] LOC = V8 | IOSTANDARD = LVCMOS33; # JB10 - -# Pmod JC - -NET PS_GPIO[40] LOC = AB7 | IOSTANDARD = LVCMOS33; # JC1_P (JC1) -NET PS_GPIO[41] LOC = AB6 | IOSTANDARD = LVCMOS33; # JC1_N (JC2) -NET PS_GPIO[42] LOC = Y4 | IOSTANDARD = LVCMOS33; # JC2_P (JC3) -NET PS_GPIO[43] LOC = AA4 | IOSTANDARD = LVCMOS33; # JC2_N (JC4) -NET PS_GPIO[44] LOC = R6 | IOSTANDARD = LVCMOS33; # JC3_P (JC7) -NET PS_GPIO[45] LOC = T6 | IOSTANDARD = LVCMOS33; # JC3_N (JC8) -NET PS_GPIO[46] LOC = T4 | IOSTANDARD = LVCMOS33; # JC4_P (JC9) -NET PS_GPIO[47] LOC = U4 | IOSTANDARD = LVCMOS33; # JC4_N (JC10) - -# Pmod JD - -NET PS_GPIO[48] LOC = V7 | IOSTANDARD = LVCMOS33; # JD1_P (JD1) -NET PS_GPIO[49] LOC = W7 | IOSTANDARD = LVCMOS33; # JD1_N (JD2) -NET PS_GPIO[50] LOC = V5 | IOSTANDARD = LVCMOS33; # JD2_P (JD3) -NET PS_GPIO[51] LOC = V4 | IOSTANDARD = LVCMOS33; # JD2_N (JD4) -NET PS_GPIO[52] LOC = W6 | IOSTANDARD = LVCMOS33; # JD3_P (JD7) -NET PS_GPIO[53] LOC = W5 | IOSTANDARD = LVCMOS33; # JD3_N (JD8) -NET PS_GPIO[54] LOC = U6 | IOSTANDARD = LVCMOS33; # JD4_P (JD9) -NET PS_GPIO[55] LOC = U5 | IOSTANDARD = LVCMOS33; # JD4_N (JD10) - -# Pin for detecting USB OTG over-current condition - -NET otg_oc LOC = L16 | IOSTANDARD="LVCMOS33"; - -# Pins connected to sound chip -NET smbus_addr[0] LOC = AB1 | IOSTANDARD=LVCMOS33; # "AC-ADR0" -NET smbus_addr[1] LOC = Y5 | IOSTANDARD=LVCMOS33; # "AC-ADR1" -NET smb_sclk LOC = AB4 | IOSTANDARD=LVCMOS33; # "AC-SCK" -NET smb_sdata LOC = AB5 | IOSTANDARD=LVCMOS33; # "AC-SDA" - -NET audio_dac LOC = Y8 | IOSTANDARD=LVCMOS33; # "AC-GPIO0" -NET audio_adc LOC = AA7 | IOSTANDARD=LVCMOS33; # "AC-GPIO1" -NET audio_bclk LOC = AA6 | IOSTANDARD=LVCMOS33; # "AC-GPIO2" -NET audio_lrclk LOC = Y6 | IOSTANDARD=LVCMOS33; # "AC-GPIO3" -NET audio_mclk LOC = AB2 | IOSTANDARD=LVCMOS33; # "AC-MCLK" diff --git a/xillinux-syn/vhdl/src/xillydemo.vhd b/xillinux-syn/vhdl/src/xillydemo.vhd index f8488c9..268aaa4 100644 --- a/xillinux-syn/vhdl/src/xillydemo.vhd +++ b/xillinux-syn/vhdl/src/xillydemo.vhd @@ -36,7 +36,8 @@ entity xillydemo is dac_data_out : out std_logic; dac_cs_n : out std_logic; dac_ldac : out std_logic; - dac_sclk : out std_logic + dac_sclk : out std_logic; + leds : out std_logic_vector(LED_WIDTH-1 downto 0) ); end xillydemo; @@ -177,7 +178,8 @@ architecture sample_arch of xillydemo is dac_data_out : out std_logic; dac_cs_n : out std_logic; dac_ldac : out std_logic; - dac_sclk : out std_logic + dac_sclk : out std_logic; + leds : out std_logic_vector(LED_WIDTH-1 downto 0) ); end component; @@ -343,7 +345,7 @@ begin mem_wen => user_w_config_wren, mem_full => user_w_config_full, --FPGA - clk_in => clk_ext, + clk_in => clk_100, areset => areset, areset_debug => areset_debug, async_pulse => async_pulse, @@ -355,7 +357,8 @@ begin dac_data_out => dac_data_out, dac_cs_n => dac_cs_n, dac_ldac => dac_ldac, - dac_sclk => dac_sclk + dac_sclk => dac_sclk, + leds => leds ); audio_ins : i2s_audio diff --git a/xillinux-syn/vivado-essentials/xillydemo.xdc b/xillinux-syn/vivado-essentials/xillydemo.xdc index aca6261..2c36a8b 100644 --- a/xillinux-syn/vivado-essentials/xillydemo.xdc +++ b/xillinux-syn/vivado-essentials/xillydemo.xdc @@ -1,5 +1,5 @@ -create_clock -name gclk -period 10 [get_ports "clk_100"] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets "clk_100"] +create_clock -period 10.000 -name gclk [get_ports clk_100] +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_100] # Vivado constraints unrelated clocks. So set false paths. set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks vga_clk_ins/*] @@ -9,42 +9,91 @@ set_false_path -from [get_clocks vga_clk_ins/*] -to [get_clocks clk_fpga_1] # network, so the flip flops driving these must sit in the IOBs to minimize # timing skew. The RTL code should handle this, but the constraint below # is there to fail if something goes wrong about this. -set_output_delay 5.5 [get_ports {vga*}] +set_output_delay 5.500 [get_ports vga*] -set_property -dict "PACKAGE_PIN Y9 IOSTANDARD LVCMOS33" [get_ports "clk_100"] -set_property -dict "PACKAGE_PIN T22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[0]"] -set_property -dict "PACKAGE_PIN T21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[1]"] -set_property -dict "PACKAGE_PIN U22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[2]"] -set_property -dict "PACKAGE_PIN U21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[3]"] -set_property -dict "PACKAGE_PIN Y21 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[0]"] -set_property -dict "PACKAGE_PIN Y20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[1]"] -set_property -dict "PACKAGE_PIN AB20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[2]"] -set_property -dict "PACKAGE_PIN AB19 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[3]"] -set_property -dict "PACKAGE_PIN AB22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[0]"] -set_property -dict "PACKAGE_PIN AA22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[1]"] -set_property -dict "PACKAGE_PIN AB21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[2]"] -set_property -dict "PACKAGE_PIN AA21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[3]"] -set_property -dict "PACKAGE_PIN V20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[0]"] -set_property -dict "PACKAGE_PIN U20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[1]"] -set_property -dict "PACKAGE_PIN V19 IOSTANDARD LVCMOS33" [get_ports "vga4_red[2]"] -set_property -dict "PACKAGE_PIN V18 IOSTANDARD LVCMOS33" [get_ports "vga4_red[3]"] -set_property -dict "PACKAGE_PIN Y19 IOSTANDARD LVCMOS33" [get_ports "vga_vsync"] -set_property -dict "PACKAGE_PIN AA19 IOSTANDARD LVCMOS33" [get_ports "vga_hsync"] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports clk_100] +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[0]}] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[1]}] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[2]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[3]}] +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[0]}] +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[1]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[2]}] +set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[3]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[0]}] +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[1]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[2]}] +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[0]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[1]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {vga4_red[2]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {vga4_red[3]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports vga_vsync] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports vga_hsync] # IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin # placement doesn't match the one given by Digilent. # Pin for detecting USB OTG over-current condition -set_property -dict "PACKAGE_PIN L16 IOSTANDARD LVCMOS33" [get_ports "otg_oc"] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_oc] # Pins connected to sound chip -set_property -dict "PACKAGE_PIN AB1 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[0]"] -set_property -dict "PACKAGE_PIN Y5 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[1]"] -set_property -dict "PACKAGE_PIN AB4 IOSTANDARD LVCMOS33" [get_ports "smb_sclk"] -set_property -dict "PACKAGE_PIN AB5 IOSTANDARD LVCMOS33" [get_ports "smb_sdata"] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[0]}] +set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[1]}] +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33} [get_ports smb_sclk] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports smb_sdata] -set_property -dict "PACKAGE_PIN Y8 IOSTANDARD LVCMOS33" [get_ports "audio_dac"] -set_property -dict "PACKAGE_PIN AA7 IOSTANDARD LVCMOS33" [get_ports "audio_adc"] -set_property -dict "PACKAGE_PIN AA6 IOSTANDARD LVCMOS33" [get_ports "audio_bclk"] -set_property -dict "PACKAGE_PIN Y6 IOSTANDARD LVCMOS33" [get_ports "audio_lrclk"] -set_property -dict "PACKAGE_PIN AB2 IOSTANDARD LVCMOS33" [get_ports "audio_mclk"] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports audio_dac] +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports audio_adc] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports audio_bclk] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports audio_lrclk] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports audio_mclk] + + +create_clock -period 100.000 -name sys_clk -waveform {0.000 50.000} [get_ports clk_ext] +create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000} +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1] +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1] +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in2] +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in2] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -5.000 [get_ports adc_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000 [get_ports dac_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out] + +set_property IOSTANDARD LVCMOS33 [get_ports adc_cs_n] +set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in1] +set_property PACKAGE_PIN AB7 [get_ports adc_cs_n] +set_property PACKAGE_PIN AB6 [get_ports adc_data_in1] +set_property PACKAGE_PIN Y4 [get_ports adc_data_in2] +set_property PACKAGE_PIN AA4 [get_ports adc_sclk] +set_property PACKAGE_PIN V7 [get_ports dac_cs_n] +set_property IOSTANDARD LVCMOS33 [get_ports dac_cs_n] +set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in2] +set_property IOSTANDARD LVCMOS33 [get_ports adc_sclk] +set_property PACKAGE_PIN W7 [get_ports dac_data_out] +set_property IOSTANDARD LVCMOS33 [get_ports dac_data_out] +set_property PACKAGE_PIN V5 [get_ports dac_ldac] +set_property IOSTANDARD LVCMOS33 [get_ports dac_ldac] +set_property PACKAGE_PIN V4 [get_ports dac_sclk] +set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk] +set_property PACKAGE_PIN AA9 [get_ports clk_ext] +set_property IOSTANDARD LVCMOS33 [get_ports clk_ext] +set_property PACKAGE_PIN Y11 [get_ports async_pulse] +set_property IOSTANDARD LVCMOS33 [get_ports async_pulse] +set_property PACKAGE_PIN U14 [get_ports {leds[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}] +set_property PACKAGE_PIN U19 [get_ports {leds[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}] +set_property PACKAGE_PIN W22 [get_ports {leds[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}] +set_property PACKAGE_PIN V22 [get_ports {leds[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}] +set_property PACKAGE_PIN M15 [get_ports astandby] +set_property IOSTANDARD LVCMOS33 [get_ports astandby] +set_property PACKAGE_PIN P16 [get_ports areset] +set_property IOSTANDARD LVCMOS33 [get_ports areset] +set_property PACKAGE_PIN T18 [get_ports areset_debug] +set_property IOSTANDARD LVCMOS33 [get_ports areset_debug] diff --git a/xillinux-syn/vivado/xillydemo.xpr b/xillinux-syn/vivado/xillydemo.xpr index 41a36ab..9139ae2 100644 --- a/xillinux-syn/vivado/xillydemo.xpr +++ b/xillinux-syn/vivado/xillydemo.xpr @@ -247,6 +247,7 @@ + @@ -319,7 +320,7 @@ - + @@ -332,6 +333,7 @@ +