From abe34fd0fc31c37e8d4dd779404c23101e0bd446 Mon Sep 17 00:00:00 2001
From: Greek64 <greek64.mail@gmail.com>
Date: Mon, 22 Mar 2021 18:17:08 +0100
Subject: [PATCH] Day 1 Labor Fixes

---
 src/feedback_loop.vhd | 45 +++++++++++++++++++++++++++++++++++++------
 src/feedback_top.vhd  | 17 +++++++++++++++-
 2 files changed, 55 insertions(+), 7 deletions(-)

diff --git a/src/feedback_loop.vhd b/src/feedback_loop.vhd
index 4583098..c259523 100644
--- a/src/feedback_loop.vhd
+++ b/src/feedback_loop.vhd
@@ -139,7 +139,7 @@ architecture arch of feedback_loop is
     --*****SIGNAL DECLARATION*****
     signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
     signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
-    signal scaler_out, addsub_out, inputA : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal scaler_out, addsub_out, inputA, inputB, scaler_offset : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
     signal scaler_done, addsub_done : std_logic := '0';
     
 begin
@@ -180,7 +180,7 @@ begin
         );
     
     --*****STAGE III*****
-    scaler_inst : scaler
+    scaler_A_inst : scaler
         generic map(
             DATA_WIDTH      => ADC_DATA_WIDTH,
             FACTOR_WIDTH    => FACTOR_WIDTH,
@@ -194,6 +194,20 @@ begin
             data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_out
         );
     
+    scaler_offset_inst : scaler
+        generic map(
+            DATA_WIDTH      => ADC_DATA_WIDTH,
+            FACTOR_WIDTH    => FACTOR_WIDTH,
+            PIPELINE_STAGES => 1
+        )
+        port map(
+            clk                                 => clk,
+            data_in                             => (ADC_DATA_WIDTH-1 => '0', others => '1'),
+            factor                              => "0" & factor(FACTOR_WIDTH-2 downto 0),
+            data_out(DAC_DATA_WIDTH)            => open,    --Truncate result
+            data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_offset
+        );
+    
     process(clk)
     begin
         if (rising_edge(clk)) then
@@ -216,6 +230,21 @@ begin
         end if;
     end process;
     
+    addsub_instB : addsub
+        generic map(
+            PIPELINE_STAGES => 0,
+            DATA_WIDTH      => DAC_DATA_WIDTH
+        )
+        port map(
+            clk     => clk,
+            reset   => reset,
+            mode    => '0',
+            cap     => '0',
+            A       => scaler_out,
+            B       => scaler_offset,
+            RES     => inputB
+        );
+    
     --*****STAGE IV*****
     
     mux: process(all)
@@ -223,11 +252,15 @@ begin
         if (add_input_mux = '1') then
             inputA  <= latch_out & "0000";
         else
-            inputA  <= (others => '0');
+            if (addsub_mode = '1') then
+                inputA  <= (others => '0');
+            else
+                inputA  <= (others => '1');
+            end if;
         end if;
     end process;
     
-    addsub_inst : addsub
+    addsub_instA : addsub
         generic map(
             PIPELINE_STAGES => 1,
             DATA_WIDTH      => DAC_DATA_WIDTH
@@ -238,7 +271,7 @@ begin
             mode    => addsub_mode,
             cap     => add_input_mux,
             A       => inputA,
-            B       => scaler_out,
+            B       => inputB,
             RES     => addsub_out
         );
     
@@ -303,4 +336,4 @@ begin
     
     
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/feedback_top.vhd b/src/feedback_top.vhd
index 4909dcc..74466e5 100644
--- a/src/feedback_top.vhd
+++ b/src/feedback_top.vhd
@@ -148,6 +148,7 @@ architecture arch of feedback_top is
     signal config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := (others => '0');
     signal config_ren : std_logic := '0';
     signal config_data : std_logic_vector(CONFIG_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal sync_led : std_logic := '0';
     
 begin
     
@@ -270,6 +271,20 @@ begin
     begin
         leds                <= (others => '0');
         leds(LED_WIDTH-1)   <= standby;
+        leds(LED_WIDTH-2)   <= sync_led;
     end process;
     
-end architecture;
\ No newline at end of file
+    sync_debug : process(all)
+    begin
+        if rising_edge(clk_20) then
+            if (reset = '1') then
+                sync_led    <= '0';
+            else
+                if (sync_pulse = '1') then
+                    sync_led    <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+    
+end architecture;