From b6357a993e67eee6846e7deab059f3e7147e1e9d Mon Sep 17 00:00:00 2001 From: Greek Date: Tue, 23 Mar 2021 02:16:23 +0100 Subject: [PATCH] Fix Scaling Offset --- src/feedback_loop.vhd | 44 +++++++++++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/src/feedback_loop.vhd b/src/feedback_loop.vhd index c259523..04af8d7 100644 --- a/src/feedback_loop.vhd +++ b/src/feedback_loop.vhd @@ -139,8 +139,10 @@ architecture arch of feedback_loop is --*****SIGNAL DECLARATION***** signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal scaler_out, addsub_out, inputA, inputB, scaler_offset : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal scaler_out, scaler_offset : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); signal scaler_done, addsub_done : std_logic := '0'; + signal offset_factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); begin @@ -179,6 +181,21 @@ begin data_out => delay_out ); + addsub_offset_inst : addsub + generic map( + PIPELINE_STAGES => 1, + DATA_WIDTH => FACTOR_WIDTH + ) + port map( + clk => clk, + reset => reset, + mode => '0', + cap => '0', + A => (FACTOR_WIDTH-1 => '1', others => '0'), + B => factor, + RES => offset_factor + ); + --*****STAGE III***** scaler_A_inst : scaler generic map( @@ -187,11 +204,10 @@ begin PIPELINE_STAGES => 1 ) port map( - clk => clk, - data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), - factor => factor, - data_out(DAC_DATA_WIDTH) => open, --Truncate result - data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_out + clk => clk, + data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), + factor => factor, + data_out => scaler_out ); scaler_offset_inst : scaler @@ -201,11 +217,10 @@ begin PIPELINE_STAGES => 1 ) port map( - clk => clk, - data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), - factor => "0" & factor(FACTOR_WIDTH-2 downto 0), - data_out(DAC_DATA_WIDTH) => open, --Truncate result - data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_offset + clk => clk, + data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), + factor => offset_factor, + data_out => scaler_offset ); process(clk) @@ -233,16 +248,17 @@ begin addsub_instB : addsub generic map( PIPELINE_STAGES => 0, - DATA_WIDTH => DAC_DATA_WIDTH + DATA_WIDTH => DAC_DATA_WIDTH+1 ) port map( clk => clk, reset => reset, - mode => '0', + mode => not factor(FACTOR_WIDTH-1), cap => '0', A => scaler_out, B => scaler_offset, - RES => inputB + RES(DAC_DATA_WIDTH) => open, --Truncate Carry Bit + RES(DAC_DATA_WIDTH-1 downto 0) => inputB ); --*****STAGE IV*****