diff --git a/Readme.md b/Readme.md
index 1776543..00a5d80 100644
--- a/Readme.md
+++ b/Readme.md
@@ -29,6 +29,8 @@
 
 # Board Mapping
 
+Zedboard Pin                    |   Description
+--------------------------------|---------------
 JC1 PMOD Connector (Upper Row)  |   PMOD-AD1 Board  
 JD1 PMOD Connector (Upper Row)  |   PMOD-DA3 Board  
 JA1 PMOD JA1 Pin                |   Optional External Clock [NOTE: Clk has to be connected in VHDl and PLL has to be reconfigured accordingly]  
@@ -36,7 +38,7 @@ JA1 PMOD JA4 Pin                |   External SYNC Pulse [NOTE: if pin is left un
 SW7                             |   Standby / Write Mode (Allows xillinux to write configuration)  
 LED7                            |   Standby Status  
 BTNC                            |   Global reset  
-BTNU                            |   Debug value reset  
+BTNU                            |   Debug value reset
 
 
 # Project Description
@@ -100,18 +102,3 @@ Currently the FPGA logic sends every second the max values of the both ADC chann
 
 The `read_debug.c` C program can be used to read the debug values. Since the program enters an endless loop, a signal handler has beeen implemented and the program can be safely terminated with `CTRL-C` and co.  
 e.g. `./read_debug /dev/xillybus_debug`
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