diff --git a/src/clockgen.vhd b/src/clockgen.vhd new file mode 100644 index 0000000..4914a31 --- /dev/null +++ b/src/clockgen.vhd @@ -0,0 +1,87 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +entity clockgen is + port ( + clk_in : in std_logic; + clk_out : out std_logic + ); +end entity; + +architecture inst of clockgen is + + signal clkfbout, clkfbout_buf : std_logic := '0'; + +begin + + --*****FEEDBACK***** + clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout, + O => clkfbout_buf + ); + + --*****PLL***** + plle2_adv_inst: unisim.vcomponents.PLLE2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT => 41, + CLKFBOUT_PHASE => 0.000000, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE => 41, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 5, + IS_CLKINSEL_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + STARTUP_WAIT => "FALSE" + ) + port map ( + CLKFBIN => clkfbout_buf, + CLKFBOUT => clkfbout, + CLKIN1 => clk_in, + CLKIN2 => '0', + CLKINSEL => '1', + CLKOUT0 => clk_out, + CLKOUT1 => open, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => open, + DRDY => open, + DWE => '0', + LOCKED => open, + PWRDWN => '0', + RST => '0' + ); + +end architecture; \ No newline at end of file diff --git a/src/top.vhd b/src/top.vhd new file mode 100644 index 0000000..9ce3dec --- /dev/null +++ b/src/top.vhd @@ -0,0 +1,66 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity top is + port ( + sys_clk : in std_logic; + areset : in std_logic; + adc_data_in1 : in std_logic; + adc_data_in2 : in std_logic; + adc_cs_n : out std_logic; + adc_sclk : out std_logic; + dac_data_out : out std_logic; + dac_cs_n : out std_logic; + dac_ldac : out std_logic; + dac_sclk : out std_logic + ); +end entity; + +architecture arch of top is + + --*****COMPONENT DECLARATION***** + component clockgen is + port ( + clk_in : in std_logic; + clk_out : out std_logic + ); + end component; + + component open_loop is + port ( + clk : in std_logic; + areset : in std_logic; + adc_data_in : in std_logic; + adc_cs_n : out std_logic; + dac_data_out : out std_logic; + dac_cs_n : out std_logic; + dac_ldac : out std_logic + ); + end component; + + --*****DIGNAL DECLARATION***** + signal clk_20 : std_logic := '0'; + +begin + + clockgen_inst : clockgen + port map( + clk_in => sys_clk, + clk_out => clk_20 + ); + + open_loop_inst : open_loop + port map( + clk => clk_20, + areset => areset, + adc_data_in => adc_data_in1, + adc_cs_n => adc_cs_n, + dac_data_out => dac_data_out, + dac_cs_n => dac_cs_n, + dac_ldac => dac_ldac + ); + + adc_sclk <= clk_20; + dac_sclk <= clk_20; +end architecture; \ No newline at end of file diff --git a/src/top.xdc b/src/top.xdc new file mode 100644 index 0000000..328c44e --- /dev/null +++ b/src/top.xdc @@ -0,0 +1,33 @@ +create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports sys_clk] +create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000} +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1] +set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -5.000 [get_ports adc_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000 [get_ports dac_cs_n] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out] +set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out] + +set_property PACKAGE_PIN Y9 [get_ports sys_clk] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clk] + +set_property PACKAGE_PIN P16 [get_ports areset] +set_property PACKAGE_PIN Y11 [get_ports adc_cs_n] +set_property IOSTANDARD LVCMOS33 [get_ports adc_cs_n] +set_property PACKAGE_PIN AA11 [get_ports adc_data_in1] +set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in1] +set_property PACKAGE_PIN Y19 [get_ports adc_data_in2] +set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in2] +set_property PACKAGE_PIN AA9 [get_ports adc_sclk] +set_property IOSTANDARD LVCMOS33 [get_ports adc_sclk] +set_property PACKAGE_PIN W12 [get_ports dac_cs_n] +set_property IOSTANDARD LVCMOS33 [get_ports dac_cs_n] +set_property PACKAGE_PIN W11 [get_ports dac_data_out] +set_property IOSTANDARD LVCMOS33 [get_ports dac_data_out] +set_property PACKAGE_PIN V10 [get_ports dac_ldac] +set_property IOSTANDARD LVCMOS33 [get_ports dac_ldac] +set_property PACKAGE_PIN W8 [get_ports dac_sclk] +set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk] + +set_property IOSTANDARD LVCMOS33 [get_ports areset] diff --git a/syn/labor-mst.xpr b/syn/labor-mst.xpr index b9a026e..46e35cf 100644 --- a/syn/labor-mst.xpr +++ b/syn/labor-mst.xpr @@ -18,6 +18,7 @@