diff --git a/modelsim/feedback.do b/modelsim/feedback.do index 8e1710a..74bba58 100644 --- a/modelsim/feedback.do +++ b/modelsim/feedback.do @@ -8,39 +8,35 @@ add wave -noupdate /feedback_loop_tb/adc_data_in1 add wave -noupdate /feedback_loop_tb/adc_data_in2 add wave -noupdate /feedback_loop_tb/adc_cs_n add wave -noupdate -divider CONFIG -add wave -noupdate /feedback_loop_tb/factor add wave -noupdate /feedback_loop_tb/addsub_mode add wave -noupdate /feedback_loop_tb/add_input_mux add wave -noupdate -radix unsigned /feedback_loop_tb/delay +add wave -noupdate -radix binary /feedback_loop_tb/uut/factor1 +add wave -noupdate -radix binary /feedback_loop_tb/uut/factor2 add wave -noupdate -divider INPUT add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/adc_data1 add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/adc_data2 add wave -noupdate /feedback_loop_tb/uut/adc_done -add wave -noupdate -radix hexadecimal /feedback_loop_tb/input2 -add wave -noupdate -divider OUTPUT -add wave -noupdate /feedback_loop_tb/uut/addsub_done -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/addsub_out add wave -noupdate -divider TESTBENCH add wave -noupdate /feedback_loop_tb/adc_stage add wave -noupdate /feedback_loop_tb/cnt1 add wave -noupdate /feedback_loop_tb/cnt2 add wave -noupdate -divider SIGNAL -add wave -noupdate -format Analog-Step -height 200 -max 4096.0 -radix unsigned /feedback_loop_tb/input1 -add wave -noupdate -format Analog-Step -height 200 -max 4094.9999999999995 -radix unsigned /feedback_loop_tb/input2 -add wave -noupdate -format Analog-Step -height 200 -max 65536.0 -radix unsigned /feedback_loop_tb/output +add wave -noupdate -expand -group ANALOG -format Analog-Step -height 200 -max 4096.0 -radix unsigned /feedback_loop_tb/input1 +add wave -noupdate -expand -group ANALOG -format Analog-Step -height 200 -max 4094.9999999999995 -radix unsigned /feedback_loop_tb/input2 +add wave -noupdate -expand -group ANALOG -format Analog-Step -height 200 -max 65536.0 -radix unsigned /feedback_loop_tb/output add wave -noupdate -divider MISC -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_1_out -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_2_out +add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/data1_B +add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/data2_B add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_offset_1 add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_offset_2 -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputA_wide -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputB_wide -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputA -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputB -add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/addsub_out -add wave -noupdate /feedback_loop_tb/uut/scaler_done +add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/data1_C +add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/data2_C +add wave -noupdate /feedback_loop_tb/uut/done_II +add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/data_out +add wave -noupdate /feedback_loop_tb/uut/done_IV TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {399500000000 fs} 0} +WaveRestoreCursors {{Cursor 4} {101850000000 fs} 0} quietly wave cursor active 1 configure wave -namecolwidth 150 configure wave -valuecolwidth 100 @@ -56,4 +52,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {371218089984 fs} {506777995264 fs} +WaveRestoreZoom {0 fs} {535391147585 fs} diff --git a/src/addsub.vhd b/src/addsub.vhd deleted file mode 100644 index 0c7595a..0000000 --- a/src/addsub.vhd +++ /dev/null @@ -1,76 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -Library UNIMACRO; -use UNIMACRO.vcomponents.all; - --- Add/Sub --- This entity adds or subtracts inputs 'A' and 'B', depending on 'mode' (1 = add, 0 = sub). --- If 'cap' is high, on Overfolw/Underflow conditions the result is capped at max/min value. - -entity addsub is - generic ( - PIPELINE_STAGES : integer := 1; - DATA_WIDTH : integer := 16 - ); - port ( - clk : in std_logic; - reset : in std_logic; - mode : in std_logic; - cap : in std_logic; - A : in std_logic_vector(DATA_WIDTH-1 downto 0); - B : in std_logic_vector(DATA_WIDTH-1 downto 0); - RES : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); -end entity; - -architecture arch of addsub is - - --*****SIGNAl DECLARATION - signal result : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); - signal carry : std_logic := '0'; - -begin - - ADDSUB_MACRO_inst : ADDSUB_MACRO - generic map ( - DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6" - LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-2 - WIDTH => DATA_WIDTH -- Input / Output bus width, 1-48 - ) - port map ( - CARRYOUT => open, -- 1-bit carry-out output signal - RESULT => result, -- Add/sub result output, width defined by WIDTH generic - A => A, -- Input A bus, width defined by WIDTH generic - ADD_SUB => mode, -- 1-bit add/sub input, high selects add, low selects subtract - B => B, -- Input B bus, width defined by WIDTH generic - CARRYIN => '0', -- 1-bit carry-in input - CE => '1', -- 1-bit clock enable input - CLK => clk, -- 1-bit clock input - RST => reset -- 1-bit active high synchronous reset - ); - - clamp : process(all) - begin - --DEFAULT VALUE - RES <= result; - - --Overflow/Underflow - if(carry = '1' and cap = '1') then - --ADD - if(mode = '1') then - --CAP AT MAX VALUE - RES <= (others => '1'); - --SUB - else - --CAP AT ZERO - RES <= (others => '0'); - end if; - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/src/feedback_controller.vhd b/src/feedback_controller.vhd index ff51055..f81ba88 100644 --- a/src/feedback_controller.vhd +++ b/src/feedback_controller.vhd @@ -14,8 +14,9 @@ use work.typedef_package.all; -- mem_data(63) : Slot Enable -- mem_data(62) : Addsub_mode -- mem_data(61) : Add_input_mux --- mem_data(47-40) : delay --- mem_data(36-32) : factor +-- mem_data(57-42) : delay +-- mem_data(41-37) : factor1 +-- mem_data(36-32) : factor2 -- mem_data(31-0) : timestamp @@ -33,7 +34,8 @@ entity feedback_controller is addsub_mode : out std_logic; add_input_mux : out std_logic; delay : out std_logic_vector(DELAY_WIDTH-1 downto 0); - factor : out std_logic_vector(FACTOR_WIDTH-1 downto 0) + factor1 : out std_logic_vector(FACTOR_WIDTH-1 downto 0); + factor2 : out std_logic_vector(FACTOR_WIDTH-1 downto 0) ); end entity; @@ -47,7 +49,7 @@ architecture arch of feedback_controller is signal sync_pulse_arrived : std_logic; signal addsub_mode_next, addsub_mode_sig, add_input_mux_next, add_input_mux_sig : std_logic := '0'; signal delay_next, delay_sig : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0'); - signal factor_next, factor_sig : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal factor1_next, factor1_sig, factor2_next, factor2_sig : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); begin @@ -58,7 +60,8 @@ begin addsub_mode <= addsub_mode_sig; add_input_mux <= add_input_mux_sig; delay <= delay_sig; - factor <= factor_sig; + factor1 <= factor1_sig; + factor2 <= factor2_sig; ctrl : process(all) begin @@ -67,7 +70,8 @@ begin addsub_mode_next <= addsub_mode_sig; add_input_mux_next <= add_input_mux_sig; delay_next <= delay_sig; - factor_next <= factor_sig; + factor1_next <= factor1_sig; + factor2_next <= factor2_sig; if(mem_data(CONFIG_DATA_WIDTH-1) = '1') then -- If timestamp is reached (or exceeded), apply configuration and fetch next configuration @@ -75,8 +79,9 @@ begin if (unsigned(timer) >= unsigned(mem_data(TIMESTAMP_WIDTH-1 downto 0))) then addsub_mode_next <= mem_data(CONFIG_DATA_WIDTH-2); add_input_mux_next <= mem_data(CONFIG_DATA_WIDTH-3); - delay_next <= mem_data(CONFIG_DATA_WIDTH-17 downto CONFIG_DATA_WIDTH-16-DELAY_WIDTH); - factor_next <= mem_data(TIMESTAMP_WIDTH+FACTOR_WIDTH-1 downto TIMESTAMP_WIDTH); + factor2_next <= mem_data(TIMESTAMP_WIDTH+FACTOR_WIDTH-1 downto TIMESTAMP_WIDTH); + factor1_next <= mem_data(TIMESTAMP_WIDTH+FACTOR_WIDTH+FACTOR_WIDTH-1 downto TIMESTAMP_WIDTH+FACTOR_WIDTH); + delay_next <= mem_data(TIMESTAMP_WIDTH+FACTOR_WIDTH+FACTOR_WIDTH+DELAY_WIDTH-1 downto TIMESTAMP_WIDTH+FACTOR_WIDTH+FACTOR_WIDTH); slot_nr_next <= std_logic_vector(unsigned(slot_nr) + inc); end if; @@ -91,13 +96,15 @@ begin addsub_mode_sig <= '0'; add_input_mux_sig <= '0'; delay_sig <= (others => '0'); - factor_sig <= (others => '0'); + factor1_sig <= (others => '0'); + factor2_sig <= (others => '0'); else slot_nr <= slot_nr_next; addsub_mode_sig <= addsub_mode_next; add_input_mux_sig <= add_input_mux_next; delay_sig <= delay_next; - factor_sig <= factor_next; + factor1_sig <= factor1_next; + factor2_sig <= factor2_next; end if; end if; end process; diff --git a/src/feedback_loop.vhd b/src/feedback_loop.vhd index fbf1d53..2eecf4f 100644 --- a/src/feedback_loop.vhd +++ b/src/feedback_loop.vhd @@ -34,9 +34,10 @@ entity feedback_loop is dac_sclk : out std_logic; -- PMOD-DA3 -- DYNAMIC CONFIGURATION addsub_mode : in std_logic; -- (1=ADD, 0=SUB) - add_input_mux : in std_logic; -- (1=ADC Input 2, 0=GND) - delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- unsigned delay clock count - factor : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point + add_input_mux : in std_logic; -- (1=Double Input 2, 0=Single Input) + delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- Unsigned delay clock count + factor1 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point + factor2 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point -- DEBUG reset_debug : in std_logic; adc_data1_max : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0); @@ -48,10 +49,6 @@ end entity; architecture arch of feedback_loop is - --*****SIGNAL DECLARATION***** - signal adc_data1, adc_data2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal adc_done : std_logic := '0'; - --*****COMPONENT DECLARATION***** component pmod_ad1_ctrl is generic( @@ -105,22 +102,6 @@ architecture arch of feedback_loop is ); end component; - component addsub is - generic ( - PIPELINE_STAGES : integer := 1; - DATA_WIDTH : integer := 16 - ); - port ( - clk : in std_logic; - reset : in std_logic; - mode : in std_logic; - cap : in std_logic; - A : in std_logic_vector(DATA_WIDTH-1 downto 0); - B : in std_logic_vector(DATA_WIDTH-1 downto 0); - RES : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); - end component; - component delay_line is generic ( DATA_WIDTH : integer := 12; @@ -142,13 +123,16 @@ architecture arch of feedback_loop is constant FACTOR_ONE : unsigned(FACTOR_WIDTH-1 downto 0) := (FACTOR_WIDTH-1 => '1', others => '0'); --*****SIGNAL DECLARATION***** - signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); - signal tmp2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal inputA_wide, inputB_wide : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); - signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal scaler_1_out, scaler_2_out, scaler_offset_1, scaler_offset_2 : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); - signal scaler_done, addsub_done : std_logic := '0'; - signal offset_factor, tmp : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal adc_data1, adc_data2, adc_data1_latch : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal adc_done : std_logic := '0'; + signal data1_A : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal data2_A : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); + signal data2_C, data1_C : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); + signal data_out, data2_D, data1_D : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); + signal data1_B, data2_B, scaler_offset_1, scaler_offset_2 : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); + signal done_II, done_IV : std_logic := '0'; + signal offset_factor1, offset_factor2, factor1_latch, factor2_latch : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal add_input_mux_latch, addsub_mode_latch : std_logic := '0'; begin @@ -173,7 +157,29 @@ begin ); --*****STAGE II***** - delay_line_inst : delay_line + + -- NOTE: The Input1 Signal has to be latched if the delay line is used, so that + -- there is a valid Signal to do operations with after the delay line. + latch_1_prc : process (clk) + begin + if rising_edge(clk) then + if (adc_done = '1') then + adc_data1_latch <= adc_data1; + end if; + end if; + end process; + + data1_prc : process (all) + begin + -- If delay_line disabled or Signle Input Mode + if (delay = (delay'range => '0') or add_input_mux = '0') then + data1_A <= adc_data1; + else + data1_A <= adc_data1_latch; + end if; + end process; + + delay_line_2_inst : delay_line generic map( DATA_WIDTH => ADC_DATA_WIDTH+1, DELAY_WIDTH => DELAY_WIDTH, @@ -183,39 +189,46 @@ begin clk => clk, reset => reset, delay => delay, - data_in => (adc_done & adc_data1), - data_out => delay_out + data_in => (adc_done & adc_data2), + data_out => data2_A ); - latch_prc : process (all) + offset_factor_1_prc : process (all) + variable tmp_res : unsigned(FACTOR_WIDTH-1 downto 0) := (others => '0'); begin - if (delay = (delay'range => '0')) then - tmp2 <= adc_data2; - elsif rising_edge(clk) then - if (adc_done = '1') then - tmp2 <= adc_data2; - end if; + if (factor1(FACTOR_WIDTH-1) = '1') then + offset_factor1 <= "0" & std_logic_vector(factor1(FACTOR_WIDTH-2 downto 0)); + else + tmp_res := FACTOR_ONE - unsigned(factor1); + offset_factor1 <= "0" & std_logic_vector(tmp_res(FACTOR_WIDTH-2 downto 0)); end if; end process; - addsub_offset_inst : addsub - generic map( - PIPELINE_STAGES => 0, - DATA_WIDTH => FACTOR_WIDTH - ) - port map( - clk => clk, - reset => reset, - mode => '0', - cap => '0', - A => (FACTOR_WIDTH-1 => '1', others => '0'), - B => factor, - RES => tmp - ); + offset_factor_2_prc : process (all) + variable tmp_res : unsigned(FACTOR_WIDTH-1 downto 0) := (others => '0'); + begin + if (factor2(FACTOR_WIDTH-1) = '1') then + offset_factor2 <= "0" & std_logic_vector(factor2(FACTOR_WIDTH-2 downto 0)); + else + tmp_res := FACTOR_ONE - unsigned(factor2); + offset_factor2 <= "0" & std_logic_vector(tmp_res(FACTOR_WIDTH-2 downto 0)); + end if; + end process; - offset_factor <= tmp when (factor(FACTOR_WIDTH-1) = '0') else ("0" & factor(FACTOR_WIDTH-2 downto 0)); + -- NOTE: We delay the config signals to synchronize them with the data flow and + -- prevent glitches in the case that the config is changed between the stages. + config_latch : process (clk) + begin + if rising_edge(clk) then + factor1_latch <= factor1; + factor2_latch <= factor2; + add_input_mux_latch <= add_input_mux; + addsub_mode_latch <= addsub_mode; + end if; + end process; --*****STAGE III***** + scaler_1_inst : scaler generic map( DATA_WIDTH => ADC_DATA_WIDTH, @@ -224,22 +237,9 @@ begin ) port map( clk => clk, - data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), - factor => factor, - data_out => scaler_1_out - ); - - scaler_2_inst : scaler - generic map( - DATA_WIDTH => ADC_DATA_WIDTH, - FACTOR_WIDTH => FACTOR_WIDTH, - PIPELINE_STAGES => 1 - ) - port map( - clk => clk, - data_in => tmp2, - factor => "10101", --1.32 - data_out => scaler_2_out + data_in => data1_A, + factor => factor1, + data_out => data1_B ); scaler_offset_1_inst : scaler @@ -251,10 +251,45 @@ begin port map( clk => clk, data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), - factor => offset_factor, + factor => offset_factor1, data_out => scaler_offset_1 ); + addsub_1_prc : process (all) + begin + if (factor1_latch(FACTOR_WIDTH-1) = '1') then + data1_C <= std_logic_vector(unsigned(data1_B) - unsigned(scaler_offset_1)); + else + data1_C <= std_logic_vector(unsigned(data1_B) + unsigned(scaler_offset_1)); + end if; + end process; + + cap_1_prc : process(all) + begin + if (data1_C(DAC_DATA_WIDTH) = '1') then + if (factor1_latch(FACTOR_WIDTH-1) = '1' and data1_B(DAC_DATA_WIDTH) = '0') then + data1_D <= (others => '0'); + else + data1_D <= (others => '1'); + end if; + else + data1_D <= data1_C(DAC_DATA_WIDTH-1 downto 0); + end if; + end process; + + scaler_2_inst : scaler + generic map( + DATA_WIDTH => ADC_DATA_WIDTH, + FACTOR_WIDTH => FACTOR_WIDTH, + PIPELINE_STAGES => 1 + ) + port map( + clk => clk, + data_in => data2_A(ADC_DATA_WIDTH-1 downto 0), + factor => factor2, + data_out => data2_B + ); + scaler_offset_2_inst : scaler generic map( DATA_WIDTH => ADC_DATA_WIDTH, @@ -264,206 +299,115 @@ begin port map( clk => clk, data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), - factor => "00101", --0.32 + factor => offset_factor2, data_out => scaler_offset_2 ); - process(clk) + addsub_2_prc : process (all) + begin + if (factor2_latch(FACTOR_WIDTH-1) = '1') then + data2_C <= std_logic_vector(unsigned(data2_B) - unsigned(scaler_offset_2)); + else + data2_C <= std_logic_vector(unsigned(data2_B) + unsigned(scaler_offset_2)); + end if; + end process; + + cap_2_prc : process(all) + begin + if (data2_C(DAC_DATA_WIDTH) = '1') then + if (factor2_latch(FACTOR_WIDTH-1) = '1' and data2_B(DAC_DATA_WIDTH) = '0') then + data2_D <= (others => '0'); + else + data2_D <= (others => '1'); + end if; + else + data2_D <= data2_C(DAC_DATA_WIDTH-1 downto 0); + end if; + end process; + + done_II_prc : process(clk) begin if (rising_edge(clk)) then if (reset = '1') then - scaler_done <= '0'; + done_II <= '0'; else - scaler_done <= delay_out(ADC_DATA_WIDTH); + -- Signle Input Mode + if (add_input_mux_latch = '0') then + -- Synchronize on ADC Output + done_II <= adc_done; + else + -- Synchronize on Delay Line Output + done_II <= data2_A(ADC_DATA_WIDTH); + end if; end if; end if; end process; - addsub_1_inst : addsub - generic map( - PIPELINE_STAGES => 0, - DATA_WIDTH => DAC_DATA_WIDTH+1 - ) - port map( - clk => clk, - reset => reset, - mode => not factor(FACTOR_WIDTH-1), - cap => '0', - A => scaler_1_out, - B => scaler_offset_1, - RES => inputB_wide - ); - - addsub_2_inst : addsub - generic map( - PIPELINE_STAGES => 0, - DATA_WIDTH => DAC_DATA_WIDTH+1 - ) - port map( - clk => clk, - reset => reset, - mode => '0', - cap => '0', - A => scaler_2_out, - B => scaler_offset_2, - RES => inputA_wide - ); - - cap_B_prc : process(all) - begin - if (inputB_wide(DAC_DATA_WIDTH) = '1') then - if (factor(FACTOR_WIDTH-1) = '1' and scaler_1_out(DAC_DATA_WIDTH) = '0') then - inputB <= (others => '0'); - else - inputB <= (others => '1'); - end if; - else - inputB <= inputB_wide(DAC_DATA_WIDTH-1 downto 0); - end if; - end process; - - cap_A_prc : process(all) - begin - if (inputA_wide(DAC_DATA_WIDTH) = '1') then - --if (factor(FACTOR_WIDTH-1) = '1' and scaler_2_out(DAC_DATA_WIDTH) = '0') then - if (scaler_2_out(DAC_DATA_WIDTH) = '0') then - inputA <= (others => '0'); - else - inputA <= (others => '1'); - end if; - else - inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0); - end if; - end process; - --*****STAGE IV***** - --mux: process(all) - --begin - -- if (add_input_mux = '1') then - -- if (inputA_wide(DAC_DATA_WIDTH) = '1') then - -- --TODO: CAP Needed? - -- inputA <= (others => '0'); - -- else - -- inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0); - -- end if; - -- else - -- if (addsub_mode = '1') then - -- inputA <= (others => '0'); - -- else - -- inputA <= (others => '1'); - -- end if; - -- end if; - --end process; - - --add_sub_prc : process (all) - -- variable tmp_res : unsigned(inputB'length-1 downto 0) := (others => '0'); - --begin - -- if rising_edge(clk) then - -- if (reset = '1') then - -- addsub_out <= (others => '0'); - -- else - -- -- Both Inputs - -- if (add_input_mux = '1') then - -- -- ADD - -- if (addsub_mode = '1') then - -- tmp_res := unsigned(inputB) + unsigned(inputA); - -- -- SUB - -- else - -- tmp_res := unsigned(inputB) - unsigned(inputA); - -- end if; - -- addsub_out <= std_logic_vector(tmp_res + CONST_HALF); - -- -- Single Input - -- else - -- -- ADD - -- if (addsub_mode = '1') then - -- addsub_out <= inputB; - -- -- SUB - -- else - -- addsub_out <= not inputB;--std_logic_vector(CONST_MAX - unsigned(inputB)); - -- end if; - -- end if; - -- end if; - -- end if; - --end process; - - add_sub_prc : process (all) + add_sub_prc : process (clk) variable tmp_res : unsigned(DAC_DATA_WIDTH+1 downto 0) := (others => '0'); begin if rising_edge(clk) then if (reset = '1') then - addsub_out <= (others => '0'); + data_out <= (others => '0'); else - -- Both Inputs - if (add_input_mux = '1') then + -- Double Input Mode + if (add_input_mux_latch = '1') then -- ADD - if (addsub_mode = '1') then - tmp_res := unsigned("00" & inputB) + unsigned("00" & inputA); + if (addsub_mode_latch = '1') then + tmp_res := unsigned("00" & data1_D) + unsigned("00" & data2_D); tmp_res := tmp_res + ("00" & CONST_HALF); -- Overflow if (tmp_res(DAC_DATA_WIDTH+1) = '1') then - addsub_out <= (others => '1'); + data_out <= (others => '1'); -- Underflow elsif (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "00") then - addsub_out <= (others => '0'); + data_out <= (others => '0'); else - addsub_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0)); + data_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0)); end if; -- SUB else - tmp_res := unsigned("00" & inputB) - unsigned("00" & inputA); + tmp_res := unsigned("00" & data1_D) - unsigned("00" & data2_D); tmp_res := tmp_res + ("00" & CONST_HALF); -- Underflow if (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "11") then - addsub_out <= (others => '0'); + data_out <= (others => '0'); -- Overflow elsif (tmp_res(DAC_DATA_WIDTH) = '1') then - addsub_out <= (others => '1'); + data_out <= (others => '1'); else - addsub_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0)); + data_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0)); end if; end if; - -- Single Input + -- Single Input Mode else -- ADD - if (addsub_mode = '1') then - addsub_out <= inputB; + if (addsub_mode_latch = '1') then + data_out <= data1_D; -- SUB else - addsub_out <= not inputB;--std_logic_vector(CONST_MAX - unsigned(inputB)); + data_out <= not data1_D; end if; end if; end if; end if; end process; --- addsub_instA : addsub --- generic map( --- PIPELINE_STAGES => 1, --- DATA_WIDTH => DAC_DATA_WIDTH --- ) --- port map( --- clk => clk, --- reset => reset, --- mode => addsub_mode, --- cap => add_input_mux, --- A => inputA, --- B => inputB, --- RES => addsub_out --- ); - - process(clk) + done_IV_prc : process(clk) begin if (rising_edge(clk)) then if (reset = '1') then - addsub_done <= '0'; + done_IV <= '0'; else - addsub_done <= scaler_done; + done_IV <= done_II; end if; end if; end process; --*****STAGE V***** + dac_inst : pmod_da3_ctrl generic map( TRANSFER_CLK_COUNT => DAC_TRANSFER_CLK_COUNT, @@ -472,8 +416,8 @@ begin port map( clk => clk, reset => reset, - start => addsub_done, - data => addsub_out, + start => done_IV, + data => data_out, cs_n => dac_cs_n, sdata => dac_data_out, ldac => dac_ldac, @@ -497,15 +441,15 @@ begin elsif (to_integer(unsigned(adc_data2)) >= to_integer(unsigned(adc_data2_max))) then adc_data2_max <= adc_data2; end if; - -- DAC MAX VALUES - elsif (addsub_done = '1') then - if (to_integer(unsigned(addsub_out)) >= to_integer(unsigned(dac_max))) then - dac_max <= addsub_out; - end if; -- SCALER MAX VALUES - elsif (scaler_done = '1') then - if (to_integer(unsigned(scaler_1_out)) >= to_integer(unsigned(scaler_max))) then - scaler_max <= scaler_1_out(DAC_DATA_WIDTH-1 downto 0); + elsif (done_II = '1') then + if (to_integer(unsigned(data1_B)) >= to_integer(unsigned(scaler_max))) then + scaler_max <= data1_B(DAC_DATA_WIDTH-1 downto 0); + end if; + -- DAC MAX VALUES + elsif (done_IV = '1') then + if (to_integer(unsigned(data_out)) >= to_integer(unsigned(dac_max))) then + dac_max <= data_out; end if; end if; end if; diff --git a/src/feedback_top.vhd b/src/feedback_top.vhd index 74466e5..0255b3c 100644 --- a/src/feedback_top.vhd +++ b/src/feedback_top.vhd @@ -76,9 +76,10 @@ architecture arch of feedback_top is dac_sclk : out std_logic; -- PMOD-DA3 -- DYNAMIC CONFIGURATION addsub_mode : in std_logic; -- (1=ADD, 0=SUB) - add_input_mux : in std_logic; -- (1=ADC Input 2, 0=GND) - delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- unsigned delay clock count - factor : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point + add_input_mux : in std_logic; -- (1=Double Input 2, 0=Single Input) + delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- Unsigned delay clock count + factor1 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point + factor2 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point -- DEBUG reset_debug : in std_logic; adc_data1_max : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0); @@ -102,7 +103,8 @@ architecture arch of feedback_top is addsub_mode : out std_logic; add_input_mux : out std_logic; delay : out std_logic_vector(DELAY_WIDTH-1 downto 0); - factor : out std_logic_vector(FACTOR_WIDTH-1 downto 0) + factor1 : out std_logic_vector(FACTOR_WIDTH-1 downto 0); + factor2 : out std_logic_vector(FACTOR_WIDTH-1 downto 0) ); end component; @@ -142,7 +144,7 @@ architecture arch of feedback_top is signal clk_20, reset, sync_pulse, standby, reset_debug : std_logic := '0'; signal addsub_mode, add_input_mux : std_logic := '0'; signal delay : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0'); - signal factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal factor1, factor2 : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); signal adc_data1_max, adc_data2_max : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); signal scaler_max, dac_max : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); signal config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -219,7 +221,8 @@ begin addsub_mode => addsub_mode, add_input_mux => add_input_mux, delay => delay, - factor => factor, + factor1 => factor1, + factor2 => factor2, reset_debug => reset_debug, adc_data1_max => adc_data1_max, adc_data2_max => adc_data2_max, @@ -238,7 +241,8 @@ begin addsub_mode => addsub_mode, add_input_mux => add_input_mux, delay => delay, - factor => factor + factor1 => factor1, + factor2 => factor2 ); xillybus_link_inst : xillybus_link diff --git a/src/sim/100kHz_half.vhd b/src/sim/100kHz_half.vhd deleted file mode 100644 index d13fbd2..0000000 --- a/src/sim/100kHz_half.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 10) of std_logic_vector(11 downto 0); -constant sine : SINE_ARRAY_TYPE := (x"800", x"A2A", x"BA3", x"BF6", x"B06", x"920", x"6E0", x"4FA", x"40A", x"45D", x"5D6"); -end package; diff --git a/src/sim/100kHz_max.vhd b/src/sim/100kHz_max.vhd deleted file mode 100644 index 9a7485a..0000000 --- a/src/sim/100kHz_max.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 10) of std_logic_vector(11 downto 0); -constant sine : SINE_ARRAY_TYPE := (x"800", x"C53", x"F46", x"FEA", x"E0B", x"A41", x"5BF", x"1F5", x"016", x"0BA", x"3AD"); -end package; diff --git a/src/sim/10kHz_half.vhd b/src/sim/10kHz_half.vhd deleted file mode 100644 index 4f096e0..0000000 --- a/src/sim/10kHz_half.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 110) of std_logic_vector(11 downto 0); - constant sine : SINE_ARRAY_TYPE := (x"800", x"83A", x"874", x"8AD", x"8E6", x"91E", x"955", x"98B", x"9C0", x"9F3", x"A25", x"A55", x"A83", x"AAF", x"AD9", x"B01", x"B26", x"B48", x"B68", x"B85", x"B9F", x"BB6", x"BCA", x"BDB", x"BE9", x"BF4", x"BFB", x"BFF", x"C00", x"BFD", x"BF8", x"BEF", x"BE3", x"BD3", x"BC1", x"BAB", x"B92", x"B77", x"B58", x"B37", x"B14", x"AED", x"AC5", x"A9A", x"A6C", x"A3D", x"A0C", x"9DA", x"9A6", x"970", x"93A", x"902", x"8CA", x"890", x"857", x"81D", x"7E3", x"7A9", x"770", x"736", x"6FE", x"6C6", x"690", x"65A", x"626", x"5F4", x"5C3", x"594", x"566", x"53B", x"513", x"4EC", x"4C9", x"4A8", x"489", x"46E", x"455", x"43F", x"42D", x"41D", x"411", x"408", x"403", x"400", x"401", x"405", x"40C", x"417", x"425", x"436", x"44A", x"461", x"47B", x"498", x"4B8", x"4DA", x"4FF", x"527", x"551", x"57D", x"5AB", x"5DB", x"60D", x"640", x"675", x"6AB", x"6E2", x"71A", x"753", x"78C", x"7C6"); -end package; diff --git a/src/sim/10kHz_max.vhd b/src/sim/10kHz_max.vhd deleted file mode 100644 index a00c427..0000000 --- a/src/sim/10kHz_max.vhd +++ /dev/null @@ -1,11 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 110) of std_logic_vector(11 downto 0); - -- OFFSET: 2048, AMPLITUDE: 2047, FREQUENCY: 10kHz - constant sine2 : SINE_ARRAY_TYPE := (x"800", x"874", x"8E7", x"95A", x"9CC", x"A3C", x"AAA", x"B16", x"B80", x"BE6", x"C4A", x"CAA", x"D06", x"D5E", x"DB2", x"E01", x"E4B", x"E90", x"ECF", x"F09", x"F3D", x"F6B", x"F94", x"FB5", x"FD1", x"FE6", x"FF5", x"FFD", x"FFF", x"FFA", x"FEE", x"FDC", x"FC4", x"FA5", x"F80", x"F55", x"F24", x"EED", x"EB0", x"E6E", x"E26", x"DDA", x"D88", x"D33", x"CD8", x"C7A", x"C18", x"BB3", x"B4B", x"AE0", x"A73", x"A04", x"993", x"921", x"8AE", x"83A", x"7C6", x"752", x"6DF", x"66D", x"5FC", x"58D", x"520", x"4B5", x"44D", x"3E8", x"386", x"328", x"2CD", x"278", x"226", x"1DA", x"192", x"150", x"113", x"0DC", x"0AB", x"080", x"05B", x"03C", x"024", x"012", x"006", x"001", x"003", x"00B", x"01A", x"02F", x"04B", x"06C", x"095", x"0C3", x"0F7", x"131", x"170", x"1B5", x"1FF", x"24E", x"2A2", x"2FA", x"356", x"3B6", x"41A", x"480", x"4EA", x"556", x"5C4", x"634", x"6A6", x"719", x"78C"); - -- OFFSET: 2048, AMPLITUDE: 1024, FREQUENCY: 10kHz - constant sine1 : SINE_ARRAY_TYPE := (x"800", x"83A", x"874", x"8AD", x"8E6", x"91E", x"955", x"98B", x"9C0", x"9F3", x"A25", x"A55", x"A83", x"AAF", x"AD9", x"B01", x"B26", x"B48", x"B68", x"B85", x"B9F", x"BB6", x"BCA", x"BDB", x"BE9", x"BF4", x"BFB", x"BFF", x"C00", x"BFD", x"BF8", x"BEF", x"BE3", x"BD3", x"BC1", x"BAB", x"B92", x"B77", x"B58", x"B37", x"B14", x"AED", x"AC5", x"A9A", x"A6C", x"A3D", x"A0C", x"9DA", x"9A6", x"970", x"93A", x"902", x"8CA", x"890", x"857", x"81D", x"7E3", x"7A9", x"770", x"736", x"6FE", x"6C6", x"690", x"65A", x"626", x"5F4", x"5C3", x"594", x"566", x"53B", x"513", x"4EC", x"4C9", x"4A8", x"489", x"46E", x"455", x"43F", x"42D", x"41D", x"411", x"408", x"403", x"400", x"401", x"405", x"40C", x"417", x"425", x"436", x"44A", x"461", x"47B", x"498", x"4B8", x"4DA", x"4FF", x"527", x"551", x"57D", x"5AB", x"5DB", x"60D", x"640", x"675", x"6AB", x"6E2", x"71A", x"753", x"78C", x"7C6"); -end package; diff --git a/src/sim/1kHz_half.vhd b/src/sim/1kHz_half.vhd deleted file mode 100644 index b075349..0000000 --- a/src/sim/1kHz_half.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 1110) of std_logic_vector(11 downto 0); -constant sine : SINE_ARRAY_TYPE := (x"800", x"806", x"80C", x"811", x"817", x"81D", x"823", x"829", x"82E", x"834", x"83A", x"840", x"845", x"84B", x"851", x"857", x"85D", x"862", x"868", x"86E", x"874", x"879", x"87F", x"885", x"88B", x"890", x"896", x"89C", x"8A1", x"8A7", x"8AD", x"8B3", x"8B8", x"8BE", x"8C4", x"8C9", x"8CF", x"8D5", x"8DA", x"8E0", x"8E6", x"8EB", x"8F1", x"8F7", x"8FC", x"902", x"907", x"90D", x"913", x"918", x"91E", x"923", x"929", x"92E", x"934", x"939", x"93F", x"944", x"94A", x"94F", x"955", x"95A", x"960", x"965", x"96B", x"970", x"975", x"97B", x"980", x"986", x"98B", x"990", x"996", x"99B", x"9A0", x"9A5", x"9AB", x"9B0", x"9B5", x"9BA", x"9C0", x"9C5", x"9CA", x"9CF", x"9D4", x"9DA", x"9DF", x"9E4", x"9E9", x"9EE", x"9F3", x"9F8", x"9FD", x"A02", x"A07", x"A0C", x"A11", x"A16", x"A1B", x"A20", x"A25", x"A2A", x"A2E", x"A33", x"A38", x"A3D", x"A42", x"A47", x"A4B", x"A50", x"A55", x"A59", x"A5E", x"A63", x"A67", x"A6C", x"A71", x"A75", x"A7A", x"A7E", x"A83", x"A87", x"A8C", x"A90", x"A95", x"A99", x"A9D", x"AA2", x"AA6", x"AAB", x"AAF", x"AB3", x"AB7", x"ABC", x"AC0", x"AC4", x"AC8", x"ACC", x"AD0", x"AD5", x"AD9", x"ADD", x"AE1", x"AE5", x"AE9", x"AED", x"AF1", x"AF5", x"AF8", x"AFC", x"B00", x"B04", x"B08", x"B0C", x"B0F", x"B13", x"B17", x"B1A", x"B1E", x"B22", x"B25", x"B29", x"B2C", x"B30", x"B33", x"B37", x"B3A", x"B3E", x"B41", x"B44", x"B48", x"B4B", x"B4E", x"B52", x"B55", x"B58", x"B5B", x"B5E", x"B61", x"B64", x"B67", x"B6B", x"B6D", x"B70", x"B73", x"B76", x"B79", x"B7C", x"B7F", x"B82", x"B84", x"B87", x"B8A", x"B8D", x"B8F", x"B92", x"B94", x"B97", x"B9A", x"B9C", x"B9F", x"BA1", x"BA3", x"BA6", x"BA8", x"BAB", x"BAD", x"BAF", x"BB1", x"BB4", x"BB6", x"BB8", x"BBA", x"BBC", x"BBE", x"BC0", x"BC2", x"BC4", x"BC6", x"BC8", x"BCA", x"BCC", x"BCE", x"BCF", x"BD1", x"BD3", x"BD4", x"BD6", x"BD8", x"BD9", x"BDB", x"BDC", x"BDE", x"BDF", x"BE1", x"BE2", x"BE4", x"BE5", x"BE6", x"BE8", x"BE9", x"BEA", x"BEB", x"BEC", x"BED", x"BEE", x"BF0", x"BF1", x"BF2", x"BF2", x"BF3", x"BF4", x"BF5", x"BF6", x"BF7", x"BF8", x"BF8", x"BF9", x"BFA", x"BFA", x"BFB", x"BFB", x"BFC", x"BFC", x"BFD", x"BFD", x"BFE", x"BFE", x"BFE", x"BFF", x"BFF", x"BFF", x"BFF", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"C00", x"BFF", x"BFF", x"BFF", x"BFF", x"BFE", x"BFE", x"BFE", x"BFD", x"BFD", x"BFC", x"BFC", x"BFB", x"BFB", x"BFA", x"BF9", x"BF9", x"BF8", x"BF7", x"BF6", x"BF6", x"BF5", x"BF4", x"BF3", x"BF2", x"BF1", x"BF0", x"BEF", x"BEE", x"BED", x"BEC", x"BEB", x"BE9", x"BE8", x"BE7", x"BE6", x"BE4", x"BE3", x"BE2", x"BE0", x"BDF", x"BDD", x"BDC", x"BDA", x"BD9", x"BD7", x"BD5", x"BD4", x"BD2", x"BD0", x"BCE", x"BCD", x"BCB", x"BC9", x"BC7", x"BC5", x"BC3", x"BC1", x"BBF", x"BBD", x"BBB", x"BB9", x"BB7", x"BB5", x"BB2", x"BB0", x"BAE", x"BAC", x"BA9", x"BA7", x"BA5", x"BA2", x"BA0", x"B9D", x"B9B", x"B98", x"B96", x"B93", x"B91", x"B8E", x"B8B", x"B89", x"B86", x"B83", x"B80", x"B7D", x"B7B", x"B78", x"B75", x"B72", x"B6F", x"B6C", x"B69", x"B66", x"B63", x"B60", x"B5D", x"B5A", x"B56", x"B53", x"B50", x"B4D", x"B49", x"B46", x"B43", x"B3F", x"B3C", x"B39", x"B35", x"B32", x"B2E", x"B2B", x"B27", x"B23", x"B20", x"B1C", x"B19", x"B15", x"B11", x"B0D", x"B0A", x"B06", x"B02", x"AFE", x"AFA", x"AF7", x"AF3", x"AEF", x"AEB", x"AE7", x"AE3", x"ADF", x"ADB", x"AD7", x"AD3", x"ACE", x"ACA", x"AC6", x"AC2", x"ABE", x"ABA", x"AB5", x"AB1", x"AAD", x"AA8", x"AA4", x"AA0", x"A9B", x"A97", x"A92", x"A8E", x"A8A", x"A85", x"A81", x"A7C", x"A77", x"A73", x"A6E", x"A6A", x"A65", x"A60", x"A5C", x"A57", x"A52", x"A4E", x"A49", x"A44", x"A3F", x"A3B", x"A36", x"A31", x"A2C", x"A27", x"A22", x"A1D", x"A18", x"A14", x"A0F", x"A0A", x"A05", x"A00", x"9FB", x"9F6", x"9F0", x"9EB", x"9E6", x"9E1", x"9DC", x"9D7", x"9D2", x"9CD", x"9C7", x"9C2", x"9BD", x"9B8", x"9B3", x"9AD", x"9A8", x"9A3", x"99D", x"998", x"993", x"98E", x"988", x"983", x"97D", x"978", x"973", x"96D", x"968", x"962", x"95D", x"958", x"952", x"94D", x"947", x"942", x"93C", x"937", x"931", x"92C", x"926", x"920", x"91B", x"915", x"910", x"90A", x"905", x"8FF", x"8F9", x"8F4", x"8EE", x"8E8", x"8E3", x"8DD", x"8D8", x"8D2", x"8CC", x"8C7", x"8C1", x"8BB", x"8B5", x"8B0", x"8AA", x"8A4", x"89F", x"899", x"893", x"88D", x"888", x"882", x"87C", x"876", x"871", x"86B", x"865", x"85F", x"85A", x"854", x"84E", x"848", x"843", x"83D", x"837", x"831", x"82B", x"826", x"820", x"81A", x"814", x"80E", x"809", x"803", x"7FD", x"7F7", x"7F2", x"7EC", x"7E6", x"7E0", x"7DA", x"7D5", x"7CF", x"7C9", x"7C3", x"7BD", x"7B8", x"7B2", x"7AC", x"7A6", x"7A1", x"79B", x"795", x"78F", x"78A", x"784", x"77E", x"778", x"773", x"76D", x"767", x"761", x"75C", x"756", x"750", x"74B", x"745", x"73F", x"739", x"734", x"72E", x"728", x"723", x"71D", x"718", x"712", x"70C", x"707", x"701", x"6FB", x"6F6", x"6F0", x"6EB", x"6E5", x"6E0", x"6DA", x"6D4", x"6CF", x"6C9", x"6C4", x"6BE", x"6B9", x"6B3", x"6AE", x"6A8", x"6A3", x"69E", x"698", x"693", x"68D", x"688", x"683", x"67D", x"678", x"672", x"66D", x"668", x"663", x"65D", x"658", x"653", x"64D", x"648", x"643", x"63E", x"639", x"633", x"62E", x"629", x"624", x"61F", x"61A", x"615", x"610", x"60A", x"605", x"600", x"5FB", x"5F6", x"5F1", x"5EC", x"5E8", x"5E3", x"5DE", x"5D9", x"5D4", x"5CF", x"5CA", x"5C5", x"5C1", x"5BC", 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x"466", x"469", x"46C", x"46E", x"471", x"473", x"476", x"479", x"47C", x"47E", x"481", x"484", x"487", x"48A", x"48D", x"490", x"493", x"495", x"499", x"49C", x"49F", x"4A2", x"4A5", x"4A8", x"4AB", x"4AE", x"4B2", x"4B5", x"4B8", x"4BC", x"4BF", x"4C2", x"4C6", x"4C9", x"4CD", x"4D0", x"4D4", x"4D7", x"4DB", x"4DE", x"4E2", x"4E6", x"4E9", x"4ED", x"4F1", x"4F4", x"4F8", x"4FC", x"500", x"504", x"508", x"50B", x"50F", x"513", x"517", x"51B", x"51F", x"523", x"527", x"52B", x"530", x"534", x"538", x"53C", x"540", x"544", x"549", x"54D", x"551", x"555", x"55A", x"55E", x"563", x"567", x"56B", x"570", x"574", x"579", x"57D", x"582", x"586", x"58B", x"58F", x"594", x"599", x"59D", x"5A2", x"5A7", x"5AB", x"5B0", x"5B5", x"5B9", x"5BE", x"5C3", x"5C8", x"5CD", x"5D2", x"5D6", x"5DB", x"5E0", x"5E5", x"5EA", x"5EF", x"5F4", x"5F9", x"5FE", x"603", x"608", x"60D", x"612", x"617", x"61C", x"621", x"626", x"62C", x"631", x"636", x"63B", x"640", x"646", x"64B", x"650", x"655", x"65B", x"660", x"665", x"66A", x"670", x"675", x"67A", x"680", x"685", x"68B", x"690", x"695", x"69B", x"6A0", x"6A6", x"6AB", x"6B1", x"6B6", x"6BC", x"6C1", x"6C7", x"6CC", x"6D2", x"6D7", x"6DD", x"6E2", x"6E8", x"6ED", x"6F3", x"6F9", x"6FE", x"704", x"709", x"70F", x"715", x"71A", x"720", x"726", x"72B", x"731", x"737", x"73C", x"742", x"748", x"74D", x"753", x"759", x"75F", x"764", x"76A", x"770", x"775", x"77B", x"781", x"787", x"78C", x"792", x"798", x"79E", x"7A3", x"7A9", x"7AF", x"7B5", x"7BB", x"7C0", x"7C6", x"7CC", x"7D2", x"7D7", x"7DD", x"7E3", x"7E9", x"7EF", x"7F4", x"7FA"); -end package; diff --git a/src/sim/1kHz_max.vhd b/src/sim/1kHz_max.vhd deleted file mode 100644 index ab4a418..0000000 --- a/src/sim/1kHz_max.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sine_package is - type SINE_ARRAY_TYPE is array (0 to 1110) of std_logic_vector(11 downto 0); -constant sine : SINE_ARRAY_TYPE := (x"800", x"80C", x"817", x"823", x"82E", x"83A", x"845", x"851", x"85D", x"868", x"874", x"87F", x"88B", x"896", x"8A2", x"8AD", x"8B9", x"8C5", x"8D0", x"8DC", x"8E7", x"8F3", x"8FE", x"90A", x"915", x"920", x"92C", x"937", x"943", x"94E", x"95A", x"965", x"970", x"97C", x"987", x"993", x"99E", x"9A9", x"9B5", x"9C0", x"9CB", x"9D6", x"9E2", x"9ED", x"9F8", x"A03", x"A0F", x"A1A", x"A25", x"A30", x"A3B", x"A46", x"A51", x"A5C", x"A67", x"A72", x"A7E", x"A89", x"A93", x"A9E", x"AA9", x"AB4", x"ABF", x"ACA", x"AD5", x"AE0", x"AEA", x"AF5", x"B00", x"B0B", x"B15", x"B20", x"B2B", x"B35", x"B40", x"B4A", x"B55", x"B5F", x"B6A", x"B74", x"B7F", x"B89", x"B94", x"B9E", x"BA8", x"BB3", x"BBD", x"BC7", x"BD1", x"BDB", x"BE5", x"BF0", x"BFA", x"C04", x"C0E", x"C18", x"C22", x"C2B", x"C35", x"C3F", x"C49", x"C53", x"C5C", x"C66", x"C70", x"C79", x"C83", x"C8C", x"C96", x"C9F", x"CA9", x"CB2", x"CBC", x"CC5", x"CCE", x"CD7", x"CE1", x"CEA", x"CF3", x"CFC", x"D05", x"D0E", x"D17", x"D20", x"D29", x"D32", x"D3A", x"D43", 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x"A57", x"A4C", x"A41", x"A36", x"A2A", x"A1F", x"A14", x"A09", x"9FE", x"9F3", x"9E7", x"9DC", x"9D1", x"9C5", x"9BA", x"9AF", x"9A4", x"998", x"98D", x"982", x"976", x"96B", x"95F", x"954", x"949", x"93D", x"932", x"926", x"91B", x"90F", x"904", x"8F8", x"8ED", x"8E1", x"8D6", x"8CA", x"8BF", x"8B3", x"8A8", x"89C", x"891", x"885", x"879", x"86E", x"862", x"857", x"84B", x"840", x"834", x"829", x"81D", x"811", x"806", x"7FA", x"7EF", x"7E3", x"7D7", x"7CC", x"7C0", x"7B5", x"7A9", x"79E", x"792", x"787", x"77B", x"76F", x"764", x"758", x"74D", x"741", x"736", x"72A", x"71F", x"713", x"708", x"6FC", x"6F1", x"6E5", x"6DA", x"6CE", x"6C3", x"6B7", x"6AC", x"6A1", x"695", x"68A", x"67E", x"673", x"668", x"65C", x"651", x"646", x"63B", x"62F", x"624", x"619", x"60D", x"602", x"5F7", x"5EC", x"5E1", x"5D6", x"5CA", x"5BF", x"5B4", x"5A9", x"59E", x"593", x"588", x"57D", x"572", x"567", x"55C", x"551", x"546", x"53B", x"531", x"526", x"51B", x"510", x"505", x"4FB", x"4F0", x"4E5", x"4DB", x"4D0", x"4C5", x"4BB", x"4B0", x"4A6", x"49B", x"491", x"486", x"47C", x"472", x"467", x"45D", x"453", x"448", x"43E", x"434", x"42A", x"420", x"415", x"40B", x"401", x"3F7", x"3ED", x"3E3", x"3D9", x"3D0", x"3C6", x"3BC", x"3B2", x"3A8", x"39F", x"395", x"38B", x"382", x"378", x"36F", x"365", x"35C", x"352", x"349", x"340", x"336", x"32D", x"324", x"31B", x"312", x"309", x"300", x"2F7", x"2EE", x"2E5", x"2DC", x"2D3", x"2CA", x"2C1", x"2B9", x"2B0", x"2A7", x"29F", x"296", x"28E", x"285", x"27D", x"274", x"26C", x"264", x"25C", x"253", x"24B", x"243", x"23B", x"233", x"22B", x"223", x"21B", x"214", x"20C", x"204", x"1FD", x"1F5", x"1ED", x"1E6", x"1DE", x"1D7", x"1D0", x"1C8", x"1C1", x"1BA", x"1B3", x"1AC", x"1A5", x"19E", x"197", x"190", x"189", x"182", x"17B", x"175", x"16E", x"168", x"161", x"15B", x"154", x"14E", x"148", x"141", x"13B", x"135", x"12F", x"129", x"123", x"11D", x"117", x"111", x"10C", x"106", x"100", x"0FB", x"0F5", x"0F0", x"0EA", x"0E5", x"0E0", x"0DA", x"0D5", x"0D0", x"0CB", x"0C6", x"0C1", x"0BC", x"0B8", x"0B3", x"0AE", x"0AA", x"0A5", x"0A0", x"09C", x"098", x"093", x"08F", x"08B", x"087", x"083", x"07F", x"07B", x"077", x"073", x"06F", x"06B", x"068", x"064", x"061", x"05D", x"05A", x"056", x"053", x"050", x"04D", x"04A", x"047", x"044", x"041", x"03E", x"03B", x"038", x"036", x"033", x"031", x"02E", x"02C", x"02A", x"027", x"025", x"023", x"021", x"01F", x"01D", x"01B", x"019", x"018", x"016", x"014", x"013", x"011", x"010", x"00E", x"00D", x"00C", x"00B", x"00A", x"009", x"008", x"007", x"006", x"005", x"004", x"004", x"003", x"003", x"002", x"002", x"002", x"001", x"001", x"001", x"001", x"001", x"001", x"001", x"001", x"002", x"002", x"002", x"003", x"004", x"004", x"005", x"006", x"006", x"007", x"008", x"009", x"00A", x"00B", x"00C", x"00E", x"00F", x"010", x"012", x"013", x"015", x"017", x"018", x"01A", x"01C", x"01E", x"020", x"022", x"024", x"026", x"028", x"02B", x"02D", x"02F", x"032", x"035", x"037", x"03A", x"03D", x"03F", x"042", x"045", x"048", x"04B", x"04E", x"051", x"055", x"058", x"05B", x"05F", x"062", x"066", x"06A", x"06D", x"071", x"075", x"079", x"07D", x"081", x"085", x"089", x"08D", x"091", x"095", x"09A", x"09E", x"0A3", x"0A7", x"0AC", x"0B0", x"0B5", x"0BA", x"0BF", x"0C4", x"0C9", x"0CE", x"0D3", x"0D8", x"0DD", x"0E2", x"0E8", x"0ED", x"0F2", x"0F8", x"0FD", x"103", x"109", x"10E", x"114", x"11A", x"120", x"126", x"12C", x"132", x"138", x"13E", x"144", x"14B", x"151", x"157", x"15E", x"164", x"16B", x"171", x"178", x"17F", x"186", x"18C", x"193", x"19A", x"1A1", x"1A8", x"1AF", x"1B6", x"1BE", x"1C5", x"1CC", x"1D3", x"1DB", x"1E2", x"1EA", x"1F1", x"1F9", x"200", x"208", x"210", x"218", x"21F", x"227", x"22F", x"237", x"23F", x"247", x"24F", x"258", x"260", x"268", x"270", x"279", x"281", x"289", x"292", x"29A", x"2A3", x"2AC", x"2B4", x"2BD", x"2C6", x"2CE", x"2D7", x"2E0", x"2E9", x"2F2", x"2FB", x"304", x"30D", x"316", x"31F", x"329", x"332", x"33B", x"344", x"34E", x"357", x"361", x"36A", x"374", x"37D", x"387", x"390", x"39A", x"3A4", x"3AD", x"3B7", x"3C1", x"3CB", x"3D5", x"3DE", x"3E8", x"3F2", x"3FC", x"406", x"410", x"41B", x"425", x"42F", x"439", x"443", x"44D", x"458", x"462", x"46C", x"477", x"481", x"48C", x"496", x"4A1", x"4AB", x"4B6", x"4C0", x"4CB", x"4D5", x"4E0", x"4EB", x"4F5", x"500", x"50B", x"516", x"520", x"52B", x"536", x"541", x"54C", x"557", x"562", x"56D", x"577", x"582", x"58E", x"599", x"5A4", x"5AF", x"5BA", x"5C5", x"5D0", x"5DB", x"5E6", x"5F1", x"5FD", x"608", x"613", x"61E", x"62A", x"635", x"640", x"64B", x"657", x"662", x"66D", x"679", x"684", x"690", x"69B", x"6A6", x"6B2", x"6BD", x"6C9", x"6D4", x"6E0", x"6EB", x"6F6", x"702", x"70D", x"719", x"724", x"730", x"73B", x"747", x"753", x"75E", x"76A", x"775", x"781", x"78C", x"798", x"7A3", x"7AF", x"7BB", x"7C6", x"7D2", x"7DD", x"7E9", x"7F4"); -end package; diff --git a/src/sim/feedback_loop_tb.vhd b/src/sim/feedback_loop_tb.vhd index 257aef9..f735726 100644 --- a/src/sim/feedback_loop_tb.vhd +++ b/src/sim/feedback_loop_tb.vhd @@ -25,9 +25,10 @@ architecture beh of feedback_loop_tb is dac_sclk : out std_logic; -- PMOD-DA3 -- DYNAMIC CONFIGURATION addsub_mode : in std_logic; -- (1=ADD, 0=SUB) - add_input_mux : in std_logic; -- (1=ADC Input 2, 0=GND) - delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- unsigned delay clock count - factor : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point + add_input_mux : in std_logic; -- (1=Double Input 2, 0=Single Input) + delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- Unsigned delay clock count + factor1 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point + factor2 : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- Q1.x Fixed Point -- DEBUG reset_debug : in std_logic; adc_data1_max : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0); @@ -39,18 +40,34 @@ architecture beh of feedback_loop_tb is type ADC_STAGE_TYPE is (ZERO, DATA); + constant ZERO_SIGNAL : SIGNAL_RECORD_TYPE := ( + sine => (others => (others => '0')), + len => 1 + ); + constant HALF_SIGNAL : SIGNAL_RECORD_TYPE := ( + sine => (others => x"800"), + len => 1 + ); + --*****SIGNAL DECLARATION***** signal clk, reset : std_logic := '0'; signal adc_data_in1, adc_data_in2, adc_cs_n : std_logic := '0'; - signal factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); + signal factor1, factor2 : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); signal addsub_mode, add_input_mux : std_logic := '0'; signal delay : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0'); signal adc_stage : ADC_STAGE_TYPE := ZERO; - signal cnt1, cnt2 : integer := 0; + signal cnt1, cnt2, cnt3 : integer := 0; signal input1, input2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); signal output : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); - signal sine_done : std_logic := '0'; - + signal sig1, sig2 : SIGNAL_RECORD_TYPE := ZERO_SIGNAL; + + procedure wait_samples( num : in natural) is + begin + -- Num * Sampling Cadence * Clock Period + wait for num*18*50 ns; + wait until rising_edge(clk); + end procedure; + begin --*****COMPONENT INSTANTIATION***** @@ -69,7 +86,8 @@ begin addsub_mode => addsub_mode, add_input_mux => add_input_mux, delay => delay, - factor => factor, + factor1 => factor1, + factor2 => factor2, reset_debug => '0', adc_data1_max => open, adc_data2_max => open, @@ -92,50 +110,147 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; - --report "Single Input, Positive Feedback, Scale 1.32, Delay 0"; - --add_input_mux <= '0'; - --addsub_mode <= '1'; - --factor <= "10101"; --1.32 - --delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); - --wait until sine_done = '1'; - --report "Single Input, Negative Feedback, Scale 1.32, Delay 0"; - --add_input_mux <= '0'; - --addsub_mode <= '0'; - --factor <= "10101"; --1.32 - --delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); - --wait until sine_done = '1'; - --report "Single Input, Positive Feedback, Scale 0.66, Delay 0"; - --add_input_mux <= '0'; - --addsub_mode <= '1'; - --factor <= "01010"; --0.66 - --delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); - --wait until sine_done = '1'; - --report "Single Input, Positive Feedback, Scale 1.32, Delay 500"; - --add_input_mux <= '0'; - --addsub_mode <= '1'; - --factor <= "10101"; --1.32 - --delay <= std_logic_vector(to_unsigned(500,DELAY_WIDTH)); - --wait until sine_done = '1'; - --report "Double Input, Positive Feedback, Scale 0.66, Delay 0"; - --add_input_mux <= '1'; - --addsub_mode <= '1'; - --factor <= "01010"; --0.66 - --delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); - --wait until sine_done = '1'; - report "Double Input, Negative Feedback, Scale 1.32, Delay 0"; + report "Single Input, Signal 1 [MAX Amplitude, 10kHz], Positive Feedback, Scale 1"; + sig1 <= sine1; + sig2 <= ZERO_SIGNAL; + add_input_mux <= '0'; + addsub_mode <= '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Single Input, Signal 1 [MAX Amplitude, 10kHz], Negative Feedback, Scale 1"; + sig1 <= sine1; + sig2 <= ZERO_SIGNAL; + add_input_mux <= '0'; + addsub_mode <= '0'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Single Input, Signal 1 [DAC Adjusted MAX Amplitude, 10kHz], Positive Feedback, Scale 1.32"; + sig1 <= sine3; + sig2 <= ZERO_SIGNAL; + add_input_mux <= '0'; + addsub_mode <= '1'; + factor1 <= "10101"; --1.32 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine3.len); + report "Single Input, Signal 1 [MAX Amplitude, 10kHz], Positive Feedback, Scale 1.32"; + sig1 <= sine1; + sig2 <= ZERO_SIGNAL; + add_input_mux <= '0'; + addsub_mode <= '1'; + factor1 <= "10101"; --1.32 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Single Input, Signal 1 [MAX Amplitude, 10kHz], Positive Feedback, Scale 0.5"; + sig1 <= sine1; + sig2 <= ZERO_SIGNAL; + add_input_mux <= '0'; + addsub_mode <= '1'; + factor1 <= "01000"; --0.5 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [HALF Amplitude, 10kHz], Signal 2 [Static HALF], Positive Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= sine2; + sig2 <= HALF_SIGNAL; + add_input_mux <= '1'; + addsub_mode <= '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine2.len); + report "Double Input, Signal 1 [HALF Amplitude, 10kHz], Signal 2 [HALF Amplitude, 10kHz], Positive Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= sine2; + sig2 <= sine2; + add_input_mux <= '1'; + addsub_mode <= '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine2.len); + report "Double Input, Signal 1 [MAX Amplitude, 10kHz], Signal 2 [HALF Amplitude, 10kHz], Positive Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= sine1; + sig2 <= sine2; + add_input_mux <= '1'; + addsub_mode <= '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [MAX Amplitude, 10kHz], Signal 2 [MAX Amplitude, 10kHz], Positive Feedback, Scale1 0.75, Scale2 0.25, Delay 0"; + sig1 <= sine1; + sig2 <= sine1; + add_input_mux <= '1'; + addsub_mode <= '1'; + factor1 <= "01100"; --0.75 + factor2 <= "00100"; --0.25 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [HALF Amplitude, 10kHz], Signal 2 [HALF Amplitude, 10kHz], Negative Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= sine2; + sig2 <= sine2; add_input_mux <= '1'; addsub_mode <= '0'; - --factor <= "01010"; --0.66 - factor <= "10101"; --1.32 - delay <= std_logic_vector(to_unsigned(500,DELAY_WIDTH)); - wait until sine_done = '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine2.len); + report "Double Input, Signal 1 [MAX Amplitude, 10kHz], Signal 2 [HALF Amplitude, 10kHz], Negative Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= sine1; + sig2 <= sine2; + add_input_mux <= '1'; + addsub_mode <= '0'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [Static HALF], Signal 2 [MAX Amplitude, 10kHz], Negative Feedback, Scale1 1, Scale2 1, Delay 0"; + sig1 <= HALF_SIGNAL; + sig2 <= sine1; + add_input_mux <= '1'; + addsub_mode <= '0'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [MAX Amplitude, 10kHz], Signal 2 [HALF Amplitude, 10kHz], Negative Feedback, Scale1 1.32, Scale2 1, Delay 0"; + sig1 <= sine1; + sig2 <= sine2; + add_input_mux <= '1'; + addsub_mode <= '0'; + factor1 <= "10101"; --1.32 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH)); + wait_samples(sine1.len); + report "Double Input, Signal 1 [MAX Amplitude, 10kHz], Signal 2 [MAX Amplitude, 10kHz], Positive Feedback, Scale1 1, Scale2 1, Delay 1008"; + sig1 <= sine1; + sig2 <= sine1; + add_input_mux <= '1'; + addsub_mode <= '1'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(1008,DELAY_WIDTH)); + wait_samples(sine1.len+56); + report "Double Input, Signal 1 [HALF Amplitude, 10kHz], Signal 2 [MAX Amplitude, 10kHz], Negative Feedback, Scale1 1, Scale2 1, Delay 504"; + sig1 <= sine2; + sig2 <= sine1; + add_input_mux <= '1'; + addsub_mode <= '0'; + factor1 <= "10000"; --1.0 + factor2 <= "10000"; --1.0 + delay <= std_logic_vector(to_unsigned(504,DELAY_WIDTH)); + wait_samples(sine1.len+28); wait; end process; adc_prc : process (all) begin if rising_edge(clk) then - sine_done <= '0'; case (adc_stage) is when ZERO => if (adc_cs_n = '0') then @@ -147,14 +262,20 @@ begin end if; when DATA => if (adc_cs_n = '0') then - cnt1 <= cnt1 - 1; + cnt1 <= cnt1 - 1; if (cnt1 = 0) then - if (cnt2 = sine1'length-1) then - cnt2 <= 0; - sine_done <= '1'; + -- Signal 1 + if (cnt2 = sig1.len-1) then + cnt2 <= 0; else cnt2 <= cnt2 + 1; end if; + -- Signal 2 + if (cnt3 = sig2.len-1) then + cnt3 <= 0; + else + cnt3 <= cnt3 + 1; + end if; cnt1 <= 0; adc_stage <= ZERO; end if; @@ -167,24 +288,30 @@ begin adc_data_in1 <= '0'; adc_data_in2 <= '0'; when DATA => - adc_data_in1 <= sine1(cnt2)(cnt1); - adc_data_in2 <= sine2(cnt2)(cnt1); + adc_data_in1 <= sig1.sine(cnt2)(cnt1); + adc_data_in2 <= sig2.sine(cnt3)(cnt1); end case; end process; io_prc : process (all) - --alias in1 is <>; - --alias in2 is <>; - --alias in_done is <>; - alias in1 is <>; - alias in2 is <>; - alias out1 is <>; - alias out_done is <>; + alias in_done is <>; + alias in1 is <>; + alias in2 is <>; + alias out1 is <>; + alias out_done is <>; begin if rising_edge(clk) then - if (in1(ADC_DATA_WIDTH) = '1') then - input1 <= in1(ADC_DATA_WIDTH-1 downto 0); - input2 <= in2; + -- Signle Input Mode + if (add_input_mux = '0') then + if (in_done = '1') then + input1 <= in1; + input2 <= in2(ADC_DATA_WIDTH-1 downto 0); + end if; + else + if (in2(ADC_DATA_WIDTH) = '1') then + input1 <= in1; + input2 <= in2(ADC_DATA_WIDTH-1 downto 0); + end if; end if; if (out_done = '1') then output <= out1; diff --git a/src/sim/sine_package.vhd b/src/sim/sine_package.vhd new file mode 100644 index 0000000..ea317bd --- /dev/null +++ b/src/sim/sine_package.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package sine_package is + type SIGNAL_ARRAY_TYPE is array (0 to 1024) of std_logic_vector(11 downto 0); + type SIGNAL_RECORD_TYPE is record + sine : SIGNAL_ARRAY_TYPE; + len : natural; + end record; + + -- ZERO: 2048, AMPLITUDE: 2047, FREQUENCY: 10kHz + constant sine1 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"873", x"8E5", x"957", x"9C8", x"A37", x"AA4", x"B0F", x"B78", x"BDE", x"C41", x"CA1", x"CFC", x"D54", x"DA7", x"DF6", x"E40", x"E85", x"EC5", x"F00", x"F34", x"F63", x"F8C", x"FAF", x"FCC", x"FE2", x"FF2", x"FFC", x"FFF", x"FFC", x"FF2", x"FE2", x"FCC", x"FAF", x"F8C", x"F63", x"F34", x"F00", x"EC5", x"E85", x"E40", x"DF6", x"DA7", x"D54", x"CFC", x"CA1", x"C41", x"BDE", x"B78", x"B0F", x"AA4", x"A37", x"9C8", x"957", x"8E5", x"873", x"800", x"78D", x"71B", x"6A9", x"638", x"5C9", x"55C", x"4F1", x"488", x"422", x"3BF", x"35F", x"304", x"2AC", x"259", x"20A", x"1C0", x"17B", x"13B", x"100", x"0CC", x"09D", x"074", x"051", x"034", x"01E", x"00E", x"004", x"001", x"004", x"00E", x"01E", x"034", x"051", x"074", x"09D", x"0CC", x"100", x"13B", x"17B", x"1C0", x"20A", x"259", x"2AC", x"304", x"35F", x"3BF", x"422", x"488", x"4F1", x"55C", x"5C9", x"638", x"6A9", x"71B", x"78D", others => x"000"), + len => 112 + ); + -- ZERO: 2048, AMPLITUDE: 1024, FREQUENCY: 10kHz + constant sine2 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"839", x"873", x"8AC", x"8E4", x"91B", x"952", x"988", x"9BC", x"9EF", x"A21", x"A51", x"A7E", x"AAA", x"AD4", x"AFC", x"B21", x"B43", x"B63", x"B80", x"B9B", x"BB2", x"BC7", x"BD8", x"BE6", x"BF2", x"BFA", x"BFE", x"C00", x"BFE", x"BFA", x"BF2", x"BE6", x"BD8", x"BC7", x"BB2", x"B9B", x"B80", x"B63", x"B43", x"B21", x"AFC", x"AD4", x"AAA", x"A7E", x"A51", x"A21", x"9EF", x"9BC", x"988", x"952", x"91B", x"8E4", x"8AC", x"873", x"839", x"800", x"7C7", x"78D", x"754", x"71C", x"6E5", x"6AE", x"678", x"644", x"611", x"5DF", x"5AF", x"582", x"556", x"52C", x"504", x"4DF", x"4BD", x"49D", x"480", x"465", x"44E", x"439", x"428", x"41A", x"40E", x"406", x"402", x"400", x"402", x"406", x"40E", x"41A", x"428", x"439", x"44E", x"465", x"480", x"49D", x"4BD", x"4DF", x"504", x"52C", x"556", x"582", x"5AF", x"5DF", x"611", x"644", x"678", x"6AE", x"6E5", x"71C", x"754", x"78D", x"7C7", others => x"000"), + len => 112 + ); + -- ZERO: 2048, AMPLITUDE: 1551, FREQUENCY: 10kHz + constant sine3 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"857", x"8AE", x"904", x"959", x"9AD", x"A00", x"A52", x"AA1", x"AEE", x"B39", x"B82", x"BC7", x"C0A", x"C49", x"C84", x"CBD", x"CF1", x"D21", x"D4D", x"D75", x"D99", x"DB8", x"DD2", x"DE8", x"DF9", x"E05", x"E0D", x"E0F", x"E0D", x"E05", x"DF9", x"DE8", x"DD2", x"DB8", x"D99", x"D75", x"D4D", x"D21", x"CF1", x"CBD", x"C84", x"C49", x"C0A", x"BC7", x"B82", x"B39", x"AEE", x"AA1", x"A52", x"A00", x"9AD", x"959", x"904", x"8AE", x"857", x"800", x"7A9", x"752", x"6FC", x"6A7", x"653", x"600", x"5AE", x"55F", x"512", x"4C7", x"47E", x"439", x"3F6", x"3B7", x"37C", x"343", x"30F", x"2DF", x"2B3", x"28B", x"267", x"248", x"22E", x"218", x"207", x"1FB", x"1F3", x"1F1", x"1F3", x"1FB", x"207", x"218", x"22E", x"248", x"267", x"28B", x"2B3", x"2DF", x"30F", x"343", x"37C", x"3B7", x"3F6", x"439", x"47E", x"4C7", x"512", x"55F", x"5AE", x"600", x"653", x"6A7", x"6FC", x"752", x"7A9", others => x"000"), + len => 112 + ); + -- ZERO: 2048, AMPLITUDE: 2047, FREQUENCY: 20kHz + constant sine4 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"8E5", x"9C8", x"AA4", x"B78", x"C41", x"CFC", x"DA7", x"E40", x"EC5", x"F34", x"F8C", x"FCC", x"FF2", x"FFF", x"FF2", x"FCC", x"F8C", x"F34", x"EC5", x"E40", x"DA7", x"CFC", x"C41", x"B78", x"AA4", x"9C8", x"8E5", x"800", x"71B", x"638", x"55C", x"488", x"3BF", x"304", x"259", x"1C0", x"13B", x"0CC", x"074", x"034", x"00E", x"001", x"00E", x"034", x"074", x"0CC", x"13B", x"1C0", x"259", x"304", x"3BF", x"488", x"55C", x"638", x"71B", others => x"000"), + len => 56 + ); + -- ZERO: 2048, AMPLITUDE: 1024, FREQUENCY: 20kHz + constant sine5 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"873", x"8E4", x"952", x"9BC", x"A21", x"A7E", x"AD4", x"B21", x"B63", x"B9B", x"BC7", x"BE6", x"BFA", x"C00", x"BFA", x"BE6", x"BC7", x"B9B", x"B63", x"B21", x"AD4", x"A7E", x"A21", x"9BC", x"952", x"8E4", x"873", x"800", x"78D", x"71C", x"6AE", x"644", x"5DF", x"582", x"52C", x"4DF", x"49D", x"465", x"439", x"41A", x"406", x"400", x"406", x"41A", x"439", x"465", x"49D", x"4DF", x"52C", x"582", x"5DF", x"644", x"6AE", x"71C", x"78D", others => x"000"), + len => 56 + ); + -- ZERO: 2048, AMPLITUDE: 1551, FREQUENCY: 20kHz + constant sine6 : SIGNAL_RECORD_TYPE := ( + sine => (x"800", x"8AE", x"959", x"A00", x"AA1", x"B39", x"BC7", x"C49", x"CBD", x"D21", x"D75", x"DB8", x"DE8", x"E05", x"E0F", x"E05", x"DE8", x"DB8", x"D75", x"D21", x"CBD", x"C49", x"BC7", x"B39", x"AA1", x"A00", x"959", x"8AE", x"800", x"752", x"6A7", x"600", x"55F", x"4C7", x"439", x"3B7", x"343", x"2DF", x"28B", x"248", x"218", x"1FB", x"1F1", x"1FB", x"218", x"248", x"28B", x"2DF", x"343", x"3B7", x"439", x"4C7", x"55F", x"600", x"6A7", x"752", others => x"000"), + len => 56 + ); +end package; diff --git a/src/typedef_package.vhd b/src/typedef_package.vhd index 3065431..42d45cf 100644 --- a/src/typedef_package.vhd +++ b/src/typedef_package.vhd @@ -15,8 +15,8 @@ package typedef_package is constant ADC_DELAY_CLK_CNT : integer := 2; constant DAC_TRANSFER_CLK_COUNT : integer := 16; - constant MAX_DELAY : integer := 1024; - constant DELAY_WIDTH : integer := 10; --at least log2(MAX_DELAY) + constant MAX_DELAY : integer := 65536; + constant DELAY_WIDTH : integer := 16; --at least log2(MAX_DELAY) constant FACTOR_WIDTH : integer := 5; constant TIMESTAMP_WIDTH : integer := 32; diff --git a/src/xillybus_link.vhd b/src/xillybus_link.vhd index 99463dc..46a2ab4 100644 --- a/src/xillybus_link.vhd +++ b/src/xillybus_link.vhd @@ -14,7 +14,7 @@ use work.typedef_package.all; -- memory for configuration. The 32-bit wide 16-bit address interface is converted into 2 32-bit wide -- 15-bit address RAMs, effectively increasing the internal config to 64-bits. --- NOTE: It has to be made sure that the read and write port to not access the smae address at the same +-- NOTE: It has to be made sure that the read and write port do not access the same address at the same -- time entity xillybus_link is diff --git a/xillinux-syn/vivado/xillydemo.xpr b/xillinux-syn/vivado/xillydemo.xpr index 9139ae2..0f7d576 100644 --- a/xillinux-syn/vivado/xillydemo.xpr +++ b/xillinux-syn/vivado/xillydemo.xpr @@ -146,12 +146,6 @@ - - - - - - @@ -258,6 +252,7 @@