xilinx.com xci unknown 1.0 fifo_8x2048 100000000 0 0.000 100000000 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 100000000 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 0 0 0 0 0 0 0 1 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 1 0 11 BlankString 8 1 32 64 1 64 2 0 8 0 1 0 0 0 0 0 0 0 0 zynq 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 2 1 2 1 2 0 0 1 BlankString 1 0 0 0 1 0 2kx9 1kx18 512x36 1kx36 512x36 1kx36 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 2046 1023 1023 1023 1023 1023 1023 2045 0 0 0 0 0 0 0 0 0 11 2048 1 11 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 2048 1024 16 1024 16 1024 16 1 11 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_8x2048 64 false 11 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Distributed_RAM Common_Clock_Block_RAM Common_Clock_Distributed_RAM Common_Clock_Block_RAM Common_Clock_Distributed_RAM Common_Clock_Block_RAM 0 2046 1023 1023 1023 1023 1023 1023 2045 false false false 0 Native false false false false false false false false false false false false false false 8 2048 1024 16 1024 16 1024 16 false 8 2048 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 11 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Synchronous_Reset false 0 0 0 0 0 4 false false Active_High Active_High true false false false false Active_High 0 false Active_High 1 false 11 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO zynq xc7z020 clg484 VHDL MIXED -1 TRUE TRUE IP_Flow 3 TRUE . . 2018.3.1 OUT_OF_CONTEXT