create_clock -period 10.000 -name gclk [get_ports clk_100]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_100]

# Vivado constraints unrelated clocks. So set false paths.
set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks vga_clk_ins/*]
set_false_path -from [get_clocks vga_clk_ins/*] -to [get_clocks clk_fpga_1]

# The VGA outputs are turned into an analog voltage by virtue of a resistor
# network, so the flip flops driving these must sit in the IOBs to minimize
# timing skew. The RTL code should handle this, but the constraint below
# is there to fail if something goes wrong about this.
set_output_delay 5.500 [get_ports vga*]

set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports clk_100]
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[0]}]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[1]}]
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[2]}]
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[3]}]
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[0]}]
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[1]}]
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[2]}]
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[3]}]
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[0]}]
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[1]}]
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[2]}]
set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[3]}]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[0]}]
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[1]}]
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {vga4_red[2]}]
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {vga4_red[3]}]
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports vga_vsync]
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports vga_hsync]

# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin
# placement doesn't match the one given by Digilent.

# Pin for detecting USB OTG over-current condition
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_oc]

# Pins connected to sound chip
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[0]}]
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[1]}]
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33} [get_ports smb_sclk]
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports smb_sdata]

set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports audio_dac]
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports audio_adc]
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports audio_bclk]
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports audio_lrclk]
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports audio_mclk]


create_clock -period 100.000 -name sys_clk -waveform {0.000 50.000} [get_ports clk_ext]
#create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000}
#set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1]
#set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1]
#set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in2]
#set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in2]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -5.000 [get_ports adc_cs_n]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_cs_n]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_cs_n]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000 [get_ports dac_cs_n]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out]
#set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out]

set_property IOSTANDARD LVCMOS33 [get_ports adc_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in1]
set_property PACKAGE_PIN AB7 [get_ports adc_cs_n]
set_property PACKAGE_PIN AB6 [get_ports adc_data_in1]
set_property PACKAGE_PIN Y4 [get_ports adc_data_in2]
set_property PACKAGE_PIN AA4 [get_ports adc_sclk]
set_property PACKAGE_PIN V7 [get_ports dac_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports dac_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in2]
set_property IOSTANDARD LVCMOS33 [get_ports adc_sclk]
set_property PACKAGE_PIN W7 [get_ports dac_data_out]
set_property IOSTANDARD LVCMOS33 [get_ports dac_data_out]
set_property PACKAGE_PIN V5 [get_ports dac_ldac]
set_property IOSTANDARD LVCMOS33 [get_ports dac_ldac]
set_property PACKAGE_PIN V4 [get_ports dac_sclk]
set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk]
set_property PACKAGE_PIN AA9 [get_ports clk_ext]
set_property IOSTANDARD LVCMOS33 [get_ports clk_ext]
set_property PACKAGE_PIN Y11 [get_ports async_pulse]
set_property IOSTANDARD LVCMOS33 [get_ports async_pulse]
set_property PACKAGE_PIN U14 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}]
set_property PACKAGE_PIN U19 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}]
set_property PACKAGE_PIN W22 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
set_property PACKAGE_PIN V22 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]
set_property PACKAGE_PIN M15 [get_ports astandby]
set_property IOSTANDARD LVCMOS33 [get_ports astandby]
set_property PACKAGE_PIN P16 [get_ports areset]
set_property IOSTANDARD LVCMOS33 [get_ports areset]
set_property PACKAGE_PIN T18 [get_ports areset_debug]
set_property IOSTANDARD LVCMOS33 [get_ports areset_debug]