xillybus xillybus xillybus_ip 1.0 S_AXI AWADDR S_AXI_AWADDR AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WVALID S_AXI_WVALID WREADY S_AXI_WREADY BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARADDR S_AXI_ARADDR ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA RRESP S_AXI_RRESP RVALID S_AXI_RVALID RREADY S_AXI_RREADY m_axi AWADDR m_axi_awaddr AWLEN m_axi_awlen AWSIZE m_axi_awsize AWBURST m_axi_awburst AWCACHE m_axi_awcache AWPROT m_axi_awprot AWVALID m_axi_awvalid AWREADY m_axi_awready WDATA m_axi_wdata WSTRB m_axi_wstrb WLAST m_axi_wlast WVALID m_axi_wvalid WREADY m_axi_wready BRESP m_axi_bresp BVALID m_axi_bvalid BREADY m_axi_bready ARADDR m_axi_araddr ARLEN m_axi_arlen ARSIZE m_axi_arsize ARBURST m_axi_arburst ARCACHE m_axi_arcache ARPROT m_axi_arprot ARVALID m_axi_arvalid ARREADY m_axi_arready RDATA m_axi_rdata RRESP m_axi_rresp RLAST m_axi_rlast RVALID m_axi_rvalid RREADY m_axi_rready xillybus_M_AXI AWADDR xillybus_M_AXI_AWADDR AWLEN xillybus_M_AXI_AWLEN AWSIZE xillybus_M_AXI_AWSIZE AWBURST xillybus_M_AXI_AWBURST AWCACHE xillybus_M_AXI_AWCACHE AWPROT xillybus_M_AXI_AWPROT AWVALID xillybus_M_AXI_AWVALID AWREADY xillybus_M_AXI_AWREADY WDATA xillybus_M_AXI_WDATA WSTRB xillybus_M_AXI_WSTRB WLAST xillybus_M_AXI_WLAST WVALID xillybus_M_AXI_WVALID WREADY xillybus_M_AXI_WREADY BRESP xillybus_M_AXI_BRESP BVALID xillybus_M_AXI_BVALID BREADY xillybus_M_AXI_BREADY ARADDR xillybus_M_AXI_ARADDR ARLEN xillybus_M_AXI_ARLEN ARSIZE xillybus_M_AXI_ARSIZE ARBURST xillybus_M_AXI_ARBURST ARCACHE xillybus_M_AXI_ARCACHE ARPROT xillybus_M_AXI_ARPROT ARVALID xillybus_M_AXI_ARVALID ARREADY xillybus_M_AXI_ARREADY RDATA xillybus_M_AXI_RDATA RRESP xillybus_M_AXI_RRESP RLAST xillybus_M_AXI_RLAST RVALID xillybus_M_AXI_RVALID RREADY xillybus_M_AXI_RREADY xillybus_S_AXI AWADDR xillybus_S_AXI_AWADDR AWVALID xillybus_S_AXI_AWVALID AWREADY xillybus_S_AXI_AWREADY WDATA xillybus_S_AXI_WDATA WSTRB xillybus_S_AXI_WSTRB WVALID xillybus_S_AXI_WVALID WREADY xillybus_S_AXI_WREADY BRESP xillybus_S_AXI_BRESP BVALID xillybus_S_AXI_BVALID BREADY xillybus_S_AXI_BREADY ARADDR xillybus_S_AXI_ARADDR ARVALID xillybus_S_AXI_ARVALID ARREADY xillybus_S_AXI_ARREADY RDATA xillybus_S_AXI_RDATA RRESP xillybus_S_AXI_RRESP RVALID xillybus_S_AXI_RVALID RREADY xillybus_S_AXI_RREADY S_AXI_signal_reset RST S_AXI_ARESETN POLARITY ACTIVE_LOW m_axi_signal_reset RST m_axi_aresetn POLARITY ACTIVE_LOW S_AXI_signal_clock CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN m_axi_signal_clock CLK m_axi_aclk ASSOCIATED_BUSIF m_axi ASSOCIATED_RESET m_axi_aresetn signal_interrupt INTERRUPT Interrupt SENSITIVITY LEVEL_HIGH m_axi 4294967296 64 xillybus_S_AXI 4294967296 32 S_AXI reg0 0 4294967296 32 register xillybus_M_AXI reg0 0 4294967296 64 register xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog xillybus_ip xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog xillybus_ip xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset S_AXI_ACLK in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARESETN in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation Interrupt out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_AWVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_WDATA in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_BREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_ARADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_ARVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_RREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_ARREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RDATA out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_aclk in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_aresetn in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_arvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_araddr out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arlen out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arsize out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arburst out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arprot out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arcache out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_rready out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_rvalid in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rdata in 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rresp in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rlast in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_awready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_awvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awaddr out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awlen out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awsize out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awburst out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awprot out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awcache out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_wvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wdata out 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wstrb out 7 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wlast out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_bready out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_bvalid in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_bresp in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_bus_clk out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_bus_rst_n out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_AWADDR out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_AWVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_WDATA out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_WSTRB out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_WVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_BREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_ARADDR out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_ARVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_RREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_S_AXI_ARREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_RDATA in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_RRESP in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_RVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_WREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_BRESP in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_BVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_S_AXI_AWREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_ARREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_ARVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_ARADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_ARLEN in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_ARSIZE in 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_ARBURST in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 1 xillybus_M_AXI_ARPROT in 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_ARCACHE in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 3 xillybus_M_AXI_RREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_RVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_RDATA out 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_RRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_RLAST out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_AWREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_AWVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_AWADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_AWLEN in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_AWSIZE in 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_AWBURST in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 1 xillybus_M_AXI_AWPROT in 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_AWCACHE in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 3 xillybus_M_AXI_WREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_WVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_WDATA in 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_WSTRB in 7 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_WLAST in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_BREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 xillybus_M_AXI_BVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_M_AXI_BRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xillybus_host_interrupt in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 ACTIVE_HIGH ACTIVE_LOW choices_2 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choices_3 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING xilinx_verilogsynthesis_view_fileset xillybus.srcs/sources_1/imports/verilog/xillybus_ip.v verilogSource work xilinx_verilogbehavioralsimulation_view_fileset xillybus.srcs/sources_1/imports/verilog/xillybus_ip.v verilogSource work xilinx_xpgui_view_fileset xgui/xillybus_ip_v1_0.tcl tclSource XGUI_VERSION_2 Xillybus main IP core C_NATIVE_DATA_WIDTH C Native Data Width 64 C_MAX_BURST_LEN C Max Burst Len 256 C_SLV_DWIDTH C Slv Dwidth 64 C_SLV_AWIDTH C Slv Awidth 32 C_HIGHADDR C Highaddr 0x79C0FFFF C_BASEADDR C Baseaddr 0x79C00000 C_DPHASE_TIMEOUT C Dphase Timeout 8 C_USE_WSTRB C Use Wstrb 1 C_S_AXI_MIN_SIZE C S Axi Min Size 0x000001FF C_M_AXI_DATA_WIDTH C M Axi Data Width 64 C_M_AXI_ADDR_WIDTH C M Axi Addr Width 32 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 32 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 Component_Name xillybus_ip_v1_0 zynq /BaseIP xillybus_ip_v1_0 Xillybus Ltd. http://xillybus.com 1 2014-04-03T12:22:58Z 2013.4