xillybus xillybus xillybus_lite 1.0 S_AXI S_AXI AXI Lite slave ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA AWREADY S_AXI_AWREADY ARADDR S_AXI_ARADDR AWADDR S_AXI_AWADDR RRESP S_AXI_RRESP WDATA S_AXI_WDATA AWVALID S_AXI_AWVALID RREADY S_AXI_RREADY BREADY S_AXI_BREADY BVALID S_AXI_BVALID WSTRB S_AXI_WSTRB BRESP S_AXI_BRESP WVALID S_AXI_WVALID ARVALID S_AXI_ARVALID RVALID S_AXI_RVALID WREADY S_AXI_WREADY s_axi_clk s_axi_clk CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN s_axi_resetn s_axi_resetn RST S_AXI_ARESETN POLARITY ACTIVE_LOW host_interrupt host_interrupt INTERRUPT host_interrupt SENSITIVITY EDGE_RISING user 4G 32 S_AXI reg0 0 4294967296 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis xillybus_lite xilinx_anylanguagesynthesis_view_fileset xilinx_implementation Implementation :vivado.xilinx.com:implementation xillybus_lite xilinx_implementation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset S_AXI_ACLK in std_logic xilinx_anylanguagesynthesis S_AXI_ARESETN in std_logic xilinx_anylanguagesynthesis S_AXI_AWVALID in std_logic xilinx_anylanguagesynthesis 0 S_AXI_WVALID in std_logic xilinx_anylanguagesynthesis 0 S_AXI_BREADY in std_logic xilinx_anylanguagesynthesis 0 S_AXI_ARVALID in std_logic xilinx_anylanguagesynthesis 0 S_AXI_RREADY in std_logic xilinx_anylanguagesynthesis 0 user_irq in std_logic xilinx_anylanguagesynthesis S_AXI_ARREADY out std_logic xilinx_anylanguagesynthesis S_AXI_RVALID out std_logic xilinx_anylanguagesynthesis S_AXI_WREADY out std_logic xilinx_anylanguagesynthesis S_AXI_BVALID out std_logic xilinx_anylanguagesynthesis S_AXI_AWREADY out std_logic xilinx_anylanguagesynthesis host_interrupt out std_logic xilinx_anylanguagesynthesis user_clk out std_logic xilinx_anylanguagesynthesis user_wren out std_logic xilinx_anylanguagesynthesis user_rden out std_logic xilinx_anylanguagesynthesis S_AXI_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 S_AXI_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis S_AXI_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 user_rd_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis S_AXI_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis S_AXI_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis S_AXI_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis user_wstrb out 3 0 std_logic_vector xilinx_anylanguagesynthesis user_wr_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis user_addr out 31 0 std_logic_vector xilinx_anylanguagesynthesis choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choices_2 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING xilinx_anylanguagesynthesis_view_fileset $PPRDIR/../../../../system/pcores/xillybus_lite_v1_00_a/netlist/xillybus_lite.ngc ngc work xilinx_implementation_view_fileset $PPRDIR/../../../../system/pcores/xillybus_lite_v1_00_a/netlist/xillybus_lite.ngc ngc work xilinx_xpgui_view_fileset xgui/xillybus_lite_v1_0.tcl tclSource XGUI_VERSION_2 Xillybus Lite Component_Name xillybus_lite_v1_0 zynq /BaseIP xillybus_lite_v1_0 Xillybus Ltd. http://xillybus.com 1 2014-04-03T15:18:56Z 2013.4