xillybus xillybus xillyvga 1.0 S_AXI AWADDR S_AXI_AWADDR AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WVALID S_AXI_WVALID WREADY S_AXI_WREADY BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARADDR S_AXI_ARADDR ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA RRESP S_AXI_RRESP RVALID S_AXI_RVALID RREADY S_AXI_RREADY OFFSET_BASE_PARAM C_BASEADDR OFFSET_HIGH_PARAM C_HIGHADDR m_axi AWADDR m_axi_awaddr AWLEN m_axi_awlen AWSIZE m_axi_awsize AWBURST m_axi_awburst AWCACHE m_axi_awcache AWPROT m_axi_awprot AWVALID m_axi_awvalid AWREADY m_axi_awready WDATA m_axi_wdata WSTRB m_axi_wstrb WLAST m_axi_wlast WVALID m_axi_wvalid WREADY m_axi_wready BRESP m_axi_bresp BVALID m_axi_bvalid BREADY m_axi_bready ARADDR m_axi_araddr ARLEN m_axi_arlen ARSIZE m_axi_arsize ARBURST m_axi_arburst ARCACHE m_axi_arcache ARPROT m_axi_arprot ARVALID m_axi_arvalid ARREADY m_axi_arready RDATA m_axi_rdata RRESP m_axi_rresp RLAST m_axi_rlast RVALID m_axi_rvalid RREADY m_axi_rready S_AXI_signal_reset RST S_AXI_ARESETN POLARITY ACTIVE_LOW m_axi_signal_reset RST m_axi_aresetn POLARITY ACTIVE_LOW S_AXI_signal_clock CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN m_axi_signal_clock CLK m_axi_aclk ASSOCIATED_BUSIF m_axi ASSOCIATED_RESET m_axi_aresetn m_axi 4294967296 32 S_AXI reg0 0 4294967296 32 register xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog xillyvga xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog xillyvga xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset S_AXI_ACLK in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_ARESETN in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_AWADDR in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_AWVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_BREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_RREADY in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_WDATA in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WVALID in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 clk_in in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_aclk in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_aresetn in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_awready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_bresp in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_bvalid in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rdata in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rlast in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rresp in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_rvalid in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m_axi_wready in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 S_AXI_ARREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RDATA out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RRESP out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RVALID out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WREADY out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_araddr out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arburst out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arcache out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arlen out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arprot out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arsize out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_arvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awaddr out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awburst out 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awcache out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awlen out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awprot out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awsize out 2 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_awvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_bready out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_rready out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wdata out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wlast out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wstrb out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m_axi_wvalid out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_clk out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_blue out 7 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_green out 7 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_hsync out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_red out 7 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_vsync out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation vga_de out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset xillyvga.srcs/sources_1/imports/verilog/xillyvga_core.v verilogSource work xillyvga.srcs/sources_1/imports/verilog/xillyvga.v verilogSource work xilinx_verilogbehavioralsimulation_view_fileset xillyvga.srcs/sources_1/imports/verilog/xillyvga_core.v verilogSource work xillyvga.srcs/sources_1/imports/verilog/xillyvga.v verilogSource work xilinx_xpgui_view_fileset xgui/xillyvga_v1_0.tcl tclSource XGUI_VERSION_2 VGA adapter for Xillinux C_NATIVE_DATA_WIDTH C Native Data Width 32 C_MAX_BURST_LEN C Max Burst Len 16 C_SLV_DWIDTH C Slv Dwidth 32 C_SLV_AWIDTH C Slv Awidth 32 C_HIGHADDR C Highaddr 0x79C0FFFF C_BASEADDR C Baseaddr 0x79C00000 C_DPHASE_TIMEOUT C Dphase Timeout 8 C_USE_WSTRB C Use Wstrb 1 C_S_AXI_MIN_SIZE C S Axi Min Size 0x000001FF C_M_AXI_DATA_WIDTH C M Axi Data Width 32 C_M_AXI_ADDR_WIDTH C M Axi Addr Width 32 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 32 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 Component_Name xillyvga_v1_0 zynq /BaseIP xillyvga_v1_0 Xillybus http://xillybus.com/xillinux 1 2014-04-02T09:53:17Z 2013.4