library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity open_loop_tb is
end entity;

architecture beh of open_loop_tb is
    
    --*****SIGNAL DECLARATION*****
    signal clk, reset, adc_data_in, adc_cs_n, dac_data_out, dac_cs_n, dac_ldac : std_logic := '0';
    
    --*****COMPONENT DECLARATION*****
    component open_loop is
        port (
            clk             : in std_logic;
            areset          : in std_logic;
            adc_data_in     : in std_logic;
            adc_cs_n        : out std_logic;
            dac_data_out    : out std_logic;
            dac_cs_n        : out std_logic;
            dac_ldac        : out std_logic
        );
    end component;

begin

    --*****COMPONENT INSTANTIATION*****
    uut : open_loop
    port map(
        clk             => clk,
        areset          => reset,
        adc_data_in     => '1',
        adc_cs_n        => adc_cs_n,
        dac_data_out    => dac_data_out,
        dac_cs_n        => dac_cs_n,
        dac_ldac        => dac_ldac
    );

    clk_prc : process
    begin
        clk <= '1';
        wait for 25 ns;
        clk <= '0';
        wait for 25 ns;
    end process;
    
    process
    begin
        --INITIALISE SIGNALS
        reset   <= '1';
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        wait;
    end process;

end architecture;