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labor-mst/xillinux-syn/vivado-essentials
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Greek 89182e8060 * Route sclk for ADC/DAC through controller entity itself 
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
	- Invert SCLK
2020-04-29 14:01:01 +02:00
..
fifo_8x2048 * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
fifo_32x512 * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
vga_fifo * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
vivado_system * Modify xillinux vivado project 2020-04-26 17:53:15 +02:00
vivado-ip * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
showstopper.tcl * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
system.v * Modify xillinux vivado project 2020-04-26 17:53:15 +02:00
xillydemo.xdc * Route sclk for ADC/DAC through controller entity itself 2020-04-29 14:01:01 +02:00