401 lines
14 KiB
VHDL
401 lines
14 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.typedef_package.all;
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entity xillydemo is
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port (
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clk_100 : IN std_logic;
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otg_oc : IN std_logic;
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
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vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
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vga4_green : OUT std_logic_vector(3 DOWNTO 0);
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vga4_red : OUT std_logic_vector(3 DOWNTO 0);
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vga_hsync : OUT std_logic;
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vga_vsync : OUT std_logic;
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audio_mclk : OUT std_logic;
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audio_dac : OUT std_logic;
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audio_adc : IN std_logic;
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audio_bclk : IN std_logic;
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audio_lrclk : IN std_logic;
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smb_sclk : OUT std_logic;
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smb_sdata : INOUT std_logic;
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smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
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--FEEDBACK_TOP
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clk_ext : in std_logic;
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areset : in std_logic;
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areset_debug : in std_logic;
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async_pulse : in std_logic;
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astandby : in std_logic;
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adc_data_in1 : in std_logic;
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adc_data_in2 : in std_logic;
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adc_cs_n : out std_logic;
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adc_sclk : out std_logic;
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic;
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dac_sclk : out std_logic
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);
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end xillydemo;
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architecture sample_arch of xillydemo is
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component xillybus
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port (
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PS_CLK : IN std_logic;
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PS_PORB : IN std_logic;
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PS_SRSTB : IN std_logic;
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clk_100 : IN std_logic;
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otg_oc : IN std_logic;
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DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
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DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
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DDR_CAS_n : INOUT std_logic;
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DDR_CKE : INOUT std_logic;
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DDR_CS_n : INOUT std_logic;
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DDR_Clk : INOUT std_logic;
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DDR_Clk_n : INOUT std_logic;
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DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
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DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
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DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
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DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
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DDR_DRSTB : INOUT std_logic;
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DDR_ODT : INOUT std_logic;
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DDR_RAS_n : INOUT std_logic;
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DDR_VRN : INOUT std_logic;
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DDR_VRP : INOUT std_logic;
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MIO : INOUT std_logic_vector(53 DOWNTO 0);
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DDR_WEB : OUT std_logic;
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
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bus_clk : OUT std_logic;
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quiesce : OUT std_logic;
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vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
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vga4_green : OUT std_logic_vector(3 DOWNTO 0);
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vga4_red : OUT std_logic_vector(3 DOWNTO 0);
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vga_hsync : OUT std_logic;
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vga_vsync : OUT std_logic;
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user_r_audio_rden : OUT std_logic;
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user_r_audio_empty : IN std_logic;
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user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
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user_r_audio_eof : IN std_logic;
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user_r_audio_open : OUT std_logic;
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user_w_audio_wren : OUT std_logic;
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user_w_audio_full : IN std_logic;
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user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
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user_w_audio_open : OUT std_logic;
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user_w_config_wren : OUT std_logic;
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user_w_config_full : IN std_logic;
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user_w_config_data : OUT std_logic_vector(31 DOWNTO 0);
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user_w_config_open : OUT std_logic;
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user_config_addr : OUT std_logic_vector(15 DOWNTO 0);
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user_config_addr_update : OUT std_logic;
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user_r_debug_rden : OUT std_logic;
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user_r_debug_empty : IN std_logic;
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user_r_debug_data : IN std_logic_vector(31 DOWNTO 0);
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user_r_debug_eof : IN std_logic;
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user_r_debug_open : OUT std_logic;
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user_r_smb_rden : OUT std_logic;
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user_r_smb_empty : IN std_logic;
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user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
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user_r_smb_eof : IN std_logic;
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user_r_smb_open : OUT std_logic;
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user_w_smb_wren : OUT std_logic;
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user_w_smb_full : IN std_logic;
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user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
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user_w_smb_open : OUT std_logic;
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user_clk : OUT std_logic;
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user_wren : OUT std_logic;
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user_rden : OUT std_logic;
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user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
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user_addr : OUT std_logic_vector(31 DOWNTO 0);
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user_rd_data : IN std_logic_vector(31 DOWNTO 0);
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user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
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user_irq : IN std_logic);
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end component;
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component i2s_audio
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port (
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bus_clk : IN std_logic;
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clk_100 : IN std_logic;
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quiesce : IN std_logic;
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audio_mclk : OUT std_logic;
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audio_dac : OUT std_logic;
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audio_adc : IN std_logic;
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audio_bclk : IN std_logic;
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audio_lrclk : IN std_logic;
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user_r_audio_rden : IN std_logic;
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user_r_audio_empty : OUT std_logic;
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user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
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user_r_audio_eof : OUT std_logic;
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user_r_audio_open : IN std_logic;
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user_w_audio_wren : IN std_logic;
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user_w_audio_full : OUT std_logic;
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user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
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user_w_audio_open : IN std_logic);
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end component;
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component smbus
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port (
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bus_clk : IN std_logic;
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quiesce : IN std_logic;
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smb_sclk : OUT std_logic;
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smb_sdata : INOUT std_logic;
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smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
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user_r_smb_rden : IN std_logic;
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user_r_smb_empty : OUT std_logic;
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user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
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user_r_smb_eof : OUT std_logic;
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user_r_smb_open : IN std_logic;
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user_w_smb_wren : IN std_logic;
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user_w_smb_full : OUT std_logic;
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user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
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user_w_smb_open : IN std_logic);
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end component;
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component feedback_top is
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port (
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--XILLYBUS
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xillybus_clk : in std_logic;
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fifo_rd_data : out std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0);
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fifo_ren : in std_logic;
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fifo_empty : out std_logic;
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mem_addr : in std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0);
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mem_wr_data : in std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0);
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mem_wen : in std_logic;
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mem_full : out std_logic;
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--FPGA
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clk_in : in std_logic;
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areset : in std_logic;
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areset_debug : in std_logic;
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async_pulse : in std_logic;
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astandby : in std_logic;
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adc_data_in1 : in std_logic;
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adc_data_in2 : in std_logic;
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adc_cs_n : out std_logic;
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adc_sclk : out std_logic;
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic;
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dac_sclk : out std_logic
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);
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end component;
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signal bus_clk : std_logic;
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signal quiesce : std_logic;
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signal user_r_audio_rden : std_logic;
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signal user_r_audio_empty : std_logic;
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signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
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signal user_r_audio_eof : std_logic;
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signal user_r_audio_open : std_logic;
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signal user_w_audio_wren : std_logic;
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signal user_w_audio_full : std_logic;
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signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
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signal user_w_audio_open : std_logic;
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signal user_r_smb_rden : std_logic;
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signal user_r_smb_empty : std_logic;
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signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
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signal user_r_smb_eof : std_logic;
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signal user_r_smb_open : std_logic;
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signal user_w_smb_wren : std_logic;
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signal user_w_smb_full : std_logic;
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signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
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signal user_w_smb_open : std_logic;
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-- Note that none of the ARM processor's direct connections to pads is
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-- defined as I/O on this module. Normally, they should be connected
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-- as toplevel ports here, but that confuses Vivado 2013.4 to think that
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-- some of these ports are real I/Os, causing an implementation failure.
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-- This detachment results in a lot of warnings during synthesis and
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-- implementation, but has no practical significance, as these pads are
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-- completely unrelated to the FPGA bitstream.
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signal PS_CLK : std_logic;
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signal PS_PORB : std_logic;
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signal PS_SRSTB : std_logic;
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signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
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signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
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signal DDR_CAS_n : std_logic;
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signal DDR_CKE : std_logic;
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signal DDR_CS_n : std_logic;
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signal DDR_Clk : std_logic;
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signal DDR_Clk_n : std_logic;
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signal DDR_DM : std_logic_vector(3 DOWNTO 0);
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signal DDR_DQ : std_logic_vector(31 DOWNTO 0);
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signal DDR_DQS : std_logic_vector(3 DOWNTO 0);
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signal DDR_DQS_n : std_logic_vector(3 DOWNTO 0);
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signal DDR_DRSTB : std_logic;
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signal DDR_ODT : std_logic;
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signal DDR_RAS_n : std_logic;
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signal DDR_VRN : std_logic;
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signal DDR_VRP : std_logic;
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signal MIO : std_logic_vector(53 DOWNTO 0);
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signal DDR_WEB : std_logic;
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signal user_r_debug_data : std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0) := (others => '0');
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signal user_r_debug_rden, user_r_debug_empty : std_logic := '0';
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signal user_config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0) := (others => '0');
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signal user_w_config_data : std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0) := (others => '0');
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signal user_w_config_wren, user_w_config_full : std_logic := '0';
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begin
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xillybus_ins : xillybus
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port map (
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-- Ports related to /dev/xillybus_config
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-- CPU to FPGA signals:
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user_w_config_wren => user_w_config_wren,
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user_w_config_full => user_w_config_full,
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user_w_config_data => user_w_config_data,
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user_w_config_open => open,
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-- Address signals:
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user_config_addr => user_config_addr,
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user_config_addr_update => open,
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-- Ports related to /dev/xillybus_debug
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-- FPGA to CPU signals:
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user_r_debug_rden => user_r_debug_rden,
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user_r_debug_empty => user_r_debug_empty,
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user_r_debug_data => user_r_debug_data,
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user_r_debug_eof => '0',
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user_r_debug_open => open,
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-- Ports related to Xillybus Lite
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-- UNUSED
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user_clk => open,
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user_wren => open,
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user_wstrb => open,
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user_rden => open,
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user_rd_data => (others => '0'),
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user_wr_data => open,
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user_addr => open,
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user_irq => '0',
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-- Ports related to /dev/xillybus_audio
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-- FPGA to CPU signals:
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user_r_audio_rden => user_r_audio_rden,
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user_r_audio_empty => user_r_audio_empty,
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user_r_audio_data => user_r_audio_data,
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user_r_audio_eof => user_r_audio_eof,
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user_r_audio_open => user_r_audio_open,
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-- CPU to FPGA signals:
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user_w_audio_wren => user_w_audio_wren,
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user_w_audio_full => user_w_audio_full,
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user_w_audio_data => user_w_audio_data,
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user_w_audio_open => user_w_audio_open,
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-- Ports related to /dev/xillybus_smb
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-- FPGA to CPU signals:
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user_r_smb_rden => user_r_smb_rden,
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user_r_smb_empty => user_r_smb_empty,
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user_r_smb_data => user_r_smb_data,
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user_r_smb_eof => user_r_smb_eof,
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user_r_smb_open => user_r_smb_open,
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-- CPU to FPGA signals:
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user_w_smb_wren => user_w_smb_wren,
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user_w_smb_full => user_w_smb_full,
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user_w_smb_data => user_w_smb_data,
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user_w_smb_open => user_w_smb_open,
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-- General signals
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PS_CLK => PS_CLK,
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PS_PORB => PS_PORB,
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PS_SRSTB => PS_SRSTB,
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clk_100 => clk_100,
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otg_oc => otg_oc,
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DDR_Addr => DDR_Addr,
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DDR_BankAddr => DDR_BankAddr,
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DDR_CAS_n => DDR_CAS_n,
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DDR_CKE => DDR_CKE,
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DDR_CS_n => DDR_CS_n,
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DDR_Clk => DDR_Clk,
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DDR_Clk_n => DDR_Clk_n,
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DDR_DM => DDR_DM,
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DDR_DQ => DDR_DQ,
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DDR_DQS => DDR_DQS,
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DDR_DQS_n => DDR_DQS_n,
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DDR_DRSTB => DDR_DRSTB,
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DDR_ODT => DDR_ODT,
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DDR_RAS_n => DDR_RAS_n,
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DDR_VRN => DDR_VRN,
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DDR_VRP => DDR_VRP,
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MIO => MIO,
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DDR_WEB => DDR_WEB,
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GPIO_LED => GPIO_LED,
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bus_clk => bus_clk,
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quiesce => quiesce,
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vga4_blue => vga4_blue,
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vga4_green => vga4_green,
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vga4_red => vga4_red,
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vga_hsync => vga_hsync,
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vga_vsync => vga_vsync
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);
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feedback_inst : feedback_top
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port map (
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--XILLYBUS
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xillybus_clk => bus_clk,
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fifo_rd_data => user_r_debug_data,
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fifo_ren => user_r_debug_rden,
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fifo_empty => user_r_debug_empty,
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mem_addr => user_config_addr,
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mem_wr_data => user_w_config_data,
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mem_wen => user_w_config_wren,
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mem_full => user_w_config_full,
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--FPGA
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clk_in => clk_ext,
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areset => areset,
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areset_debug => areset_debug,
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async_pulse => async_pulse,
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astandby => astandby,
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adc_data_in1 => adc_data_in1,
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adc_data_in2 => adc_data_in2,
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adc_cs_n => adc_cs_n,
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adc_sclk => adc_sclk,
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dac_data_out => dac_data_out,
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dac_cs_n => dac_cs_n,
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dac_ldac => dac_ldac,
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dac_sclk => dac_sclk
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);
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audio_ins : i2s_audio
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port map(
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bus_clk => bus_clk,
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clk_100 => clk_100,
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quiesce => quiesce,
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audio_mclk => audio_mclk,
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audio_dac => audio_dac,
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audio_adc => audio_adc,
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audio_bclk => audio_bclk,
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audio_lrclk => audio_lrclk,
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user_r_audio_rden => user_r_audio_rden,
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user_r_audio_empty => user_r_audio_empty,
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user_r_audio_data => user_r_audio_data,
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user_r_audio_eof => user_r_audio_eof,
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user_r_audio_open => user_r_audio_open,
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user_w_audio_wren => user_w_audio_wren,
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user_w_audio_full => user_w_audio_full,
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user_w_audio_data => user_w_audio_data,
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user_w_audio_open => user_w_audio_open
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);
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smbus_ins : smbus
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port map(
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bus_clk => bus_clk,
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quiesce => quiesce,
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smb_sclk => smb_sclk,
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smb_sdata => smb_sdata,
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smbus_addr => smbus_addr,
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user_r_smb_rden => user_r_smb_rden,
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user_r_smb_empty => user_r_smb_empty,
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user_r_smb_data => user_r_smb_data,
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user_r_smb_eof => user_r_smb_eof,
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user_r_smb_open => user_r_smb_open,
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user_w_smb_wren => user_w_smb_wren,
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user_w_smb_full => user_w_smb_full,
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user_w_smb_data => user_w_smb_data,
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user_w_smb_open => user_w_smb_open
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);
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end sample_arch;
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