185 lines
7.8 KiB
Verilog
185 lines
7.8 KiB
Verilog
// Wrapper for vivado_system. This matches the signals' names in XPS with
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// those of Vivado.
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module system (
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inout [53:0] processing_system7_0_MIO,
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input processing_system7_0_PS_SRSTB,
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input processing_system7_0_PS_CLK,
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input processing_system7_0_PS_PORB,
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inout processing_system7_0_DDR_Clk,
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inout processing_system7_0_DDR_Clk_n,
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inout processing_system7_0_DDR_CKE,
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inout processing_system7_0_DDR_CS_n,
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inout processing_system7_0_DDR_RAS_n,
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inout processing_system7_0_DDR_CAS_n,
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output processing_system7_0_DDR_WEB,
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inout [2:0] processing_system7_0_DDR_BankAddr,
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inout [14:0] processing_system7_0_DDR_Addr,
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inout processing_system7_0_DDR_ODT,
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inout processing_system7_0_DDR_DRSTB,
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inout [31:0] processing_system7_0_DDR_DQ,
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inout [3:0] processing_system7_0_DDR_DM,
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inout [3:0] processing_system7_0_DDR_DQS,
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inout [3:0] processing_system7_0_DDR_DQS_n,
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inout processing_system7_0_DDR_VRN,
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inout processing_system7_0_DDR_VRP,
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output xillybus_bus_clk,
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output xillybus_bus_rst_n,
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output [31:0] xillybus_S_AXI_AWADDR,
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output xillybus_S_AXI_AWVALID,
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output [31:0] xillybus_S_AXI_WDATA,
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output [3:0] xillybus_S_AXI_WSTRB,
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output xillybus_S_AXI_WVALID,
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output xillybus_S_AXI_BREADY,
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output [31:0] xillybus_S_AXI_ARADDR,
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output xillybus_S_AXI_ARVALID,
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output xillybus_S_AXI_RREADY,
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input xillybus_S_AXI_ARREADY,
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input [31:0] xillybus_S_AXI_RDATA,
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input [1:0] xillybus_S_AXI_RRESP,
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input xillybus_S_AXI_RVALID,
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input xillybus_S_AXI_WREADY,
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input [1:0] xillybus_S_AXI_BRESP,
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input xillybus_S_AXI_BVALID,
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input xillybus_S_AXI_AWREADY,
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output xillybus_M_AXI_ARREADY,
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input xillybus_M_AXI_ARVALID,
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input [31:0] xillybus_M_AXI_ARADDR,
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input [3:0] xillybus_M_AXI_ARLEN,
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input [2:0] xillybus_M_AXI_ARSIZE,
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input [1:0] xillybus_M_AXI_ARBURST,
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input [2:0] xillybus_M_AXI_ARPROT,
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input [3:0] xillybus_M_AXI_ARCACHE,
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input xillybus_M_AXI_RREADY,
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output xillybus_M_AXI_RVALID,
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output [63:0] xillybus_M_AXI_RDATA,
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output [1:0] xillybus_M_AXI_RRESP,
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output xillybus_M_AXI_RLAST,
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output xillybus_M_AXI_AWREADY,
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input xillybus_M_AXI_AWVALID,
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input [31:0] xillybus_M_AXI_AWADDR,
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input [3:0] xillybus_M_AXI_AWLEN,
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input [2:0] xillybus_M_AXI_AWSIZE,
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input [1:0] xillybus_M_AXI_AWBURST,
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input [2:0] xillybus_M_AXI_AWPROT,
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input [3:0] xillybus_M_AXI_AWCACHE,
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output xillybus_M_AXI_WREADY,
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input xillybus_M_AXI_WVALID,
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input [63:0] xillybus_M_AXI_WDATA,
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input [7:0] xillybus_M_AXI_WSTRB,
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input xillybus_M_AXI_WLAST,
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input xillybus_M_AXI_BREADY,
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output xillybus_M_AXI_BVALID,
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output [1:0] xillybus_M_AXI_BRESP,
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input xillybus_host_interrupt,
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input xillyvga_0_clk_in,
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output xillyvga_0_vga_hsync,
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output xillyvga_0_vga_vsync,
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output xillyvga_0_vga_de,
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output [7:0] xillyvga_0_vga_red,
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output [7:0] xillyvga_0_vga_green,
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output [7:0] xillyvga_0_vga_blue,
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output xillyvga_0_vga_clk,
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input processing_system7_0_USB0_VBUS_PWRFAULT,
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output xillybus_lite_0_user_clk_pin,
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output xillybus_lite_0_user_wren_pin,
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output [3:0] xillybus_lite_0_user_wstrb_pin,
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output xillybus_lite_0_user_rden_pin,
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input [31:0] xillybus_lite_0_user_rd_data_pin,
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output [31:0] xillybus_lite_0_user_wr_data_pin,
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output [31:0] xillybus_lite_0_user_addr_pin,
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input xillybus_lite_0_user_irq_pin
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);
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vivado_system vivado_system_i
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(.DDR_addr(processing_system7_0_DDR_Addr),
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.DDR_ba(processing_system7_0_DDR_BankAddr),
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.DDR_cas_n(processing_system7_0_DDR_CAS_n),
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.DDR_ck_n(processing_system7_0_DDR_Clk_n),
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.DDR_ck_p(processing_system7_0_DDR_Clk_p),
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.DDR_cke(processing_system7_0_DDR_CKE),
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.DDR_cs_n(processing_system7_0_DDR_CS_n),
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.DDR_dm(processing_system7_0_DDR_DM),
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.DDR_dq(processing_system7_0_DDR_DQ),
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.DDR_dqs_n(processing_system7_0_DDR_DQS_n),
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.DDR_dqs_p(processing_system7_0_DDR_DQS),
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.DDR_odt(processing_system7_0_DDR_ODT),
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.DDR_ras_n(processing_system7_0_DDR_RAS_n),
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.DDR_reset_n(processing_system7_0_DDR_DRSTB),
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.DDR_we_n(processing_system7_0_DDR_WEB),
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.FIXED_IO_ddr_vrn(processing_system7_0_DDR_VRN),
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.FIXED_IO_ddr_vrp(processing_system7_0_DDR_VRP),
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.FIXED_IO_mio(processing_system7_0_MIO),
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.FIXED_IO_ps_clk(processing_system7_0_PS_CLK),
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.FIXED_IO_ps_porb(processing_system7_0_PS_PORB),
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.FIXED_IO_ps_srstb(processing_system7_0_PS_SRSTB),
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.USBIND_0_port_indctl(),
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.USBIND_0_vbus_pwrfault(processing_system7_0_USB0_VBUS_PWRFAULT),
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.USBIND_0_vbus_pwrselect(),
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.clk_in(xillyvga_0_clk_in),
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.user_addr(xillybus_lite_0_user_addr_pin),
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.user_clk(xillybus_lite_0_user_clk_pin),
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.user_irq(xillybus_lite_0_user_irq_pin),
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.user_rd_data(xillybus_lite_0_user_rd_data_pin),
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.user_rden(xillybus_lite_0_user_rden_pin),
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.user_wr_data(xillybus_lite_0_user_wr_data_pin),
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.user_wren(xillybus_lite_0_user_wren_pin),
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.user_wstrb(xillybus_lite_0_user_wstrb_pin),
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.vga_blue(xillyvga_0_vga_blue),
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.vga_clk(xillyvga_0_vga_clk),
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.vga_de(xillyvga_0_vga_de),
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.vga_green(xillyvga_0_vga_green),
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.vga_hsync(xillyvga_0_vga_hsync),
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.vga_red(xillyvga_0_vga_red),
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.vga_vsync(xillyvga_0_vga_vsync),
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.xillybus_M_AXI_araddr(xillybus_M_AXI_ARADDR),
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.xillybus_M_AXI_arburst(xillybus_M_AXI_ARBURST),
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.xillybus_M_AXI_arcache(xillybus_M_AXI_ARCACHE),
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.xillybus_M_AXI_arlen(xillybus_M_AXI_ARLEN),
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.xillybus_M_AXI_arprot(xillybus_M_AXI_ARPROT),
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.xillybus_M_AXI_arready(xillybus_M_AXI_ARREADY),
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.xillybus_M_AXI_arsize(xillybus_M_AXI_ARSIZE),
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.xillybus_M_AXI_arvalid(xillybus_M_AXI_ARVALID),
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.xillybus_M_AXI_awaddr(xillybus_M_AXI_AWADDR),
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.xillybus_M_AXI_awburst(xillybus_M_AXI_AWBURST),
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.xillybus_M_AXI_awcache(xillybus_M_AXI_AWCACHE),
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.xillybus_M_AXI_awlen(xillybus_M_AXI_AWLEN),
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.xillybus_M_AXI_awprot(xillybus_M_AXI_AWPROT),
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.xillybus_M_AXI_awready(xillybus_M_AXI_AWREADY),
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.xillybus_M_AXI_awsize(xillybus_M_AXI_AWSIZE),
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.xillybus_M_AXI_awvalid(xillybus_M_AXI_AWVALID),
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.xillybus_M_AXI_bready(xillybus_M_AXI_BREADY),
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.xillybus_M_AXI_bresp(xillybus_M_AXI_BRESP),
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.xillybus_M_AXI_bvalid(xillybus_M_AXI_BVALID),
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.xillybus_M_AXI_rdata(xillybus_M_AXI_RDATA),
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.xillybus_M_AXI_rlast(xillybus_M_AXI_RLAST),
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.xillybus_M_AXI_rready(xillybus_M_AXI_RREADY),
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.xillybus_M_AXI_rresp(xillybus_M_AXI_RRESP),
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.xillybus_M_AXI_rvalid(xillybus_M_AXI_RVALID),
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.xillybus_M_AXI_wdata(xillybus_M_AXI_WDATA),
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.xillybus_M_AXI_wlast(xillybus_M_AXI_WLAST),
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.xillybus_M_AXI_wready(xillybus_M_AXI_WREADY),
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.xillybus_M_AXI_wstrb(xillybus_M_AXI_WSTRB),
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.xillybus_M_AXI_wvalid(xillybus_M_AXI_WVALID),
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.xillybus_S_AXI_araddr(xillybus_S_AXI_ARADDR),
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.xillybus_S_AXI_arready(xillybus_S_AXI_ARREADY),
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.xillybus_S_AXI_arvalid(xillybus_S_AXI_ARVALID),
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.xillybus_S_AXI_awaddr(xillybus_S_AXI_AWADDR),
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.xillybus_S_AXI_awready(xillybus_S_AXI_AWREADY),
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.xillybus_S_AXI_awvalid(xillybus_S_AXI_AWVALID),
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.xillybus_S_AXI_bready(xillybus_S_AXI_BREADY),
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.xillybus_S_AXI_bresp(xillybus_S_AXI_BRESP),
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.xillybus_S_AXI_bvalid(xillybus_S_AXI_BVALID),
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.xillybus_S_AXI_rdata(xillybus_S_AXI_RDATA),
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.xillybus_S_AXI_rready(xillybus_S_AXI_RREADY),
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.xillybus_S_AXI_rresp(xillybus_S_AXI_RRESP),
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.xillybus_S_AXI_rvalid(xillybus_S_AXI_RVALID),
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.xillybus_S_AXI_wdata(xillybus_S_AXI_WDATA),
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.xillybus_S_AXI_wready(xillybus_S_AXI_WREADY),
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.xillybus_S_AXI_wstrb(xillybus_S_AXI_WSTRB),
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.xillybus_S_AXI_wvalid(xillybus_S_AXI_WVALID),
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.xillybus_bus_clk(xillybus_bus_clk),
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.xillybus_bus_rst_n(xillybus_bus_rst_n),
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.xillybus_host_interrupt(xillybus_host_interrupt));
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endmodule
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