56 lines
1.5 KiB
VHDL
56 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Scaler
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-- This entity scales the 'data_in' input by the factor 'factor'.
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entity scaler is
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generic (
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DATA_WIDTH : integer := 12;
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FACTOR_WIDTH : integer := 4;
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PIPELINE_STAGES : integer := 1
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);
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port (
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clk : in std_logic;
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data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
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factor : in std_logic_vector(FACTOR_WIDTH-1 downto 0);
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data_out : out std_logic_vector(DATA_WIDTH+FACTOR_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of scaler is
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--*****COMPONENT DECLARATION*****
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component mult is
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generic (
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A_WIDTH : integer := 12;
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B_WIDTH : integer := 4;
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PIPELINE_STAGES : integer := 1;
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UNSIGNED : boolean := true
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);
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port (
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clk : in std_logic;
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A : in std_logic_vector(A_WIDTH-1 downto 0);
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B : in std_logic_vector(B_WIDTH-1 downto 0);
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P : out std_logic_vector(A_WIDTH+B_WIDTH-1 downto 0)
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);
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end component;
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begin
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mult_inst : mult
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generic map(
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A_WIDTH => DATA_WIDTH,
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B_WIDTH => FACTOR_WIDTH,
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PIPELINE_STAGES => PIPELINE_STAGES,
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UNSIGNED => true
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)
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port map(
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clk => clk,
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A => data_in,
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B => factor,
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P => data_out
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);
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end architecture; |