greek64/labor-mst
1
0
Fork 0
Code Issues Releases Activity
Labor Microsystemtechnik
9 Commits 2 Branches 3 Tags 1.2 GiB
VHDL 58.6%
Verilog 23.4%
Tcl 6.4%
Coq 5.7%
Stata 2.8%
Other 3.1%
4fc3cfb9a3
Go to file
Greek 4fc3cfb9a3 * Update docs 
- Download correct 7-series reference
* Add design top entity
* Add synchronizer
* Fix syntax, synth errors
2020-04-26 14:34:34 +02:00
doc * Update docs 2020-04-26 14:34:34 +02:00
modelsim * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
src * Update docs 2020-04-26 14:34:34 +02:00
syn * Update docs 2020-04-26 14:34:34 +02:00
xillinux-syn * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * Update doc 2020-04-26 00:34:08 +02:00