e6b05276d8
Another scaling factor was added and both input signals can now be independenly scaled. In Single Input Mode only Input 1 is passed to the output (negated if configured as negative feddback). In double input mode Input 2 is added/subtracted from Input 1 (in1 +/- in2). The delay line is only applied to Input 2. Addsub was removed from the design (all Additions and Subtractions are directly implemented in VHDL code). Config signals were latched to follow the data flow path and prevent glitches on certain events. Vivado Project updated. Single Package containing all needed pre-calculated sine arrays. General Code Cleanup. |
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| .. | ||
| bootfiles | ||
| cores | ||
| system | ||
| vhdl | ||
| vivado | ||
| vivado-essentials | ||
| .gitignore | ||
| xillydemo-vivado.tcl | ||