greek64/labor-mst
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Labor Microsystemtechnik
17 Commits 2 Branches 3 Tags 1.2 GiB
VHDL 58.6%
Verilog 23.4%
Tcl 6.4%
Coq 5.7%
Stata 2.8%
Other 3.1%
89182e8060
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Greek 89182e8060 * Route sclk for ADC/DAC through controller entity itself 
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
	- Invert SCLK
2020-04-29 14:01:01 +02:00
doc * Add documentation 2020-04-27 13:41:10 +02:00
modelsim * Modify PMOD-AS1 testbench 2020-04-29 13:28:41 +02:00
src * Route sclk for ADC/DAC through controller entity itself 2020-04-29 14:01:01 +02:00
sw * Fix xillybus-FPGA data ordering 2020-04-28 15:12:31 +02:00
syn * Update docs 2020-04-26 14:34:34 +02:00
xillinux-syn * Route sclk for ADC/DAC through controller entity itself 2020-04-29 14:01:01 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * Update doc 2020-04-26 00:34:08 +02:00
mapping.txt * Fix xillybus-FPGA data ordering 2020-04-28 15:12:31 +02:00