97 lines
3.2 KiB
VHDL
97 lines
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Variable Size Delay Line
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-- This entity is based on a single port RAM from which every clock cycle the old contents of an address
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-- are read out and updated with new contents. By incrementing the addresses in a pre-defined loop we
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-- have effectively a ring buffer that we can vary in size (up to the maximum capacity of the memory).
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-- NOTE: Changing the 'delay' value may lead to glitches during the first "delay period", due to the
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-- way the address generation is made. More specifically, these glitches happen when the 'delay' is
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-- increased (which is unavoidable), and when it is decreased while the momentarily counter value is
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-- the same as the new delay value [single cycle glitch].
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entity delay_line is
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generic (
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DATA_WIDTH : integer := 12;
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MAX_DELAY : integer := 200;
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DELAY_WIDTH : integer := 8
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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delay : in std_logic_vector(DELAY_WIDTH-1 downto 0);
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data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
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data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of delay_line is
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--*****COMPONENT DECLARATION*****
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component single_port_ram is
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generic (
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ADDR_WIDTH : integer := 8;
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DATA_WIDTH : integer := 12
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);
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port (
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clk : in std_logic;
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addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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wen : in std_logic;
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ren : in std_logic;
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wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
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rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end component;
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--*****SIGNAl DECLARATION*****
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signal cnt, cnt_next : integer range 0 to MAX_DELAY := 0;
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signal memory_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
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begin
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--*****COMPONENT INSTANTIATION*****
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ram_inst : single_port_ram
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generic map (
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ADDR_WIDTH => DELAY_WIDTH,
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DATA_WIDTH => DATA_WIDTH
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)
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port map(
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clk => clk,
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addr => std_logic_vector(to_unsigned(cnt,DELAY_WIDTH)),
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wen => '1',
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ren => '1',
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wr_data => data_in,
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rd_data => memory_out
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);
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ctrl : process(all)
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begin
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-- DEFAULT VALUES
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cnt_next <= cnt;
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if(to_integer(unsigned(delay)) = 0) then
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data_out <= data_in;
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else
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data_out <= memory_out;
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-- COUNT GENERATION
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if (cnt >= (to_integer(unsigned(delay)) - 1)) then
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cnt_next <= 0;
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else
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cnt_next <= cnt + 1;
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end if;
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end if;
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end process;
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sync : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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cnt <= 0;
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else
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cnt <= cnt_next;
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end if;
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end if;
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end process;
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end architecture; |