139 lines
5.8 KiB
Tcl
139 lines
5.8 KiB
Tcl
# Xillydemo project generation script for Vivado 2014.4 and up
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set origin_dir [file dirname [info script]]
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if {[string first { } $origin_dir] >= 0} {
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send_msg_id xillydemo-1 error "The path to the the project directory contains white space(s): \"$origin_dir\". This is known to cause problems with Vivado. Please move the project to a path without white spaces, and try again."
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}
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set proj_name xillydemo
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set proj_dir "[file normalize $origin_dir/vivado]"
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set thepart "xc7z020clg484-1"
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# Set the directory for essentials for Vivado
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set essentials_dir "[file normalize "$origin_dir/vivado-essentials"]"
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# Create project
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create_project $proj_name "$proj_dir/"
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# Set project properties
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set obj [get_projects $proj_name]
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "part" $thepart $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "source_mgmt_mode" "DisplayOnly" $obj
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set_property target_language VHDL $obj
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set_property "ip_repo_paths" "$essentials_dir/vivado-ip" [current_fileset]
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update_ip_catalog
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set_property "edif_extra_search_paths" "[file normalize "$origin_dir/cores"]" $obj
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set_property "top" "xillydemo" $obj
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# Add files to 'sources_1' fileset
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set obj [get_filesets sources_1]
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set files [list \
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$origin_dir/vhdl/src/xillydemo.vhd \
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$origin_dir/vhdl/src/smbus.v \
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$origin_dir/vhdl/src/i2s_audio.v \
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$origin_dir/vhdl/src/xillybus.v \
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$origin_dir/vhdl/src/xillybus_core.v \
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$essentials_dir/system.v \
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$essentials_dir/vga_fifo/vga_fifo.xci \
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$essentials_dir/fifo_8x2048/fifo_8x2048.xci \
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$essentials_dir/fifo_32x512/fifo_32x512.xci \
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$essentials_dir/vivado_system/vivado_system.bd \
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]
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add_files -norecurse -fileset $obj $files
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upgrade_ip [get_ips]
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# A bug in Vivado drops one slave interface on the AXI4-Lite to AXI3
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# crossbar when vivado_system.bd is loaded. So AXI4-Lite slaves are
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# connected with the Tcl commands below.
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open_bd_design $essentials_dir/vivado_system/vivado_system.bd
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startgroup
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apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_ip_0/S_AXI]
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apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillyvga_0/S_AXI]
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apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_lite_0/S_AXI]
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set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
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set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
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set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
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set_property offset 0x50000000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
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set_property offset 0x50001000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
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set_property offset 0x50002000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
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endgroup
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save_bd_design
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close_bd_design vivado_system
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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# Add files to 'constrs_1' fileset
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set obj [get_filesets constrs_1]
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add_files -fileset $obj -norecurse $essentials_dir/xillydemo.xdc
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# Set 'constrs_1' fileset properties
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set obj [get_filesets constrs_1]
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# Create 'sim_1' fileset (if not found)
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if {[string equal [get_filesets sim_1] ""]} {
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create_fileset -simset sim_1
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}
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# Add files to 'sim_1' fileset
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set obj [get_filesets sim_1]
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# Empty (no sources present)
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# Set 'sim_1' fileset properties
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set obj [get_filesets sim_1]
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set_property "top" "unknown" $obj
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set_property "xsim.simulate.runtime" "1000 ns" $obj
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set_property "xsim.simulate.uut" "UUT" $obj
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# Create 'synth_1' run (if not found)
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if {[string equal [get_runs synth_1] ""]} {
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create_run -name synth_1 -part $thepart -flow {Vivado Synthesis 2013} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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}
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set obj [get_runs synth_1]
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set_property "part" $thepart $obj
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# Create 'impl_1' run (if not found)
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if {[string equal [get_runs impl_1] ""]} {
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create_run -name impl_1 -part $thepart -flow {Vivado Implementation 2013} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
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}
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set obj [get_runs impl_1]
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set_property "part" $thepart $obj
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set_property STEPS.ROUTE_DESIGN.TCL.POST "$essentials_dir/showstopper.tcl" $obj
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# Calm down critical warnings for issues that are known to be OK
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set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_S_AXI} }
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set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_M_AXI} }
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set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_M_AXI} }
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set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_S_AXI} }
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set_msg_config -new_severity "INFO" -id {BD 41-678} -string {{xillybus_S_AXI/Reg} }
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set_msg_config -new_severity "INFO" -id {BD 41-1356} -string {{xillybus_S_AXI/Reg} }
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set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
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set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
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set_msg_config -new_severity "INFO" -id {filemgmt 20-1440} -string {{xillybus_lite.ngc} }
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# The processor's native pads are detached in the logic design to prevent
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# Vivado from confusing itself. This causes a lot of critical warnings about
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# meaningless contraints not being applied. So drop the warnings.
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set_msg_config -new_severity "INFO" -id {Netlist 29-160} -string {{vivado_system_processing_system7} }
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puts "INFO: Project created: $proj_name"
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# Uncomment the two following lines for a full implementation
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#launch_runs -jobs 8 impl_1 -to_step write_bitstream
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#wait_on_run impl_1
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