|
clockgen.vhd
|
* Added clock generator for 20Mhz sclk
|
2020-04-01 14:14:14 +02:00 |
|
open_loop_tb.vhd
|
* Added Zynq 7 documentation
|
2020-04-01 14:12:04 +02:00 |
|
open_loop.vhd
|
* Added Zynq 7 documentation
|
2020-04-01 14:12:04 +02:00 |
|
pmod_ad1_ctrl_tb.vhd
|
* .gitignore update
|
2020-03-12 20:20:35 +01:00 |
|
pmod_ad1_ctrl.vhd
|
* Added Zynq 7 documentation
|
2020-04-01 14:12:04 +02:00 |
|
pmod_da3_ctrl_tb.vhd
|
* .gitignore update
|
2020-03-12 20:20:35 +01:00 |
|
pmod_da3_ctrl.vhd
|
* Added Zynq 7 documentation
|
2020-04-01 14:12:04 +02:00 |
|
top.vhd
|
* Added clock generator for 20Mhz sclk
|
2020-04-01 14:14:14 +02:00 |
|
top.xdc
|
* Added clock generator for 20Mhz sclk
|
2020-04-01 14:14:14 +02:00 |
