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labor-mst/xillinux-syn
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Greek 89182e8060 * Route sclk for ADC/DAC through controller entity itself 
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
	- Invert SCLK
2020-04-29 14:01:01 +02:00
..
bootfiles * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
cores * Modify xillinux vivado project 2020-04-26 17:36:25 +02:00
system * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
vhdl * Add documentation 2020-04-27 13:41:10 +02:00
vivado * Add documentation 2020-04-27 13:41:10 +02:00
vivado-essentials * Route sclk for ADC/DAC through controller entity itself 2020-04-29 14:01:01 +02:00
.gitignore * Added Xillybus demo project 2020-04-26 11:42:06 +02:00
xillydemo-vivado.tcl * Added Xillybus demo project 2020-04-26 11:42:06 +02:00