greek64/labor-mst
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Labor Microsystemtechnik
4 Commits 2 Branches 3 Tags 1.2 GiB
VHDL 58.6%
Verilog 23.4%
Tcl 6.4%
Coq 5.7%
Stata 2.8%
Other 3.1%
open_loop-v1
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Greek e1ffa99874 * Added clock generator for 20Mhz sclk 
* Added top entiry
* Added constraints file
2020-04-01 14:14:14 +02:00
doc * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
modelsim * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
src * Added clock generator for 20Mhz sclk 2020-04-01 14:14:14 +02:00
syn * Added clock generator for 20Mhz sclk 2020-04-01 14:14:14 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * .gitignore update 2020-03-12 20:20:35 +01:00