-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;

entity rtps_reader is
    generic (
        -- HACK: FIXME: Quartus Workaround
        --  Quartus does not allow to reference a generic insisde the generic block.
        --  So we constrain the range later as constant
        NUM_READERS             : natural;
        CONFIG_ARRAY            : QUARTUS_CONFIG_ARRAY_TYPE;
            -- RELIABILITY_QOS
            -- LIVELINESS_QOS
            -- DURABILITY_QOS
            -- HEARTBEAT_RESPONSE_DELAY
            -- HEARTBEAT_SUPPRESSION_DELAY
            -- LEASE_DURATION
            -- WITH_KEY
            -- MAX_PAYLOAD_SIZE
        ENTITYID                : ENTITYID_ARRAY_TYPE;
        MAX_REMOTE_ENDPOINTS    : natural := 50
    );
    port (
        -- SYSTEM
        clk                 : in std_logic;
        reset               : in std_logic;
        time                : in TIME_TYPE;
        -- FROM RTPS HANDLER (USER TRAFFIC)
        empty_user          : in std_logic_vector(0 to NUM_READERS-1);
        rd_user             : out std_logic;
        data_in_user        : in std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_in_user   : in std_logic;
        -- FROM DISCOVERY MODULE (META TRAFFIC)
        empty_meta          : in std_logic_vector(0 to NUM_READERS-1);
        rd_meta             : out std_logic;
        data_in_meta        : in std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_in_meta   : in std_logic;
        -- RTPS OUTPUT
        full_ro             : in std_logic;
        wr_ro               : out std_logic;
        data_out_ro         : out std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_out_ro    : out std_logic;
        -- TO HISTORY CACHE
        start_hc            : out std_logic_vector(0 to NUM_READERS-1);
        opcode_hc           : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1);
        ack_hc              : in std_logic_vector(0 to NUM_READERS-1);
        done_hc             : in std_logic_vector(0 to NUM_READERS-1);
        ret_hc              : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1);
        valid_out_hc        : out std_logic_vector(0 to NUM_READERS-1);
        ready_out_hc        : in std_logic_vector(0 to NUM_READERS-1);
        data_out_hc         : out WORD_ARRAY_TYPE(0 to NUM_READERS-1);
        last_word_out_hc    : out std_logic_vector(0 to NUM_READERS-1)
    );
end entity;

architecture arch of rtps_reader is
    
    constant CONFIG_ARRAY_T : QUARTUS_CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := CONFIG_ARRAY;
    constant ENTITYID_T     : ENTITYID_ARRAY_TYPE(0 to NUM_READERS-1) := ENTITYID;
    
    --*****CONSTANT DECLARATION*****
    -- *ENDPOINT MEMORY*
    -- 4-Byte Word Size of a Remote Endpoint Entry in Memory
    constant ENDPOINT_FRAME_SIZE            : natural := 17;
    -- Endpoint Memory Size in 4-Byte Words
    constant ENDPOINT_MEMORY_SIZE           : natural := MAX_REMOTE_ENDPOINTS * ENDPOINT_FRAME_SIZE;
    -- Endpoint Memory Address Width
    constant ENDPOINT_MEMORY_ADDR_WIDTH     : natural := log2c(ENDPOINT_MEMORY_SIZE);
    -- Highest Endpoint Memory Address
    constant ENDPOINT_MEMORY_MAX_ADDRESS    : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(ENDPOINT_MEMORY_SIZE-1, ENDPOINT_MEMORY_ADDR_WIDTH);
    -- Highest Endpoint Frame Address
    constant MAX_ENDPOINT_ADDRESS           : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := ENDPOINT_MEMORY_MAX_ADDRESS - ENDPOINT_FRAME_SIZE + 1;
    -- Address pointing to the beginning of the first Endpoint Data Frame
    constant FIRST_ENDPOINT_ADDRESS         : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
    -- *PAYLOAD MEMORY*
    function gen_payload_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE) return natural is
        variable ret : natural := 0;
    begin
        assert (qos'length = NUM_READERS) severity FAILURE;
        
        for i in 0 to NUM_READERS-1 loop
            if (qos(i).MAX_PAYLOAD_SIZE > ret) then
                ret := qos(i).MAX_PAYLOAD_SIZE;
            end if;
        end loop;
        
        return round_div(ret, WORD_WIDTH/BYTE_WIDTH);
    end function;
    -- Payload Memory Size in 4-Byte Words
    constant PAYLOAD_MEMORY_SIZE            : natural := gen_payload_memory_size(CONFIG_ARRAY_T);
    -- Payload Memory Address Width
    constant PAYLOAD_MEMORY_ADDR_WIDTH      : natural := log2c(PAYLOAD_MEMORY_SIZE);
    -- Highest Payload Memory Address
    constant MAX_PAYLOAD_ADDRESS            : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(PAYLOAD_MEMORY_SIZE-1, PAYLOAD_MEMORY_ADDR_WIDTH);
    
    -- *ENDPOINT MEMORY FRAME FIELD FLAGS*
    -- Flags mapping to the respective Endpoint Memory Frame Fields
    constant EMF_FLAG_WIDTH             : natural := 9;
    constant EMF_ENTITYID_FLAG          : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (0 => '1', others => '0');
    constant EMF_GUIDPREFIX_FLAG        : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (1 => '1', others => '0');
    constant EMF_IPV4_ADDR_FLAG         : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (2 => '1', others => '0');
    constant EMF_UDP_PORT_FLAG          : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (3 => '1', others => '0');
    constant EMF_NEXT_SEQ_NR_FLAG       : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (4 => '1', others => '0');
    constant EMF_LEASE_DEADLINE_FLAG    : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (5 => '1', others => '0');
    constant EMF_LIFESPAN_DURATION_FLAG : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (6 => '1', others => '0');
    constant EMF_RES_TIME_FLAG          : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (7 => '1', others => '0');
    constant EMF_WRITER_ID_FLAG         : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (8 => '1', others => '0');
    
    -- *ENDPOINT MEMORY FRAME FIELD OFFSETS*
    -- 4-Byte Word Offsets to Beginning of Respective Fields in the Endpoint Memory Frame
    constant EMF_ENTITYID_OFFSET            : natural := 0;
    constant EMF_GUIDPREFIX_OFFSET          : natural := 1;
    constant EMF_IPV4_ADDR_OFFSET           : natural := 4;
    constant EMF_UDP_PORT_OFFSET            : natural := 5;
    constant EMF_NEXT_SEQ_NR_OFFSET         : natural := 6;
    constant EMF_LEASE_DEADLINE_OFFSET      : natural := 8;
    constant EMF_LIFESPAN_DURATION_OFFSET   : natural := 10;
    constant EMF_RES_TIME_OFFSET            : natural := 12;
    constant EMF_WRITER_ID_OFFSET           : natural := 14;
    constant EMF_NEXT_ADDR_OFFSET           : natural := 15;
    constant EMF_PREV_ADDR_OFFSET           : natural := 16;
    
    
    --*****TYPE DECLARATION*****
    type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural;
    type ENDPOINT_ADDRESS_ARRAY_TYPE is array(0 to NUM_READERS-1) of unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
    type ACKNACK_COUNT_ARRAY is array (0 to NUM_READERS-1) of unsigned(COUNT_WIDTH-1 downto 0);
    -- FSM states. Explained below in detail
    type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION, LATCH_SRC_ADDR, 
        LATCH_EXTRA_DATA, LATCH_HEARTBEAT, PROCESS_HEARTBEAT, LATCH_GAP, PROCESS_GAP, FIND_NEXT_VALID_IN_BITMAP, PROCESS_INLINE_QOS, 
        LATCH_KEY_HASH, LATCH_STATUS_INFO, INITIATE_ADD_CACHE_CHANGE_REQUEST, ADD_CACHE_CHANGE, PUSH_PAYLOAD, FINALIZE_ADD_CACHE_CHANGE_REQUEST, 
        ENDPOINT_STALE_CHECK, SEND_HEADER, SEND_ACKNACK, SKIP_PARAMETER, SKIP_PACKET, SKIP_META_OPERATION, LATCH_PAYLOAD);
    -- Memory FSM states. Explained below in detail
    type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, RESET_MEMORY);
    -- *Memory FSM Opcodes*
    --  OPCODE              DESCRIPTION
    --  SEARCH_ENDPOINT     Search memory for Endpoint with GUID equal to "mem_r.guid" signal.
    --                      Set "mem_endpoint_data.addr" to base Address of found Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if nothing found.
    --                      "mem_endpoint_data" contains Endpoint Data according to "mem_r.field_flags".
    --  INSERT_ENDPOINT     Insert Endpoint in memory
    --  UPDATE_ENDPOINT     Update Endpoint pointed by "mem_r.addr" according to "mem_r.field_flags".
    --  REMOVE_ENDPOINT     Remove Endpoint pointed by "mem_r.addr".
    --                      "mem_endpoint_data.addr" is set to the next Endpoint (or ENDPOINT_MEMORY_MAX_ADDRESS if no next Endpoint exists)
    --  GET_NEXT_ENDPOINT   Get Endpoint Data of next Endpoint (from the Endpoint pointed by "mem_r.addr") according to "mem_r.field_flags".
    --                      Set "mem_endpoint_data.addr" to Address of Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if no other Endpoint in Memory.
    --  GET_ENDPOINT        Get Endpoint Data from Endpoint pointed by "mem_r.addr" according to "mem_r.field_flags".
    --                      Already fetched data of the same Endpoint is not modified.
    type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, GET_ENDPOINT);
    -- Record of Endpoint Data
    type ENDPOINT_DATA_TYPE is record
        i               : natural range 0 to NUM_READERS-1;    
        addr            : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
        guid            : GUID_TYPE;
        ip_addr         : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
        portn           : std_logic_vector(UDP_PORT_WIDTH-1 downto 0);
        next_seq_nr     : SEQUENCENUMBER_TYPE;
        lease_deadline  : TIME_TYPE;
        lifespan        : DURATION_TYPE;
        res_time        : TIME_TYPE;
        writer_id       : natural;
        field_flags     : std_logic_vector(0 to EMF_FLAG_WIDTH-1);
    end record;
    -- Zero initialized Endpoint Data
    constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := (
        i               => 0,
        addr            => ENDPOINT_MEMORY_MAX_ADDRESS,
        guid            => GUID_UNKNOWN,
        ip_addr         => IPv4_ADDRESS_INVALID,
        portn           => UDP_PORT_INVALID,
        next_seq_nr     => SEQUENCENUMBER_UNKNOWN,
        lease_deadline  => TIME_INVALID,
        lifespan        => DURATION_INFINITE,
        res_time        => TIME_INVALID,
        writer_id       => 0,
        field_flags     => (others => '0')
    );
    
    
    --*****SIGNAL DECLARATION*****
    -- *MAIN PROCESS*
    -- FSM state
    signal stage, stage_next : STAGE_TYPE;
    -- FSM state latch. Used to transition dynamically to different states from the same state.
    signal return_stage, return_stage_next : STAGE_TYPE;
    -- Intermediate input read signal. (Read from output port not allowed)
    signal rd_sig : std_logic;
    -- Signal used to reset the word counter
    signal reset_read_cnt : std_logic;
    -- Word (4-Byte) counter (Counts words read from input fifo)
    signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0);
    -- Word aligned End of Parameter
    signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0);
    -- General Purpose Counter
    signal cnt, cnt_next : natural range 0 to 9;
    -- Packet Opcode Latch (RTPS Message ID)
    signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0);
    -- Metatraffic Opcode Latch
    signal meta_opcode, meta_opcode_next : std_logic_vector(EMO_WIDTH-1 downto 0);
    -- Signifies if the received packet is a metatraffic operation
    signal is_meta, is_meta_next : std_logic;
    -- Source GUID Latch
    signal guid, guid_next : GUID_TYPE;
    -- Source IPv4 Address Latch
    signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
    -- UDP Port Latch
    signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0);
    -- RTPS Header Flags Latch
    signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0);
    -- Source Timestamp Latch
    signal ts, ts_next : TIME_TYPE;
    -- Key Hash Latch
    signal key_hash, key_hash_next  : KEY_HASH_TYPE;
    -- Signifies if a Key Hash was received
    signal key_hash_rcvd, key_hash_rcvd_next : std_logic;
    -- Status Info Latch
    signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0);
    -- Lifespan Latch (Contains Lifespan Duration during meta parsing, and Lifespan Deadline during user parsing)
    signal lifespan, lifespan_next : TIME_TYPE;
    -- RTPS Sequence Number Latch
    signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE;
    -- Signifies the next expected Sequence Number
    signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE;
    -- Generic Sequence Number Latch
    signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE;
    -- Generic Sequence Number Latch
    signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE;
    -- Generic Sequence Number Latch
    signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE;
    -- Toggle latching the "last_word_in_user" signal until reset
    signal last_word_in_latch, last_word_in_latch_next : std_logic;
    -- Time of next Stale Endpoint Check
    signal check_time, check_time_next : TIME_TYPE;
    -- Signifies if a Stale Endpoint Check is in progress
    signal stale_check, stale_check_next : std_logic;
    -- Signal containing the RTPS ACKNACK Count Field
    signal count, count_next : ACKNACK_COUNT_ARRAY;
    -- Data in represented in Big Endian
    signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0);
    -- Denotes the number of valid Bitmap longs (4-Byte words)
    signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0);
    -- NumberSet Bitmap Latch
    signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE;
    -- Counter used to read out Bitmaps
    signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length;
    -- Signal used to iterate through Bitmaps
    signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1;
    -- Signals the start of a Memory Operation
    signal mem_op_start : std_logic;
    -- Opcode of the Memory Operation (Valid only when mem_op_start is high)
    signal mem_opcode : MEM_OPCODE_TYPE;
    -- Signals the end of a Memory Operation
    signal mem_op_done : std_logic;
    -- Signal used to pass data to memory process
    signal mem_r : ENDPOINT_DATA_TYPE;
    -- Bitmap used to index the readers
    signal r_map, r_map_next : std_logic_vector(0 to NUM_READERS-1);
    -- Signal used to index the readers
    signal ind, ind_next : natural range 0 to NUM_READERS-1;
    -- Pointer to current Payload Memory Address
    signal payload_addr_base, payload_addr_base_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0);
    -- Last valid Address of current Payload
    signal payload_max_addr, payload_max_addr_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0);
    -- Test signal used for testbench synchronisation
    signal idle_sig : std_logic;
    -- Test signal used in testbenches for removal check
    signal empty_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE;
    
    -- *MEMORY PROCESS*
    -- Memory FSM state
    signal mem_stage, mem_stage_next : MEM_STAGE_TYPE;
    -- Head of Occupied Memory Endpoint List
    signal mem_occupied_head, mem_occupied_head_next : ENDPOINT_ADDRESS_ARRAY_TYPE;
    -- Head of Empty Memory Endpoint List
    signal mem_empty_head, mem_empty_head_next : ENDPOINT_ADDRESS_ARRAY_TYPE;
    -- Pointer to current relevant Endpoint Address
    signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
    -- General Memory Address Latch
    signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
    -- General Purpose Couter
    signal mem_cnt, mem_cnt_next : natural range 0 to 29;
    -- Latch for Endpoint Data from Memory
    signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE;
    -- Latch for Endpoint Data from main process
    signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_DATA_TYPE;
    -- Signal used to write to ALL memories simutanously
    signal multi_w : std_logic;
    
    -- *ENDPOINT MEMORY CONNECTION SIGNALS*
    signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
    signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0);
    signal mem_ready_in, mem_valid_in : std_logic;
    signal mem_ready_out, mem_valid_out : std_logic;
    signal mem_read : std_logic;
    signal abort_read : std_logic;
    signal mem_addr_i : ENDPOINT_ADDRESS_ARRAY_TYPE;
    signal mem_read_data_i, mem_write_data_i : WORD_ARRAY_TYPE(0 to NUM_READERS-1);
    signal mem_ready_in_i, mem_valid_in_i : std_logic_vector(0 to NUM_READERS-1);
    signal mem_ready_out_i, mem_valid_out_i : std_logic_vector(0 to NUM_READERS-1);
    signal mem_read_i : std_logic_vector(0 to NUM_READERS-1);
    signal abort_read_i : std_logic_vector(0 to NUM_READERS-1);
    
    -- *PAYLOAD MEMORY CONNECTION SIGNALS*
    signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0);
    signal payload_read : std_logic;
    signal payload_read_data, payload_write_data : std_logic_vector(WORD_WIDTH-1 downto 0);
    signal payload_ready_in, payload_valid_in : std_logic;
    signal payload_ready_out, payload_valid_out : std_logic;
    signal payload_abort_read : std_logic;
    
    --*****ALIAS DECLARATION*****
    -- ENDPOINT FRAME HEADER
    alias header_opcode             : std_logic_vector(7 downto 0) is data_in_user(31 downto 24);
    alias header_flags              : std_logic_vector(7 downto 0) is data_in_user(23 downto 16);
    alias header_udp_port           : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
    -- RTPS PARAMETER LIST HEADER
    alias parameter_id              : std_logic_vector(15 downto 0) is data_in_user(31 downto 16);
    alias parameter_length          : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
    -- RTPS DATA PAYLOAD HEADER
    alias representation_id         : std_logic_vector(15 downto 0) is data_in_user(31 downto 16);
    alias representation_options    : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
    -- RTPS SUBMESSAGE FLAGS
    alias endian_flag               : std_logic is flags(0);
    alias qos_flag                  : std_logic is flags(1);
    alias data_flag                 : std_logic is flags(2);
    alias key_flag                  : std_logic is flags(3);
    alias final_flag                : std_logic is flags(1);
    alias non_std_flag              : std_logic is flags(4);
    alias liveliness_flag           : std_logic is flags(2);
    -- HEARTBEAT
    alias first_seq_nr              : SEQUENCENUMBER_TYPE is sn_latch_1;
    alias first_seq_nr_next         : SEQUENCENUMBER_TYPE is sn_latch_1_next;
    alias last_seq_nr               : SEQUENCENUMBER_TYPE is sn_latch_2;
    alias last_seq_nr_next          : SEQUENCENUMBER_TYPE is sn_latch_2_next;
    -- GAP
    alias gap_start                 : SEQUENCENUMBER_TYPE is sn_latch_1;
    alias gap_start_next            : SEQUENCENUMBER_TYPE is sn_latch_1_next;
    alias gap_list_base             : SEQUENCENUMBER_TYPE is sn_latch_2;
    alias gap_list_base_next        : SEQUENCENUMBER_TYPE is sn_latch_2_next;
    alias gap_list_end              : SEQUENCENUMBER_TYPE is sn_latch_3;
    alias gap_list_end_next         : SEQUENCENUMBER_TYPE is sn_latch_3_next;
    
    --*****FUNCTION DECLARATION*****
    -- Helper function to convert BITMAP_TYPE to std_logic_vector
    function to_slv_bitmap (input : BITMAP_TYPE) return std_logic_vector is
        variable ret : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0');
    begin
        for i in 0 to BITMAP_TYPE'length-1 loop
            ret(i*WORD_WIDTH to ((i+1)*WORD_WIDTH)-1) := input(i);
        end loop;
        return ret;
    end function;
    
    -- HACK: Due to delta cycle race condition some assertions trigger false positives,
    --       so we check the signals on the falling edge
    function stable(clk : std_logic; a : boolean) return boolean is
    begin
        if (clk = '0') then
            return a;
        else
            return TRUE;
        end if;
    end function;
    
    -- HACK: Quartus Workaround (Does not support unary and [VHDL 2008])
    function and_reduce(input : std_logic_vector) return std_logic is
        variable ret : std_logic := '1';
    begin
        for i in 0 to input'length-1 loop
            ret := ret and input(i);
        end loop;
        return ret;
    end function;
    
begin
    
    payload_mem_inst : entity work.mem_ctrl(arch)
        generic map (
            ADDR_WIDTH          => PAYLOAD_MEMORY_ADDR_WIDTH,
            DATA_WIDTH          => WORD_WIDTH,
            MEMORY_DEPTH        => PAYLOAD_MEMORY_SIZE,
            MAX_BURST_LENGTH    => 1
        )
        port map (
            clk         => clk,
            reset       => reset or payload_abort_read,
            addr        => std_logic_vector(payload_addr),
            read        => payload_read,
            ready_in    => payload_ready_in,
            valid_in    => payload_valid_in,
            data_in     => payload_write_data,
            ready_out   => payload_ready_out,
            valid_out   => payload_valid_out,
            data_out    => payload_read_data
        );
    
    mem_ctrl_gen : for i in 0 to NUM_READERS-1 generate
        mem_ctrl_inst : entity work.mem_ctrl(arch)
            generic map (
                ADDR_WIDTH          => ENDPOINT_MEMORY_ADDR_WIDTH,
                DATA_WIDTH          => WORD_WIDTH,
                MEMORY_DEPTH        => ENDPOINT_MEMORY_SIZE,
                MAX_BURST_LENGTH    => ENDPOINT_FRAME_SIZE
            )
            port map (
                clk         => clk,
                reset       => reset or abort_read_i(i),
                addr        => std_logic_vector(mem_addr_i(i)),
                read        => mem_read_i(i),
                ready_in    => mem_ready_in_i(i),
                valid_in    => mem_valid_in_i(i),
                data_in     => mem_write_data_i(i),
                ready_out   => mem_ready_out_i(i),
                valid_out   => mem_valid_out_i(i),
                data_out    => mem_read_data_i(i)
            );
    end generate;
    
    memory_mux : process (all)
    begin
        abort_read_i        <= (others => '0');
        mem_addr_i          <= (others => (others => '0'));
        mem_read_i          <= (others => '0');
        mem_valid_in_i      <= (others => '0');
        mem_write_data_i    <= (others => (others => '0'));
        mem_ready_out_i     <= (others => '0');
        if (multi_w = '0')  then
            abort_read_i(mem_endpoint_latch_data.i)     <= abort_read;
            mem_addr_i(mem_endpoint_latch_data.i)       <= mem_addr;
            mem_read_i(mem_endpoint_latch_data.i)       <= mem_read;
            mem_valid_in_i(mem_endpoint_latch_data.i)   <= mem_valid_in;
            mem_write_data_i(mem_endpoint_latch_data.i) <= mem_write_data;
            mem_ready_out_i(mem_endpoint_latch_data.i)  <= mem_ready_out;
            
            mem_ready_in    <= mem_ready_in_i(mem_endpoint_latch_data.i);
            mem_valid_out   <= mem_valid_out_i(mem_endpoint_latch_data.i);
            mem_read_data   <= mem_read_data_i(mem_endpoint_latch_data.i);
        else
            abort_read_i        <= (others => abort_read);
            mem_addr_i          <= (others => mem_addr);
            mem_read_i          <= (others => mem_read);
            mem_valid_in_i      <= (others => mem_valid_in);
            mem_write_data_i    <= (others => mem_write_data);
            mem_ready_out_i     <= (others => mem_ready_out);
            
            mem_ready_in    <= and_reduce(mem_ready_in_i); --and mem_ready_in_i;
            mem_valid_out   <= '0';
            mem_read_data   <= (others => '0');
        end if;
    end process;
    
    -- Big Endian Representation
    data_in_swapped <= endian_swap(endian_flag, data_in_user);
    rd_user <= rd_sig;
    
    -- *Main State Machine*
    -- STATE                                DESCRIPTION
    -- IDLE                                 Idle State. Initiates Stale Endpoint Checks, Metatraffic Packet Processing, and User Packet Processing, in that priority order.
    -- LATCH_SRC_ADDR                       Store source IPv4 Address
    -- LATCH_GUIDPREFIX                     Store source GUID Prefix
    -- LATCH_ENTITYID                       Store source Entity ID
    -- LATCH_ENDPOINT_DATA                  Store Remote Endpoint Data
    -- LATCH_EXTRA_DATA                     Store source Timestamp, and source Sequence Number
    -- PROCESS_INLINE_QOS                   Parse in-line Parameter List QoS
    -- LATCH_KEY_HASH                       Store KEY_HASH
    -- LATCH_STATUS_INFO                    Store STATUS_INFO
    -- LATCH_PAYLOAD                        Store payload
    -- LATCH_HEARTBEAT                      Store RTPS HEARTBEAT Sequence Numbers
    -- LATCH_GAP                            Store RTPS GAP Sequence Numbers
    -- INITIATE_ENDPOINT_SEARCH             Initiate Endpoint Search Memory Operation. This state is used to start the Search operation as soon as the required data is available
    -- METATRAFFIC_OPERATION                State handling the Metatraffic Operations
    -- PROCESS_HEARTBEAT                    Parse RTPS HEARTBEAT Message. Update stored Sequence Number if necessary. Set HEARTBEAT response time accordingly.
    -- PROCESS_GAP                          Parse RTPS GAP Submsessage. Initiates search for next valid Sequence Number if currently expected Sequence Number is in GAP
    -- FIND_NEXT_VALID_IN_BITMAP            Iterate through Bitmap and find the next valid Sequence Number.
    -- INITIATE_ADD_CACHE_CHANGE_REQUEST    Initiate an ADD_CACHE_CHANGE Operation
    -- ADD_CACHE_CHANGE                     Send CACHE_CHANGE Data
    -- PUSH_PAYLOAD                         Send CACHE_CHANGE Data (Direct Input Passthrough)
    -- FINALIZE_ADD_CACHE_CHANGE_REQUEST    Wait for ADD_CACHE_CHANGE Operation Results. Update Endpoint Data if successfull.
    -- ENDPOINT_STALE_CHECK                 Check remote Endpoint Entries for Liveliness Lease Expiration, and Response Timeouts.
    -- SEND_HEADER                          Send Output Data Header and RTPS Message Header
    -- SEND_ACKNACK                         Send ACKNACK Submessage
    -- SKIP_PARAMETER                       Skip rest of Parameter
    -- SKIP_PACKET                          Skip rest of Packet
    -- SKIP_META_OPERATION                  Skip Metatraffic Operation
    parse_prc : process(all)
        variable tmp_dw     : DOUBLE_WORD_ARRAY;
        -- NOTE: We convert the bitamp to a slv to make operations easier (The synthesizer should handle both cases equally)
        variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1);
        variable rd_guard   : std_logic;
    begin
        -- DEFAULT Registered
        stage_next                  <= stage;
        meta_opcode_next            <= meta_opcode;
        cnt_next                    <= cnt;
        cnt2_next                   <= cnt2;
        guid_next                   <= guid;
        addr_next                   <= addr;
        portn_next                  <= portn;
        is_meta_next                <= is_meta;
        opcode_next                 <= opcode;
        flags_next                  <= flags;
        seq_nr_next                 <= seq_nr;
        ts_next                     <= ts;
        sn_latch_1_next             <= sn_latch_1;
        sn_latch_2_next             <= sn_latch_2;
        sn_latch_3_next             <= sn_latch_3;
        bitmap_latch_next           <= bitmap_latch;
        bitmap_cnt_next             <= bitmap_cnt;
        bitmap_pos_next             <= bitmap_pos;
        key_hash_rcvd_next          <= key_hash_rcvd;
        key_hash_next               <= key_hash;
        status_info_next            <= status_info;
        last_word_in_latch_next     <= last_word_in_latch;
        stale_check_next            <= stale_check;
        count_next                  <= count;
        return_stage_next           <= return_stage;
        check_time_next             <= check_time;
        lifespan_next               <= lifespan;
        parameter_end_next          <= parameter_end;
        next_seq_nr_next            <= next_seq_nr;
        r_map_next                  <= r_map;
        ind_next                    <= ind;
        payload_addr_base_next      <= payload_addr_base;
        payload_max_addr_next       <= payload_max_addr;
        -- DEFAULT Unregistered
        mem_opcode                  <= NOP;
        opcode_hc                   <= (others => NOP);
        mem_r                       <= ZERO_ENDPOINT_DATA;
        reset_read_cnt              <= '0';
        rd_meta                     <= '0';
        mem_op_start                <= '0';
        start_hc                    <= (others => '0');
        valid_out_hc                <= (others => '0');
        last_word_out_hc            <= (others => '0');
        wr_ro                       <= '0';
        last_word_out_ro            <= '0';
        idle_sig                    <= '0';
        rd_guard                    := '0';
        data_out_hc                 <= (others => (others => '0'));
        data_out_ro                 <= (others => '0');
        payload_addr                <= (others => '0');
        payload_write_data          <= (others => '0');
        payload_read                <= '0';
        payload_valid_in            <= '0';
        payload_ready_out           <= '0';
        payload_abort_read          <= '0';
        
        
        
        -- Last Word Latch Setter
        -- NOTE: Assumes meta and user traffic are not consumed concurrently
        if (last_word_in_user = '1' or last_word_in_meta = '1') then
            last_word_in_latch_next <= '1';
        end if;
        
        case (stage) is
            when IDLE =>
                idle_sig    <= '1';
                -- RESET
                lifespan_next               <= TIME_INVALID;
                addr_next                   <= (others => '0');
                portn_next                  <= (others => '0');
                status_info_next            <= (others => '0');
                key_hash_rcvd_next          <= '0';
                is_meta_next                <= '0';
                
                -- Stale Check Timeout
                if (time >= check_time) then
                    -- Reset Timeout
                    check_time_next     <= TIME_INFINITE;
                    stale_check_next    <= '1';
                    
                    r_map_next  <= (others => '1');
                    ind_next    <= 0;
                    
                    stage_next  <= ENDPOINT_STALE_CHECK;
                    cnt_next    <= 1; -- GET FIRST Endpoint
                -- Input FIFO Guard
                elsif (empty_meta /= (empty_meta'range => '1')) then
                    rd_meta     <= '1';
                    
                    r_map_next  <= not empty_meta;
                    ind_next    <= 0;
                    
                    -- Mark as METATRAFFIC
                    is_meta_next        <= '1';
                    
                    -- Latch Endpoint Metatraffic Opcode
                    meta_opcode_next    <= data_in_meta;
                    
                    case (data_in_meta) is
                        when EMO_ENDPOINT_MATCH =>
                            stage_next  <= LATCH_GUIDPREFIX;
                            cnt_next    <= 0;
                        when EMO_ENDPOINT_UNMATCH =>
                            stage_next  <= LATCH_GUIDPREFIX;
                            cnt_next    <= 0;
                        when EMO_PARTICIPANT_UNMATCH =>
                            stage_next  <= LATCH_GUIDPREFIX;
                            cnt_next    <= 0;
                        when EMO_LIVELINESS_UPDATE =>
                            stage_next  <= LATCH_GUIDPREFIX;
                            cnt_next    <= 0;
                        when others =>
                            assert FALSE report "RTPS Writer received unknown META Operation" severity WARNING;
                            stage_next  <= SKIP_META_OPERATION;
                    end case;
                -- Input FIFO Guard
                elsif (empty_user /= (empty_user'range => '1')) then
                    rd_guard        := '1';
                    
                    r_map_next  <= not empty_user;
                    ind_next    <= 0;
                    
                    -- Latch Opcode
                    opcode_next <= header_opcode;
                    -- Latch Flags
                    flags_next  <= header_flags;
                    -- Latch Source UDP Port
                    portn_next  <= header_udp_port;
                    
                    case (header_opcode) is
                        when SID_DATA =>
                            -- Reset
                            payload_addr_base_next  <= (others => '0');
                            payload_max_addr_next   <= (others => '0');
                            
                            -- SANITY CHECK: Skip Packet if non-standard Payload
                            if(header_flags(SUBMESSAGE_NON_STANDARD_PAYLOAD_FLAG_POS) = '1') then
                                stage_next  <= SKIP_PACKET;
                            else
                                stage_next  <= LATCH_SRC_ADDR;
                            end if;
                        when SID_HEARTBEAT =>
                            stage_next  <= LATCH_SRC_ADDR;
                        when SID_GAP =>
                            stage_next  <= LATCH_SRC_ADDR;
                        when others =>
                            stage_next  <= SKIP_PACKET;
                    end case;
                end if;
            when LATCH_SRC_ADDR =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard        := '1';
                    
                    -- Latch Source IP Address
                    addr_next   <= data_in_user;
                    
                    stage_next  <= LATCH_GUIDPREFIX;
                    cnt_next    <= 0;
                end if;
            when LATCH_GUIDPREFIX =>
                -- Input FIFO Guard
                if ((is_meta = '1' and empty_meta /= (empty_meta'range => '1')) or (is_meta = '0' and empty_user /= (empty_user'range => '1'))) then
                    if (is_meta = '1') then
                        assert ((empty_meta xor r_map) = (empty_meta'range => '1')) severity FAILURE;
                        rd_meta     <= '1';
                    else
                        assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                        rd_guard    := '1';
                    end if;
                    
                    case (cnt) is
                        -- GUID Prefix 1/3
                        when 0 =>
                            if (is_meta = '1') then
                                guid_next(0)    <= data_in_meta;
                            else
                                guid_next(0)    <= data_in_user;
                            end if;
                            cnt_next    <= cnt + 1;
                        -- GUID Prefix 2/3
                        when 1 =>
                            if (is_meta = '1') then
                                guid_next(1)    <= data_in_meta;
                            else
                                guid_next(1)    <= data_in_user;
                            end if;
                            cnt_next    <= cnt + 1;
                        -- GUID Prefix 3/3
                        when 2 =>
                            if (is_meta = '1') then
                                guid_next(2)    <= data_in_meta;
                            else
                                guid_next(2)    <= data_in_user;
                            end if;
                            
                            if (is_meta = '1') then
                                case (meta_opcode) is
                                    when EMO_PARTICIPANT_UNMATCH =>
                                        assert stable(clk, last_word_in_meta = '1') severity FAILURE;
                                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                        cnt_next    <= 0;
                                    when EMO_LIVELINESS_UPDATE =>   
                                        assert stable(clk, last_word_in_meta = '1') severity FAILURE;
                                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                        cnt_next    <= 0;
                                    when others =>
                                        stage_next  <= LATCH_ENTITYID;
                                end case;
                            else
                                stage_next  <= LATCH_ENTITYID;
                            end if;
                        when others =>
                            null;
                    end case;
                end if;
            when LATCH_ENTITYID =>
                -- Input FIFO Guard
                if ((is_meta = '1' and empty_meta /= (empty_meta'range => '1')) or (is_meta = '0' and empty_user /= (empty_user'range => '1'))) then
                    if (is_meta = '1') then
                        assert ((empty_meta xor r_map) = (empty_meta'range => '1')) severity FAILURE;
                        
                        rd_meta         <= '1';
                        guid_next(3)    <= data_in_meta;
                        
                        case (meta_opcode) is
                            when EMO_ENDPOINT_MATCH =>
                                stage_next  <= LATCH_ENDPOINT_DATA;
                                cnt_next    <= 0;
                            when EMO_ENDPOINT_UNMATCH =>
                                assert stable(clk, last_word_in_meta = '1') severity FAILURE;
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 0;
                            when others =>
                                null;
                        end case;
                    -- Memory Operation Guard
                    else
                        assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                        
                        rd_guard        := '1';
                        guid_next(3)    <= data_in_user;
                        
                        case (opcode) is
                            when SID_DATA =>
                                stage_next  <= LATCH_EXTRA_DATA;
                                cnt_next    <= 0;
                            when SID_HEARTBEAT =>
                                stage_next  <= LATCH_HEARTBEAT;
                                cnt_next    <= 0;
                            when SID_GAP =>
                                stage_next  <= LATCH_GAP;
                                cnt_next    <= 0;
                            when others =>
                                null;
                        end case;
                    end if;
                end if;
            when LATCH_ENDPOINT_DATA =>
                assert (is_meta = '1') severity FAILURE;
                
                -- Input FIFO Guard
                if (empty_meta /= (empty_meta'range => '1')) then
                    assert ((empty_meta xor r_map) = (empty_meta'range => '1')) severity FAILURE;
                    
                    rd_meta     <= '1';
                    
                    case (cnt) is
                        -- IPv4 Address
                        when 0 =>
                            addr_next   <= data_in_meta;
                            cnt_next    <= cnt + 1;
                        -- UDP Port
                        when 1 =>
                            -- NOTE: Reader Flags are ignored, since they are only relevant for Writer Endpoints
                            portn_next  <= data_in_meta(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH);
                            
                            cnt_next    <= cnt + 1;
                        -- Lifespan Duration 1/2
                        when 2 =>
                            lifespan_next(0)    <= unsigned(data_in_meta);
                            cnt_next            <= cnt + 1;
                        -- Lifespan Duration 2/2
                        when 3 =>
                            lifespan_next(1)    <= unsigned(data_in_meta);
                            
                            case (meta_opcode) is
                                when EMO_ENDPOINT_MATCH =>
                                    assert stable(clk, last_word_in_meta = '1') severity FAILURE;
                                    
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 0;
                                when others =>
                                    null;
                            end case;
                        when others =>
                            null;
                    end case;
                end if;
            when LATCH_EXTRA_DATA =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard    := '1';
                    
                    case (cnt) is
                        -- Sequence Number 1/2
                        when 0 =>
                            seq_nr_next(0)  <= unsigned(data_in_user);
                            cnt_next        <= cnt + 1;
                        -- Sequence Number 2/2
                        when 1 =>
                            seq_nr_next(1)  <= unsigned(data_in_user);
                            -- Store Next Sequence Number
                            tmp_dw              := (0 => seq_nr(0), 1 => unsigned(data_in_user));
                            next_seq_nr_next    <= tmp_dw + 1;
                            cnt_next        <= cnt + 1;
                        -- Timestamp 1/2
                        when 2 =>
                            ts_next(0)      <= unsigned(data_in_user);
                            cnt_next        <= cnt + 1;
                        -- Timestamp 2/2
                        when 3 =>
                            ts_next(1)      <= unsigned(data_in_user);
                            
                            if (qos_flag = '1') then
                                stage_next  <= PROCESS_INLINE_QOS;
                            else
                                if (last_word_in_user = '1') then
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 0;
                                else
                                    stage_next  <= LATCH_PAYLOAD;
                                end if;
                            end if;
                        when others => 
                            null;
                    end case;
                end if;
            when PROCESS_INLINE_QOS =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard            := '1';
                    -- Reset Word Counter
                    reset_read_cnt      <= '1';
                    -- Latch Parameter End (In order to skip parameters)
                    parameter_end_next  <= unsigned(endian_swap(endian_flag,parameter_length));
                    -- DEFAULT STAGE
                    stage_next          <= SKIP_PARAMETER;
                    
                    case (endian_swap(endian_flag,parameter_id)) is
                        when PID_TOPIC_NAME =>
                            -- Ignore
                            null;
                        when PID_DURABILITY =>
                            -- Ignore
                            null;
                        when PID_PRESENTATION =>
                            -- Ignore
                            null;
                        when PID_DEADLINE =>
                            -- Ignore
                            null;
                        when PID_LATENCY_BUDGET =>
                            -- Ignore
                            null;
                        when PID_OWNERSHIP =>
                            -- Ignore
                            null;
                        when PID_OWNERSHIP_STRENGTH =>
                            -- Ignore
                            null;
                        when PID_LIVELINESS =>
                            -- Ignore
                            null;
                        when PID_PARTITION =>
                            -- Ignore
                            null;
                        when PID_RELIABILITY =>
                            -- Ignore
                            null;
                        when PID_DESTINATION_ORDER =>
                            -- Ignore
                            null;
                        when PID_TRANSPORT_PRIORITY =>
                            -- Ignore
                            null;
                        when PID_LIFESPAN =>
                            -- Ignore
                            null;
                        when PID_CONTENT_FILTER_INFO =>
                            -- Ignore
                            null;
                        when PID_COHERENT_SET =>
                            -- Ignore
                            null;
                        when PID_DIRECTED_WRITE =>
                            -- Ignore
                            null;
                        when PID_ORIGINAL_WRITER_INFO =>
                            -- Ignore
                            null;
                        when PID_GROUP_COHERENT_SET =>
                            -- Ignore
                            null;
                        when PID_GROUP_SEQ_NUM =>
                            -- Ignore
                            null;
                        when PID_WRITER_GROUP_INFO =>
                            -- Ignore
                            null;
                        when PID_SECURE_WRITER_GROUP_INFO =>
                            -- Ignore
                            null;
                        when PID_KEY_HASH =>
                            key_hash_rcvd_next  <= '1';
                            stage_next          <= LATCH_KEY_HASH;
                            cnt_next            <= 0;
                        when PID_STATUS_INFO =>
                            stage_next  <= LATCH_STATUS_INFO;
                        when PID_PAD =>
                            -- Ignore
                            null;
                        when PID_SENTINEL =>
                            -- Reset
                            parameter_end_next  <= (others => '1');
                            -- EXIT
                            if (last_word_in_user = '1') then
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 0;
                            else
                                stage_next  <= LATCH_PAYLOAD;
                            end if;
                        when others =>
                            -- If MUST_UNDERSTAND Flag is set, we have incompatible communication. Drop Packet
                            if (endian_swap(endian_flag,parameter_id)(PID_MUST_UNDERSTAND_FLAG_POS) = '1') then
                                stage_next  <= SKIP_PACKET;
                            -- Else skip Unknown Parameter
                            else
                                stage_next  <= SKIP_PARAMETER;
                            end if;
                    end case;
                end if;
            when LATCH_KEY_HASH =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard    := '1';
                    
                    case (cnt) is
                        -- Key Hash 1/4
                        when 0 =>
                            key_hash_next(0)    <= data_in_user;
                            cnt_next            <= cnt + 1;
                        -- Key Hash 2/4
                        when 1 =>
                            key_hash_next(1)    <= data_in_user;
                            cnt_next            <= cnt + 1;
                        -- Key Hash 3/4
                        when 2 =>
                            key_hash_next(2)    <= data_in_user;
                            cnt_next            <= cnt + 1;
                        -- Key Hash 4/4
                        when 3 =>
                            key_hash_next(3)    <= data_in_user;
                            
                            -- EXIT
                            stage_next  <= SKIP_PARAMETER;
                        when others => 
                            null;
                    end case;
                end if;
            when LATCH_STATUS_INFO =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard            := '1';
                    
                    status_info_next    <= data_in_user;
                    
                    -- EXIT
                    stage_next  <= SKIP_PARAMETER;
                end if;
            when LATCH_PAYLOAD =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    if (payload_ready_in = '1') then
                        rd_guard    := '1';
                        payload_addr        <= payload_addr_base;
                        payload_valid_in    <= '1';
                        payload_write_data  <= data_in_user;
                        
                        -- Last Word
                        if (last_word_in_user = '1') then
                            payload_max_addr_next   <= payload_addr_base;
                            
                            stage_next  <= INITIATE_ENDPOINT_SEARCH;
                            cnt_next    <= 0;
                        else
                            -- Payload does not fit in Memory
                            if (payload_addr_base = MAX_PAYLOAD_ADDRESS) then
                                assert stable(clk, FALSE) report "Payload does not fit in memory" severity WARNING;
                                -- Abort
                                stage_next  <= SKIP_PACKET;
                            else
                                payload_addr_base_next  <= payload_addr_base + 1;
                            end if;
                        end if;
                    end if;
                end if;
            when LATCH_HEARTBEAT =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard    := '1';
                    
                    case (cnt) is
                        -- First Sequence Number 1/2
                        when 0 =>
                            first_seq_nr_next(0)    <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- First Sequence Number 2/2
                        when 1 =>
                            first_seq_nr_next(1)    <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- Last Sequence Number 1/2
                        when 2 =>
                            last_seq_nr_next(0)     <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- Last Sequence Number 2/2
                        when 3 =>
                            last_seq_nr_next(1)     <= unsigned(data_in_user);
                            
                            stage_next  <= INITIATE_ENDPOINT_SEARCH;
                            cnt_next    <= 0;
                        when others => 
                            null;
                    end case;
                end if;
            when LATCH_GAP =>
                -- Input FIFO Guard
                if (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    
                    rd_guard    := '1';
                    
                    case (cnt) is
                        -- GapStart Sequence Number  1/2
                        when 0 =>
                            gap_start_next(0)       <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- GapStart Sequence Number  2/2
                        when 1 =>
                            gap_start_next(1)       <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- GapList.Base 1/2
                        when 2 =>
                            gap_list_base_next(0)   <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- GapList.Base 2/2
                        when 3 =>
                            gap_list_base_next(1)   <= unsigned(data_in_user);
                            cnt_next                <= cnt + 1;
                        -- GapList.NumBits
                        when 4 =>
                            gap_list_end_next   <= gap_list_base + to_integer(unsigned(data_in_user));
                            bitmap_cnt_next     <= unsigned(round_slv(data_in_user(log2c(MAX_BITMAP_WIDTH)-1 downto 0),bitmap_cnt'length));
                            cnt2_next           <= 0;
                            cnt_next            <= cnt + 1;
                        -- GapList.Bitmap
                        when 5 =>
                            -- Read Bitmap
                            if (cnt2 < bitmap_cnt) then
                                cnt2_next <= cnt2 + 1;
                                
                                bitmap_latch_next(cnt2) <= data_in_user;
                            else
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 0;
                            end if;
                        when others =>
                            null;
                    end case;
                    
                end if;
            when INITIATE_ENDPOINT_SEARCH =>
                -- Memory Operation Guard
                if (mem_op_done = '1') then
                    case (cnt) is
                        when 0 =>
                            if (r_map(ind) = '1') then
                                if (is_meta = '1') then
                                    case (meta_opcode) is
                                        when EMO_ENDPOINT_MATCH =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= SEARCH_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.guid          <= guid;
                                            stage_next          <= METATRAFFIC_OPERATION;
                                            cnt_next            <= 0;
                                        when EMO_ENDPOINT_UNMATCH =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= SEARCH_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.field_flags   <= EMF_WRITER_ID_FLAG;
                                            mem_r.guid          <= guid;
                                            stage_next          <= METATRAFFIC_OPERATION;
                                            cnt_next            <= 0;
                                        when EMO_PARTICIPANT_UNMATCH =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= GET_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.addr          <= mem_occupied_head(ind);
                                            mem_r.field_flags   <= EMF_GUIDPREFIX_FLAG or EMF_WRITER_ID_FLAG;
                                            stage_next          <= METATRAFFIC_OPERATION;
                                            cnt_next            <= 0;
                                        when EMO_LIVELINESS_UPDATE =>
                                            if (CONFIG_ARRAY_T(ind).LIVELINESS_QOS /= MANUAL_BY_TOPIC_LIVELINESS_QOS) then
                                                mem_op_start        <= '1';
                                                mem_opcode          <= GET_ENDPOINT;
                                                mem_r.i             <= ind;
                                                mem_r.addr          <= mem_occupied_head(ind);
                                                mem_r.field_flags   <= EMF_GUIDPREFIX_FLAG;
                                                stage_next          <= METATRAFFIC_OPERATION;
                                                cnt_next            <= 0;
                                            else
                                                cnt_next    <= cnt + 1; -- NEXT READER
                                            end if;
                                        when others =>
                                            null;
                                    end case;
                                else
                                    case (opcode) is
                                        when SID_DATA =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= SEARCH_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.guid          <= guid;
                                            mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG or EMF_LIFESPAN_DURATION_FLAG or EMF_WRITER_ID_FLAG;
                                            
                                            stage_next  <= INITIATE_ADD_CACHE_CHANGE_REQUEST;
                                        when SID_HEARTBEAT =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= SEARCH_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.guid          <= guid;
                                            mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG or EMF_RES_TIME_FLAG;
                                            
                                            stage_next  <= PROCESS_HEARTBEAT;
                                            cnt_next    <= 0;
                                        when SID_GAP =>
                                            mem_op_start        <= '1';
                                            mem_opcode          <= SEARCH_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.guid          <= guid;
                                            mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG;
                                            
                                            stage_next  <= PROCESS_GAP;
                                        when others =>
                                            null;
                                    end case;
                                end if;
                            else
                                cnt_next    <= cnt + 1; -- NEXT READER
                            end if;
                        -- NEXT READER
                        when 1 =>
                            -- No more Writers
                            if (ind = NUM_READERS-1) then
                                -- DONE
                                if (is_meta = '1') then
                                    stage_next  <= SKIP_META_OPERATION;
                                else
                                    stage_next  <= SKIP_PACKET;
                                end if;
                            else
                                -- Next Reader
                                ind_next    <= ind + 1;
                                cnt_next    <= 0;
                            end if;
                        when others =>
                            null;
                    end case;
                end if;
            when METATRAFFIC_OPERATION =>
                -- Memory Operation Guard
                if (mem_op_done = '1') then
                    case (meta_opcode) is
                        when EMO_ENDPOINT_MATCH =>
                            -- Endpoint already in Memory
                            if (mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                                -- Update the Endpoint Data
                                -- NOTE: The Lease Duration is NOT updated in case of an update. That is the responsibility of the Liveliness Update
                                mem_op_start        <= '1';
                                mem_opcode          <= UPDATE_ENDPOINT;
                                mem_r.i             <= ind;
                                mem_r.addr          <= mem_endpoint_data.addr;
                                mem_r.field_flags   <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_LIFESPAN_DURATION_FLAG;
                                mem_r.ip_addr       <= addr;
                                mem_r.portn         <= portn;
                                mem_r.lifespan      <= lifespan;
                                
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            -- Endpoint Memory Full
                            elsif (mem_empty_head(ind) = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            else
                                assert (mem_empty_head(ind) /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                                
                                -- Insert Matched Remote Endpoint
                                mem_op_start    <= '1';
                                mem_opcode      <= INSERT_ENDPOINT;
                                mem_r.i         <= ind;
                                mem_r.guid      <= guid;
                                mem_r.ip_addr   <= addr;
                                mem_r.portn     <= portn;
                                mem_r.lifespan  <= lifespan;
                                if (CONFIG_ARRAY_T(ind).DURABILITY_QOS = VOLATILE_DURABILITY_QOS) then
                                    mem_r.next_seq_nr   <= SEQUENCENUMBER_UNKNOWN;
                                else
                                    mem_r.next_seq_nr   <= FIRST_SEQUENCENUMBER;
                                end if;
                                if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE) then
                                    tmp_dw  := time + CONFIG_ARRAY_T(ind).LEASE_DURATION;
                                    mem_r.lease_deadline    <= tmp_dw;
                                    
                                    -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                    -- Update Check Time
                                    if (tmp_dw < check_time) then
                                        check_time_next <= tmp_dw;
                                    end if;
                                else
                                    mem_r.lease_deadline    <= TIME_INVALID;
                                end if;
                                
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            end if;
                        when EMO_ENDPOINT_UNMATCH =>
                            -- Endpoint not in Memory
                            if (mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            else
                                assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_WRITER_ID_FLAG)) severity FAILURE;
                                
                                -- Propagate Removal (Sent Memory Position as ID)
                                start_hc(ind)       <= '1';
                                opcode_hc(ind)      <= REMOVE_WRITER;
                                data_out_hc(ind)    <= std_logic_vector(to_unsigned(mem_endpoint_data.writer_id, WORD_WIDTH));
                                
                                -- NOTE: Ignore return Code
                                
                                -- Wait for Operation Acknowledgement
                                if (ack_hc(ind) = '1') then
                                    -- Remove Unmatched Remote Endpoint
                                    mem_op_start    <= '1';
                                    mem_opcode      <= REMOVE_ENDPOINT;
                                    mem_r.i         <= ind;
                                    mem_r.addr      <= mem_endpoint_data.addr;
                                    
                                    -- EXIT
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 1; -- NEXT READER
                                end if;
                            end if;
                        when EMO_PARTICIPANT_UNMATCH =>
                            case (cnt) is
                                when 0 =>
                                    -- Reached End of Endpoints
                                    if (mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                        -- EXIT
                                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                        cnt_next    <= 1; -- NEXT READER
                                    else
                                        assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_GUIDPREFIX_FLAG or EMF_WRITER_ID_FLAG)) severity FAILURE;
                                        
                                        -- Participant Match
                                        if (guid(0) = mem_endpoint_data.guid(0) and guid(1) = mem_endpoint_data.guid(1) and guid(2) = mem_endpoint_data.guid(2)) then
                                            -- Propagate Removal (Sent Memory Position as ID)
                                            start_hc(ind)       <= '1';
                                            opcode_hc(ind)      <= REMOVE_WRITER;
                                            data_out_hc(ind)    <= std_logic_vector(to_unsigned(mem_endpoint_data.writer_id, WORD_WIDTH));
                                            -- Wait for Operation Acknowledgement
                                            if (ack_hc(ind) = '1') then
                                                -- Remove Unmatched Remote Endpoint
                                                mem_op_start    <= '1';
                                                mem_opcode      <= REMOVE_ENDPOINT;
                                                mem_r.i         <= ind;
                                                mem_r.addr      <= mem_endpoint_data.addr;
                                                -- NOTE: After removal, mem_endpoint_data.addr is pointing to the next slot (or ENDPOINT_MEMORY_MAX_ADDRESS)
                                                cnt_next        <= 2; -- GET Endpoint
                                            end if;
                                        else
                                            cnt_next    <= 1; -- GET NEXT Endpoint
                                        end if;
                                    end if;
                                -- GET NEXT ENDPOINT
                                when 1 =>
                                    -- Continue Search
                                    mem_op_start        <= '1';
                                    mem_opcode          <= GET_NEXT_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_GUIDPREFIX_FLAG or EMF_WRITER_ID_FLAG;
                                    cnt_next            <= 0;
                                -- GET ENDPOINT
                                when 2 =>
                                    -- Continue Search
                                    mem_op_start        <= '1';
                                    mem_opcode          <= GET_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_GUIDPREFIX_FLAG  or EMF_WRITER_ID_FLAG;
                                    cnt_next            <= 0;
                                when others =>
                                    null;
                            end case;
                        when EMO_LIVELINESS_UPDATE =>
                            assert (CONFIG_ARRAY_T(ind).LIVELINESS_QOS /= MANUAL_BY_TOPIC_LIVELINESS_QOS) severity FAILURE;
                            
                            case (cnt) is
                                -- UPDATE Endpoint
                                when 0 =>
                                    -- No matches in memory
                                    if (mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                        -- EXIT
                                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                        cnt_next    <= 1; -- NEXT READER
                                    else
                                        assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_GUIDPREFIX_FLAG)) severity FAILURE;
                                        
                                        -- Participant Match
                                        if (guid(0) = mem_endpoint_data.guid(0) and guid(1) = mem_endpoint_data.guid(1) and guid(2) = mem_endpoint_data.guid(2)) then
                                            -- Renew Lease of Remote Endpoint
                                            mem_op_start        <= '1';
                                            mem_opcode          <= UPDATE_ENDPOINT;
                                            mem_r.i             <= ind;
                                            mem_r.addr          <= mem_endpoint_data.addr;
                                            mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG;
                                            if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE) then
                                                tmp_dw  := time + CONFIG_ARRAY_T(ind).LEASE_DURATION;
                                                mem_r.lease_deadline    <= tmp_dw;
                                                
                                                -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                                -- Update Check Time
                                                if (tmp_dw < check_time) then
                                                    check_time_next <= tmp_dw;
                                                end if;
                                            else
                                                mem_r.lease_deadline    <= TIME_INVALID;
                                            end if;
                                        end if;
                                        cnt_next    <= 1; -- GET NEXT Endpoint
                                    end if;
                                -- GET NEXT Endpoint
                                when 1 =>
                                    -- Continue Search
                                    mem_op_start        <= '1';
                                    mem_opcode          <= GET_NEXT_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_GUIDPREFIX_FLAG;
                                    cnt_next            <= 0;
                                when others =>
                                    null;
                            end case;
                        when others =>
                            null;
                    end case;
                end if;
            when PROCESS_HEARTBEAT =>
                -- Wait for Endpoint Data
                if (mem_op_done = '1') then
                    
                    case (cnt) is
                        -- LEASE HANDLING
                        when 0 =>
                            -- Endpoint in Buffer
                            if (mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                                
                                -- Liveliness Assertion
                                if (liveliness_flag = '1') then
                                    mem_op_start        <= '1';
                                    mem_opcode          <= UPDATE_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG;
                                    cnt_next            <= cnt + 1;
                                    if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE) then
                                        tmp_dw  := time + CONFIG_ARRAY_T(ind).LEASE_DURATION;
                                        
                                        mem_r.lease_deadline    <= tmp_dw;
                                        
                                        -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                        -- Update Check Time
                                        if (tmp_dw < check_time) then
                                            check_time_next <= tmp_dw;
                                        end if;
                                    else
                                        mem_r.lease_deadline    <= TIME_INVALID;
                                    end if;
                                else
                                    cnt_next    <= cnt + 1;
                                end if;
                            else
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            end if;
                        -- RESPONSE TIME HANDLING
                        when 1 =>
                            assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_RES_TIME_FLAG or EMF_NEXT_SEQ_NR_FLAG)) severity FAILURE;
                            assert (mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                            
                            -- No scheduled Heartbeat Response
                            if (mem_endpoint_data.res_time = TIME_INVALID) then
                                -- If Reader is Volatile and we have not received anything from the writer yet
                                if (CONFIG_ARRAY_T(ind).DURABILITY_QOS = VOLATILE_DURABILITY_QOS and mem_endpoint_data.next_seq_nr = SEQUENCENUMBER_UNKNOWN) then
                                    mem_op_start        <= '1';
                                    mem_opcode          <= UPDATE_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG or EMF_RES_TIME_FLAG;
                                    
                                    -- Mark last available SN as next expected (Ignore historical data)
                                    if (first_seq_nr <= last_seq_nr) then
                                        mem_r.next_seq_nr   <= last_seq_nr;
                                    else
                                        mem_r.next_seq_nr   <= first_seq_nr;
                                    end if;
                                    
                                    -- NOTE: Only response with ACKNACK if SN is available (Or no Final Flag)
                                    if (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY /= DURATION_INFINITE and (first_seq_nr <= last_seq_nr or final_flag = '0')) then
                                        tmp_dw  := time + CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY;
                                        mem_r.res_time  <= tmp_dw;
                                        -- NOTE: Last Bit denotes if this is Response or Suppression Delay
                                        mem_r.res_time(1)(0)    <= '0';
                                        
                                        -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                        -- Update Check Time
                                        if (tmp_dw < check_time) then
                                            check_time_next <= tmp_dw;
                                        end if;
                                    else
                                        mem_r.res_time  <= TIME_INVALID;
                                    end if;
                                    
                                    -- EXIT
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 1; -- NEXT READER
                                -- If current Sequence Number obsolete (removed from source history cache)
                                elsif (first_seq_nr > mem_endpoint_data.next_seq_nr) then
                                    mem_op_start        <= '1';
                                    mem_opcode          <= UPDATE_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG or EMF_RES_TIME_FLAG;
                                    -- Store new expected Sequence Number and set Response Delay
                                    mem_r.next_seq_nr   <= first_seq_nr;
                                    
                                    -- NOTE: Only response with ACKNACK if SN is available (Or no Final Flag)
                                    if (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY /= DURATION_INFINITE and (first_seq_nr <= last_seq_nr or final_flag = '0')) then
                                        tmp_dw  := time + CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY;
                                        
                                        mem_r.res_time  <= tmp_dw;
                                        -- NOTE: Last Bit denotes if this is Response or Suppression Delay
                                        mem_r.res_time(1)(0)    <= '0';
                                        
                                        -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                        -- Update Check Time
                                        if (tmp_dw < check_time) then
                                            check_time_next <= tmp_dw;
                                        end if;
                                    else
                                        mem_r.res_time  <= TIME_INVALID;
                                    end if;
                                    
                                    -- EXIT
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 1; -- NEXT READER
                                -- If new Sequence Number is available or Writer expects ACKNACK
                                elsif (last_seq_nr >= mem_endpoint_data.next_seq_nr or final_flag = '0') then
                                    -- Set Response Delay
                                    mem_op_start        <= '1';
                                    mem_opcode          <= UPDATE_ENDPOINT;
                                    mem_r.i             <= ind;    
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_RES_TIME_FLAG;
                                    
                                    if (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY /= DURATION_INFINITE) then
                                        tmp_dw  := time + CONFIG_ARRAY_T(ind).HEARTBEAT_RESPONSE_DELAY;
                                        
                                        mem_r.res_time  <= tmp_dw;
                                        -- NOTE: Last Bit denotes if this is Response or Suppression Delay
                                        mem_r.res_time(1)(0)    <= '0';
                                        
                                        -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                        -- Update Check Time
                                        if (tmp_dw < check_time) then
                                            check_time_next <= tmp_dw;
                                        end if;
                                    else
                                        mem_r.res_time  <= TIME_INVALID;
                                    end if;
                                    
                                    -- EXIT
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 1; -- NEXT READER
                                else
                                    -- EXIT
                                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                    cnt_next    <= 1; -- NEXT READER
                                end if;
                            -- Currently in Heartbeat Response Delay
                            elsif (mem_endpoint_data.res_time(1)(0) = '0') then
                                -- If current Sequence Number obsolete (removed from source history cache)
                                if (first_seq_nr > mem_endpoint_data.next_seq_nr) then
                                    -- NOTE: Even if first_seq_nr > last_seq_nr, meaning that the writer does not have any stored SNs
                                    --       we don't cancel the response, because it may have been initiated by the Final Flag.
                                    
                                    mem_op_start        <= '1';
                                    mem_opcode          <= UPDATE_ENDPOINT;
                                    mem_r.i             <= ind;
                                    mem_r.addr          <= mem_endpoint_data.addr;
                                    mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG;
                                    -- Store new expected Sequence Number
                                    mem_r.next_seq_nr   <= first_seq_nr;
                                end if;
                                
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            else
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            end if;
                        when others =>
                            null;
                    end case;
                end if;
            when PROCESS_GAP =>
                -- Precondition: mem_endpoint_data set (EMF_NEXT_SEQ_NR_FLAG)
                
                -- Wait for Endpoint Search
                if (mem_op_done = '1') then
                
                    -- Known Remote Endpoint
                    if (mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                        assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_NEXT_SEQ_NR_FLAG)) severity FAILURE;
                        
                        -- GAP is relevant
                        if (gap_start <= mem_endpoint_data.next_seq_nr and mem_endpoint_data.next_seq_nr <= gap_list_end) then
                            -- Next Expected is in GAP List
                            if (gap_list_base <= mem_endpoint_data.next_seq_nr) then
                                -- Begin searching next valid SN from the current expected in the bitmap list
                                next_seq_nr_next    <= mem_endpoint_data.next_seq_nr;
                                bitmap_pos_next     <= to_integer(mem_endpoint_data.next_seq_nr - gap_list_base);
                            else
                                -- Begin searching next valid SN from the beginning of the bitmap list
                                next_seq_nr_next    <= gap_list_base;
                                bitmap_pos_next     <= 0;
                            end if;
                            stage_next  <= FIND_NEXT_VALID_IN_BITMAP;
                        else
                            -- EXIT
                            stage_next  <= INITIATE_ENDPOINT_SEARCH;
                            cnt_next    <= 1; -- NEXT READER
                        end if;
                    else
                        -- EXIT
                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                        cnt_next    <= 1; -- NEXT READER
                    end if;
                end if;
            when FIND_NEXT_VALID_IN_BITMAP =>
                -- Memory Operation Guard
                if (mem_op_done = '1') then
                    tmp_bitmap  := to_slv_bitmap(bitmap_latch);
                    
                    -- First valid sequence number found
                    if (tmp_bitmap(bitmap_pos) = '0') then
                        -- Update next sequence number
                        mem_op_start        <= '1';
                        mem_opcode          <= UPDATE_ENDPOINT;
                        mem_r.i             <= ind;
                        mem_r.addr          <= mem_endpoint_data.addr;
                        mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG;
                        mem_r.next_seq_nr   <= next_seq_nr;
                        
                        -- Continue
                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                        cnt_next    <= 1; -- NEXT READER
                    else
                        -- Continue SN search
                        bitmap_pos_next     <= bitmap_pos + 1;
                        next_seq_nr_next    <= next_seq_nr + 1;
                    end if;
                end if;
            when INITIATE_ADD_CACHE_CHANGE_REQUEST =>
                -- Wait for Endpoint Data
                if (mem_op_done = '1') then
                    -- Unknown Endpoint
                    if (mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                        -- Ignore/EXIT
                        stage_next  <= INITIATE_ENDPOINT_SEARCH;
                        cnt_next    <= 1; -- NEXT READER
                    else
                        assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_NEXT_SEQ_NR_FLAG or EMF_LIFESPAN_DURATION_FLAG)) severity FAILURE;
                        
                        -- Data is Next expected Sequence Number
                        if ((CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and seq_nr = mem_endpoint_data.next_seq_nr) or (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = BEST_EFFORT_RELIABILITY_QOS and seq_nr >= mem_endpoint_data.next_seq_nr) or (CONFIG_ARRAY_T(ind).DURABILITY_QOS = VOLATILE_DURABILITY_QOS and mem_endpoint_data.next_seq_nr = SEQUENCENUMBER_UNKNOWN)) then
                            -- SANITY CHECK: Skip if no Hash Key and no Payload
                            if (CONFIG_ARRAY_T(ind).WITH_KEY and key_hash_rcvd = '0' and data_flag = '0' and key_flag = '0') then
                                -- EXIT
                                stage_next  <= INITIATE_ENDPOINT_SEARCH;
                                cnt_next    <= 1; -- NEXT READER
                            else
                                start_hc(ind)   <= '1';
                                opcode_hc(ind)  <= ADD_CACHE_CHANGE;
                                -- Wait until History Cache acknowledges request
                                if (ack_hc(ind) = '1') then
                                    -- TODO: Use source timestamp if clocks with remote synchronized
                                    -- Calculate Sample Lifespan Deadline
                                    if (mem_endpoint_data.lifespan /= DURATION_INFINITE) then
                                        lifespan_next   <= time + mem_endpoint_data.lifespan;
                                    end if;
                                    
                                    stage_next      <= ADD_CACHE_CHANGE;
                                    cnt_next        <= 0;
                                end if;
                            end if;
                        else
                            -- Ignore/EXIT
                            stage_next  <= INITIATE_ENDPOINT_SEARCH;
                            cnt_next    <= 1; -- NEXT READER
                        end if;
                    end if;
                end if;
            when ADD_CACHE_CHANGE =>
                case (cnt) is
                    -- Status Info
                    when 0 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= status_info;
                        data_out_hc(ind)(SSI_KEY_HASH_FLAG) <= key_hash_rcvd;
                        -- NOTE: The SSI_DATA_FLAG states if the Payload contains normal Data for the Sample or the Serialized Key for the Key Hash calculation
                        data_out_hc(ind)(SSI_DATA_FLAG)     <= data_flag;
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Timestamp 1/2
                    when 1 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= std_logic_vector(ts(0));
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Timestamp 2/2
                    when 2 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= std_logic_vector(ts(1));
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Lifespan Deadline 1/2
                    when 3 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= std_logic_vector(lifespan(0));
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Lifespan Deadline 2/2
                    when 4 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= std_logic_vector(lifespan(1));
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            -- Skip Key Hash, if not received
                            if (key_hash_rcvd = '0') then
                                cnt_next    <= cnt + 5; -- Endpoint Memory Position
                            else
                                cnt_next    <= cnt + 1;
                            end if;
                        end if;
                    -- Key hash 1/4
                    when 5 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= key_hash(0);
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Key Hash 2/4
                    when 6 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= key_hash(1);
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Key Hash 3/4
                    when 7 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= key_hash(2);
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Key hash 4/4
                    when 8 =>
                        valid_out_hc(ind)   <= '1';
                        data_out_hc(ind)    <= key_hash(3);
                        -- Output Guard
                        if (ready_out_hc(ind) = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- Endpoint Memory Position
                    when 9 =>
                        -- Wait for Endpoint Search
                        if (mem_op_done = '1') then
                            assert stable(clk, mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                            assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_WRITER_ID_FLAG)) severity FAILURE;
                            
                            valid_out_hc(ind)   <= '1';
                            data_out_hc(ind)    <= std_logic_vector(to_unsigned(mem_endpoint_data.writer_id, WORD_WIDTH));
                            
                            -- Output Guard
                            if (ready_out_hc(ind) = '1') then
                                -- NOTE: We only push the Payload if there is Data, or if the Key Hash was not received and we need to push
                                --       the serialized Key.
                                -- Payload exists
                                if ((data_flag = '1' or key_hash_rcvd = '0') and payload_max_addr /= (payload_max_addr'reverse_range => '0')) then
                                    payload_addr_base_next  <= (others => '0');
                                    stage_next              <= PUSH_PAYLOAD;
                                    cnt_next                <= 0;
                                else
                                    -- DONE
                                    last_word_out_hc(ind)   <= '1';
                                    stage_next              <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
                                end if;
                            end if;
                        end if;
                    when others =>
                        null;
                end case;
            when PUSH_PAYLOAD =>
                case (cnt) is
                    -- GET
                    when 0 =>
                        payload_addr        <= payload_addr_base;
                        payload_read        <= '1';
                        payload_valid_in    <= '1';
                        
                        if (payload_ready_in = '1') then
                            cnt_next    <= cnt + 1;
                        end if;
                    -- READ/PUSH
                    when 1 =>
                        if (payload_valid_out = '1') then
                            valid_out_hc(ind)       <= '1';
                            data_out_hc(ind)        <= payload_read_data;
                            if (payload_addr_base = payload_max_addr) then
                                last_word_out_hc(ind)   <= '1';
                            end if;
                            
                            if (ready_out_hc(ind) = '1') then
                                payload_ready_out   <= '1';
                                
                                -- Last Payload Word
                                if (payload_addr_base = payload_max_addr) then
                                    stage_next  <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
                                else
                                    payload_addr_base_next  <= payload_addr_base + 1;
                                    cnt_next                <= 0; -- GET
                                end if;
                            end if;
                        end if;
                    when others =>
                        null;
                end case;
            when FINALIZE_ADD_CACHE_CHANGE_REQUEST =>
                -- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE)
                assert (mem_op_done = '1') severity FAILURE;
                
                -- Wait for History Cache Response
                if (done_hc(ind) = '1') then
                    
                    -- NOTE: The Lease Duration is also updated if the Cache Change is not accepted. This in effect "skews" the
                    --       "correctness" of the Writer Liveliness Protocol until the reader has no pending request from the Writer.
                    
                    -- Update Endpoint
                    mem_op_start        <= '1';
                    mem_opcode          <= UPDATE_ENDPOINT;
                    mem_r.i             <= ind;
                    mem_r.addr          <= mem_endpoint_data.addr;
                    mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG;
                    if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE) then
                        tmp_dw  := time + CONFIG_ARRAY_T(ind).LEASE_DURATION;
                        mem_r.lease_deadline    <= tmp_dw;
                        
                        -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                        -- Update Check Time
                        if (tmp_dw < check_time) then
                            check_time_next <= tmp_dw;
                        end if;
                    else
                        mem_r.lease_deadline    <= TIME_INVALID;
                    end if;
                    
                    -- NOTE: In case the operation was unsucessfull (e.g. reached Resource Limits), the Sequence Number is not updated
                    --       and thus not "acknowledged".
                    -- Operation was Accepted
                    if (ret_hc(ind) = OK) then
                        -- Update also next sequence number
                        mem_r.field_flags   <= EMF_NEXT_SEQ_NR_FLAG or EMF_LEASE_DEADLINE_FLAG;
                        mem_r.next_seq_nr   <= next_seq_nr;
                    end if;
                    
                    -- EXIT
                    stage_next  <= INITIATE_ENDPOINT_SEARCH;
                    cnt_next    <= 1; -- NEXT READER
                end if;
            when ENDPOINT_STALE_CHECK =>
                -- Precondition: mem_endpoint_data set (EMF_LEASE_DEADLINE_FLAG, EMF_RES_TIME_FLAG)
                
                -- Memory Operation Guard
                if (mem_op_done = '1') then
                    case (cnt) is
                        -- GET NEXT READER
                        when 0 =>
                            -- No more Writers
                            if (ind = NUM_READERS-1) then
                                -- Reset
                                stale_check_next    <= '0';
                                
                                -- DONE
                                stage_next  <= IDLE;
                            else
                                -- Next Writer
                                ind_next    <= ind + 1;
                                cnt_next    <= cnt + 1;
                            end if;
                        -- GET FIRST Endpoint
                        when 1 =>
                            if (r_map(ind) = '1') then
                                mem_op_start        <= '1';
                                mem_opcode          <= GET_ENDPOINT;
                                mem_r.i             <= ind;
                                mem_r.addr          <= mem_occupied_head(ind);
                                mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_WRITER_ID_FLAG;
                                cnt_next            <= 4; -- CHECK Lease
                            else
                                cnt_next    <= 0; -- GET NEXT READER
                            end if;
                        -- GET Endpoint
                        when 2 =>
                            mem_op_start        <= '1';
                            mem_opcode          <= GET_ENDPOINT;
                            mem_r.i             <= ind;
                            mem_r.addr          <= mem_endpoint_data.addr;
                            mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_WRITER_ID_FLAG;
                            cnt_next            <= 4; -- CHECK Lease
                        -- GET NEXT Endpoint
                        when 3 =>
                            mem_op_start        <= '1';
                            mem_opcode          <= GET_NEXT_ENDPOINT;
                            mem_r.i             <= ind;
                            mem_r.addr          <= mem_endpoint_data.addr;
                            mem_r.field_flags   <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_WRITER_ID_FLAG;
                            cnt_next            <= 4; -- CHECK Lease
                        -- CHECK Lease
                        when 4 =>
                            -- End of Endpoints
                            if (mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                -- Continue
                                cnt_next    <= 0; -- GET NEXT READER
                            else
                                assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_LEASE_DEADLINE_FLAG or EMF_WRITER_ID_FLAG)) severity FAILURE;
                                
                                -- Endpoint Lease Expired
                                if (mem_endpoint_data.lease_deadline /= TIME_INVALID) then
                                    if (mem_endpoint_data.lease_deadline <= time) then
                                        -- Propagate Removal (Sent Memory Position as ID)
                                        start_hc(ind)       <= '1';
                                        opcode_hc(ind)      <= REMOVE_WRITER;
                                        data_out_hc(ind)    <= std_logic_vector(to_unsigned(mem_endpoint_data.writer_id, WORD_WIDTH));
                                        -- Wait for Operation Acknowledgement
                                        if (ack_hc(ind) = '1') then
                                            -- Remove Endpoint
                                            mem_op_start    <= '1';
                                            mem_opcode      <= REMOVE_ENDPOINT;
                                            mem_r.i         <= ind;
                                            mem_r.addr      <= mem_endpoint_data.addr;
                                            cnt_next        <= 2; -- GET Endpoint
                                        end if;
                                    else
                                        if (mem_endpoint_data.lease_deadline < check_time) then
                                            check_time_next <= mem_endpoint_data.lease_deadline;
                                        end if;
                                        cnt_next        <= cnt + 1;
                                    end if;
                                else
                                    cnt_next    <= cnt + 1;
                                end if;
                            end if;
                        -- CHECK Response Time
                        when 5 =>
                            assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_RES_TIME_FLAG)) severity FAILURE;
                            
                            -- Response Time valid
                            if (mem_endpoint_data.res_time /= TIME_INVALID) then
                                assert (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) severity FAILURE;
                                
                                -- Response Time reached
                                if (mem_endpoint_data.res_time <= time) then
                                    -- If Suppression Delay passed, zero the time
                                    if(mem_endpoint_data.res_time(1)(0) = '1') then
                                        -- Disable Suppression
                                        mem_op_start        <= '1';
                                        mem_opcode          <= UPDATE_ENDPOINT;
                                        mem_r.i             <= ind;
                                        mem_r.addr          <= mem_endpoint_data.addr;
                                        mem_r.field_flags   <= EMF_RES_TIME_FLAG;
                                        mem_r.res_time      <= TIME_INVALID;
                                        cnt_next            <= 3; -- GET NEXT Endpoint
                                    -- If Response Delay Passed
                                    else
                                        -- Get Additional Data
                                        mem_op_start        <= '1';
                                        mem_opcode          <= GET_ENDPOINT;
                                        mem_r.i             <= ind;
                                        mem_r.addr          <= mem_endpoint_data.addr;
                                        mem_r.field_flags   <= EMF_ENTITYID_FLAG or EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_NEXT_SEQ_NR_FLAG;
                                        cnt_next            <= 6; -- UPDATE Endpoint
                                    end if;
                                else
                                    if (mem_endpoint_data.res_time < check_time) then
                                        check_time_next <= mem_endpoint_data.res_time;
                                    end if;
                                    cnt_next    <= 3; -- GET NEXT Endpoint
                                end if;
                            else
                                cnt_next    <= 3; -- GET NEXT Endpoint
                            end if;
                        -- UPDATE Endpoint
                        when 6 =>
                            assert (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) severity FAILURE;
                            assert (mem_op_done = '1') severity FAILURE;
                            assert (mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                                
                            mem_op_start        <= '1';
                            mem_opcode          <= UPDATE_ENDPOINT;
                            mem_r.i             <= ind;
                            mem_r.addr          <= mem_endpoint_data.addr;
                            mem_r.field_flags   <= EMF_RES_TIME_FLAG;
                            
                            -- Set Heartbeat Suppression Time
                            if (CONFIG_ARRAY_T(ind).HEARTBEAT_SUPPRESSION_DELAY /= DURATION_INFINITE and CONFIG_ARRAY_T(ind).HEARTBEAT_SUPPRESSION_DELAY /= DURATION_ZERO) then
                                tmp_dw := time + CONFIG_ARRAY_T(ind).HEARTBEAT_SUPPRESSION_DELAY;
                                -- Set Heartbeat Suppression Time
                                mem_r.res_time  <= tmp_dw;
                                -- NOTE: Last Bit denotes if this is Response or Suppression Delay
                                mem_r.res_time(1)(0)    <= '1';
                                
                                -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock)
                                -- Update Check Time
                                if (tmp_dw < check_time) then
                                    -- NOTE: Strictly speaking the check time may not EXACTLY represent the res_time (Since the last bit is ovverriden for a different functionality)
                                    --       Since the difference is at most 1/10^(-32) seconds, this will never practically impose any problem (since the time will most certainly have
                                    --       progressed beyond that difference from the check_time trigger to the actual res_time check).
                                    --       Nevertheless this has to be taken into account in testbenches that use "static" time.
                                    check_time_next <= tmp_dw;
                                end if;
                            else
                                -- Disable Suppression
                                mem_r.res_time  <= TIME_INVALID;
                            end if;
                            
                            -- Send ACKNACK
                            -- Increment Acknack Counter
                            count_next(ind)     <= count(ind) + 1;
                            stage_next          <= SEND_HEADER;
                            return_stage_next   <= SEND_ACKNACK;
                            cnt_next            <= 0;
                        when others =>
                            null;
                    end case;
                end if;
            when SEND_HEADER =>
                assert (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) severity FAILURE;
                
                -- Wait for Endpoint Data
                if (mem_op_done = '1') then
                    assert stable(clk, mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                    assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG)) severity FAILURE;
                    
                    -- Output FIFO Guard
                    if (full_ro = '0') then
                        wr_ro   <= '1';
                        
                        case (cnt) is
                            -- OUTPUT HEADER
                            -- Src IPv4 Address
                            when 0 =>
                                data_out_ro <= DEFAULT_IPv4_ADDRESS;
                                cnt_next    <= cnt + 1;
                            -- Dest IPv4 Address
                            when 1 =>
                                data_out_ro     <= mem_endpoint_data.ip_addr;
                                cnt_next        <= cnt + 1;
                            -- Src and Dest UDPv4 Ports
                            when 2 =>
                                data_out_ro     <= USER_IPv4_UNICAST_PORT & mem_endpoint_data.portn;
                                cnt_next        <= cnt + 1;
                            -- RTPS MESSAGE HEADER
                            when 3 =>
                                data_out_ro     <= PROTOCOL_RTPS;
                                cnt_next        <= cnt + 1;
                            when 4 =>
                                data_out_ro     <= PROTOCOLVERSION_2_4 & VENDORID;
                                cnt_next        <= cnt + 1;
                            when 5 =>
                                data_out_ro     <= GUIDPREFIX(0);
                                cnt_next        <= cnt + 1;
                            when 6 =>
                                data_out_ro     <= GUIDPREFIX(1);
                                cnt_next        <= cnt + 1;
                            when 7 =>
                                data_out_ro     <= GUIDPREFIX(2);
                                
                                -- Continue with respective RTPS Submessage
                                stage_next  <= return_stage;
                                cnt_next    <= 0;
                            when others =>
                                null;
                        end case;
                    end if;
                end if;
            when SEND_ACKNACK =>
                assert (stale_check = '1') severity FAILURE;
                assert (CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) severity FAILURE;
                
                -- Wait for Endpoint Data
                if (mem_op_done = '1') then
                    assert stable(clk, mem_endpoint_data.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                    assert stable(clk, mem_endpoint_data.i = ind and check_mask(mem_endpoint_data.field_flags, EMF_ENTITYID_FLAG or EMF_NEXT_SEQ_NR_FLAG)) severity FAILURE;
                    
                    -- Output FIFO Guard
                    if (full_ro = '0') then
                        wr_ro   <= '1';
                        
                        case (cnt) is
                            -- ACKNACK RTPS SUBMESSAGE
                            -- RTPS Submessage Header
                            when 0 =>
                                data_out_ro     <= SID_ACKNACK & "00000010" & std_logic_vector(to_unsigned(28, SUBMESSAGE_LENGTH_WIDTH));
                                cnt_next        <= cnt + 1;
                            -- Reader Entity ID
                            when 1 =>
                                data_out_ro     <= ENTITYID_T(ind);
                                cnt_next        <= cnt + 1;
                            -- Writer Entity ID
                            when 2 =>
                                data_out_ro     <= mem_endpoint_data.guid(3);
                                cnt_next        <= cnt + 1;
                            -- Sequence Number Set (Bitmap Base 1/2)
                            when 3 =>
                                data_out_ro     <= std_logic_vector(mem_endpoint_data.next_seq_nr(0));
                                cnt_next        <= cnt + 1;
                            -- Sequence Number Set (Bitmap Base 2/2)
                            when 4 =>
                                data_out_ro     <= std_logic_vector(mem_endpoint_data.next_seq_nr(1));
                                cnt_next        <= cnt + 1;
                            -- Sequence Number Set (NumBits)
                            when 5 =>
                                data_out_ro     <= std_logic_vector(to_unsigned(CDR_LONG_WIDTH, CDR_LONG_WIDTH));
                                cnt_next        <= cnt + 1;
                            -- Sequence Number Set (Bitmap)
                            when 6 =>
                                -- NOTE: In order to avoid having to generate a variable sized bitmap, we always request the next 32 sequence numbers, even if they do not exist (yet)
                                -- XXX: Assumes correct implementation of the RTPS Protocol (i.e. Writer ignores requested SNs that do not exist)
                                data_out_ro     <= (others => '1');
                                cnt_next        <= cnt + 1;
                            -- Count
                            when 7 =>
                                data_out_ro         <= std_logic_vector(count(ind));
                                last_word_out_ro    <= '1';
                                
                                -- Continue Search
                                stage_next  <= ENDPOINT_STALE_CHECK;
                                cnt_next    <= 3; -- GET NEXT Endpoint
                            when others =>
                                null;
                        end case;
                    end if;
                end if;
            when SKIP_PARAMETER =>
                -- Consumed last word of Packet
                if (last_word_in_latch = '1' and last_word_in_user = '0') then
                    -- Reset Last Word In Latch
                    last_word_in_latch_next <= '0';
                    -- Continue parsing next Packet
                    stage_next              <= IDLE;
                    -- Reset Parameter End
                    parameter_end_next      <= (others => '1');
                -- End of Parameter
                elsif ((read_cnt & "00" ) >= parameter_end) then
                    -- Parse Next Parameter
                    -- NOTE: data_in_user is already showing the next parameter
                    stage_next          <= PROCESS_INLINE_QOS;
                    -- Reset Parameter End
                    parameter_end_next  <= (others => '1');
                -- Input FIFO Guard
                elsif (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    -- Skip-Read
                    rd_guard    := '1';
                end if;
            when SKIP_PACKET =>
                assert (is_meta = '0') severity FAILURE;
                
                -- Reset Parameter End
                parameter_end_next  <= (others => '1');
                
                -- Consumed last word of Packet
                if (last_word_in_latch = '1' and last_word_in_user = '0') then
                    -- Reset Last Word In Latch
                    last_word_in_latch_next <= '0';
                    -- DONE
                    stage_next              <= IDLE;
                -- Input FIFO Guard
                elsif (empty_user /= (empty_user'range => '1')) then
                    assert ((empty_user xor r_map) = (empty_user'range => '1')) severity FAILURE;
                    -- Skip-Read
                    rd_guard    := '1';
                end if;
            when SKIP_META_OPERATION =>
                assert (is_meta = '1') severity FAILURE;
                
                -- Consumed last word of Packet
                if (last_word_in_latch = '1' and last_word_in_meta = '0') then
                    -- Reset Last Word In Latch
                    last_word_in_latch_next <= '0';
                    -- DONE
                    stage_next  <= IDLE;
                -- Input Guard
                elsif (empty_meta /= (empty_meta'range => '1')) then
                    assert ((empty_meta xor r_map) = (empty_meta'range => '1')) severity FAILURE;
                    -- Skip-Read
                    rd_meta <= '1';
                end if;
        end case;
        
        -- OVERREAD GUARD
        -- Read outside of packet Length
        -- NOTE: If the Packet Length is smaller than expected there will be a read from input FIFO while
        --       the Packet Length has been reached and will be caught by this clause.
        --       The SKIP_PACKET clause prevents a read signal from occuring in this situation, and thus prevents from entering this state.
        if ((last_word_in_latch = '1' and last_word_in_user = '0') and rd_guard = '1') then
            -- Force rd_sig low
            rd_sig                  <= '0';
            -- Continue parsing next Packet
            stage_next              <= IDLE;
            -- Reset Last Word In Latch
            last_word_in_latch_next <= '0';
            -- Reset Parameter End
            parameter_end_next      <= (others => '1');
        -- Read outside of Parameter Length
        -- NOTE: If the Parameter Length is smaller than expected for a particular parameter, there will be a read from input FIFO while
        --       the Parameter Length has been reached and will be caught by this clause.
        --       The SKIP_PARAMETER clause prevents a read signal from occuring in this situation, and thus prevents from entering this state.
        elsif ((read_cnt & "00") >= parameter_end and rd_guard = '1') then
            -- Force rd_sig low
            rd_sig              <= '0';
            -- Invalid Parameter Length, Skip Packet
            stage_next          <= SKIP_PACKET;
            -- Reset Parameter End
            parameter_end_next  <= (others => '1');
        -- DEFAULT
        else
            rd_sig  <= rd_guard;
        end if;
    end process;
    
    empty_head_sig_prc : process(all)
    begin
        for i in 0 to NUM_READERS-1 loop
            empty_head_sig(i)   <= to_integer(mem_empty_head(i));
        end loop;
    end process;
    
    -- *Memory State Machine*
    -- STATE                DESCRIPTION
    -- IDLE                 Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations
    -- SEARCH_ENDPOINT      See Memory OPCODE Description
    -- GET_ENDPOINT_DATA    Latch specified Endpoint Data for use by main FSM
    -- INSERT_ENDPOINT      See Memory OPCODE Description
    -- UPDATE_ENDPOINT      See Memory OPCODE Description
    -- REMOVE_ENDPOINT      See Memory OPCODE Description
    -- GET_NEXT_ENDPOINT    See Memory OPCODE Description
    -- RESET_MEMORY         Reset Endpoint Memory to Empty State
    mem_ctrl_prc : process(all)
    begin
        -- DEFAULT Registered
        mem_stage_next                  <= mem_stage;
        mem_addr_base_next              <= mem_addr_base;
        mem_empty_head_next             <= mem_empty_head;
        mem_occupied_head_next          <= mem_occupied_head;
        mem_cnt_next                    <= mem_cnt;
        mem_addr_latch_next             <= mem_addr_latch;
        mem_endpoint_data_next          <= mem_endpoint_data;
        mem_endpoint_latch_data_next    <= mem_endpoint_latch_data;
        -- DEFAULT Unregistered
        mem_addr        <= (others => '0');
        mem_write_data  <= (others => '0');
        mem_read        <= '0';
        mem_valid_in    <= '0';
        mem_ready_out   <= '0';
        mem_op_done     <= '0';
        abort_read      <= '0';
        multi_w         <= '0';
        
        
        case (mem_stage) is
            when IDLE =>
                mem_op_done             <= '1';
                
                if (mem_op_start = '1') then
                    -- Latch Signals needed for Mermory Operation
                    mem_endpoint_latch_data_next    <= mem_r;
                    
                    case(mem_opcode) is
                        when SEARCH_ENDPOINT =>
                            mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                            mem_endpoint_data_next.i    <= mem_r.i;
                            
                            if (mem_occupied_head(mem_r.i) /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_addr_base_next  <= mem_occupied_head(mem_r.i);
                                mem_stage_next      <= SEARCH_ENDPOINT;
                                mem_cnt_next        <= 0;
                            end if;
                        when INSERT_ENDPOINT =>
                            assert (mem_empty_head(mem_r.i) /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE;
                            
                            mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                            mem_endpoint_data_next.i    <= mem_r.i;
                            
                            mem_endpoint_data_next.addr <= mem_empty_head(mem_r.i);
                            mem_addr_base_next          <= mem_empty_head(mem_r.i);
                            mem_stage_next              <= INSERT_ENDPOINT;
                            mem_cnt_next                <= 0;
                        when UPDATE_ENDPOINT =>
                            if (mem_r.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                                mem_endpoint_data_next.i    <= mem_r.i;
                            else
                                if (mem_r.i /= mem_endpoint_data.i or mem_r.addr /= mem_endpoint_data.addr) then
                                    mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                                    mem_endpoint_data_next.i    <= mem_r.i;
                                end if;
                                
                                mem_endpoint_data_next.addr <= mem_r.addr;
                                mem_addr_base_next          <= mem_r.addr;
                                mem_stage_next              <= UPDATE_ENDPOINT;
                                if check_mask(mem_r.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 0;
                                elsif check_mask(mem_r.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 1;
                                elsif check_mask(mem_r.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 2;
                                elsif check_mask(mem_r.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 4;
                                elsif check_mask(mem_r.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                    mem_cnt_next    <= 6;
                                elsif check_mask(mem_r.field_flags,EMF_RES_TIME_FLAG) then
                                    mem_cnt_next    <= 8;
                                else
                                    -- DONE
                                    mem_stage_next  <= IDLE;
                                end if;
                            end if;
                        when REMOVE_ENDPOINT =>
                            mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                            mem_endpoint_data_next.i    <= mem_r.i;
                            
                            if (mem_r.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_addr_base_next  <= mem_r.addr;
                                mem_stage_next      <= REMOVE_ENDPOINT;
                                mem_cnt_next        <= 0;
                            end if;
                        when GET_NEXT_ENDPOINT =>
                            mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                            mem_endpoint_data_next.i    <= mem_r.i;
                            
                            if (mem_r.addr /= ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_addr_base_next  <= mem_r.addr;
                                mem_stage_next      <= GET_NEXT_ENDPOINT;
                                mem_cnt_next        <= 0;
                            end if;
                        when GET_ENDPOINT =>
                            if (mem_r.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                                mem_endpoint_data_next.i    <= mem_r.i;
                            else
                                if (mem_r.i /= mem_endpoint_data.i or mem_r.addr /= mem_endpoint_data.addr) then
                                    mem_endpoint_data_next  <= ZERO_ENDPOINT_DATA;
                                    mem_endpoint_data_next.i    <= mem_r.i;
                                end if;
                                
                                mem_endpoint_data_next.addr <= mem_r.addr;
                                mem_addr_base_next          <= mem_r.addr;
                                mem_stage_next              <= GET_ENDPOINT_DATA;
                                if check_mask(mem_r.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 0;
                                elsif check_mask(mem_r.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 1;
                                elsif check_mask(mem_r.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 4;
                                elsif check_mask(mem_r.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 5;
                                elsif check_mask(mem_r.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 6;
                                elsif check_mask(mem_r.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 8;
                                elsif check_mask(mem_r.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                    mem_cnt_next    <= 10;
                                elsif check_mask(mem_r.field_flags,EMF_RES_TIME_FLAG) then
                                    mem_cnt_next    <= 12;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                    mem_cnt_next    <= 14;
                                else
                                    -- DONE
                                    mem_stage_next  <= IDLE;
                                end if;
                            end if;
                        when others =>
                            null;
                    end case;
                end if;
            when SEARCH_ENDPOINT =>
                case (mem_cnt) is
                    -- GET Entity ID
                    when 0 =>
                        mem_addr        <= mem_addr_base + EMF_ENTITYID_OFFSET;
                        mem_read        <= '1';
                        mem_valid_in    <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET GUID Prefix 1/3
                    when 1 =>
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET;
                        mem_read        <= '1';
                        mem_valid_in    <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET GUID Prefix 2/3
                    when 2 =>
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 1;
                        mem_read        <= '1';
                        mem_valid_in    <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET GUID Prefix 3/3
                    when 3 =>
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2;
                        mem_read        <= '1';
                        mem_valid_in    <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Entity ID
                    when 4 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            -- No Match
                            if (mem_read_data /= mem_endpoint_latch_data.guid(3)) then
                                abort_read  <= '1';
                                mem_cnt_next    <= 8; -- GET Next Addr
                            else
                                mem_cnt_next    <= mem_cnt + 1;
                            end if;
                        end if;
                    -- READ GUID Prefix 1/3
                    when 5 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            -- No  Match
                            if (mem_read_data /= mem_endpoint_latch_data.guid(0)) then
                                abort_read  <= '1';
                                mem_cnt_next    <= 8; -- GET Next Addr
                            else
                                mem_cnt_next    <= mem_cnt + 1;
                            end if;
                        end if;
                    -- READ GUID Prefix 2/3
                    when 6 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            -- No  Match
                            if (mem_read_data /= mem_endpoint_latch_data.guid(1)) then
                                abort_read  <= '1';
                                mem_cnt_next    <= 8; -- GET Next Addr
                            else
                                mem_cnt_next    <= mem_cnt + 1;
                            end if;
                        end if;
                    -- READ GUID Prefix 3/3
                    when 7 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            -- No  Match
                            if (mem_read_data /= mem_endpoint_latch_data.guid(2)) then
                                abort_read  <= '1';
                                mem_cnt_next    <= 8; -- GET Next Addr
                            -- Match
                            else
                                mem_endpoint_data_next.addr <= mem_addr_base;
                                -- Fetch Endpoint Data
                                mem_stage_next  <= GET_ENDPOINT_DATA;
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 0;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 1;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 4;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 5;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 6;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 8;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                    mem_cnt_next    <= 10;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                    mem_cnt_next    <= 12;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                    mem_cnt_next    <= 14;
                                else
                                    -- DONE
                                    mem_stage_next  <= IDLE;
                                end if;
                            end if;
                        end if;
                    -- GET Next Addr
                    when 8 =>
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_read        <= '1';
                        mem_valid_in    <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Next Addr
                    when 9 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            -- No more Endpoints
                            if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_endpoint_data_next.addr <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match
                                -- DONE
                                mem_stage_next      <= IDLE;
                            else
                                -- Continue
                                mem_addr_base_next  <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                                mem_cnt_next        <= 0;
                            end if;
                        end if;
                    when others =>
                        null;
                end case;
            when GET_ENDPOINT_DATA =>
                
                case (mem_cnt) is
                    -- GET Entity ID
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_ENTITYID_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                mem_cnt_next    <= 1;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                mem_cnt_next    <= 4;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 5;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 8;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                mem_cnt_next    <= 15;
                            end if;
                        end if;
                    -- GET GUID Prefix 1/3
                    when 1 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET GUID Prefix 2/3
                    when 2 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 1;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET GUID Prefix 3/3
                    when 3 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                mem_cnt_next    <= 4;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 5;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 8;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                else
                                    mem_cnt_next    <= 16;
                                end if;
                            end if;
                        end if;
                    -- GET IPv4 Address
                    when 4 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 5;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 8;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                else
                                    mem_cnt_next    <= 19;
                                end if;
                            end if;
                        end if;
                    -- GET UDP Port/ Flags
                    when 5 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_UDP_PORT_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 8;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 19;
                                else
                                    mem_cnt_next    <= 20;
                                end if;
                            end if;
                        end if;
                    -- GET Next Sequence Number 1/2
                    when 6 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET Next Sequence Number 2/2
                    when 7 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET + 1;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 8;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 19;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 20;
                                else
                                    mem_cnt_next    <= 21;
                                end if;
                            end if;
                        end if;
                    -- GET Lease Deadline 1/2
                    when 8 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET Lease Deadline 2/2
                    when 9 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 10;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 19;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 20;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 21;
                                else
                                    mem_cnt_next    <= 23;
                                end if;
                            end if;
                        end if;
                    -- GET Lifespan Duration 1/2
                    when 10 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET Lifespan Duration 2/2
                    when 11 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET + 1;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 12;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 19;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 20;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 21;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 23;
                                else
                                    mem_cnt_next    <= 25;
                                end if;
                            end if;
                        end if;
                    -- GET Response Time 1/2
                    when 12 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET Response Time 2/2
                    when 13 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 14;
                            else
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 15;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 16;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 19;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 20;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 21;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 23;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                    mem_cnt_next    <= 25;
                                else
                                    mem_cnt_next    <= 27;
                                end if;
                            end if;
                        end if;
                    -- GET Writer ID
                    when 14 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_WRITER_ID_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                mem_cnt_next    <= 15;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                mem_cnt_next    <= 16;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                mem_cnt_next    <= 19;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 20;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 21;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            else
                                mem_cnt_next    <= 29;
                            end if;
                        end if;
                    -- READ Entity ID
                    when 15 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.guid(3)  <= mem_read_data;
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_ENTITYID_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                mem_cnt_next    <= 16;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                mem_cnt_next    <= 19;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 20;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 21;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ GUID Prefix 1/3
                    when 16 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.guid(0)  <= mem_read_data;
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ GUID Prefix 2/3
                    when 17 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.guid(1)  <= mem_read_data;
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ GUID Prefix 3/3
                    when 18 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.guid(2)  <= mem_read_data;
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_GUIDPREFIX_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                mem_cnt_next    <= 19;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 20;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 21;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ IPv4 Address
                    when 19 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.ip_addr     <= mem_read_data;
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_IPV4_ADDR_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 20;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 21;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ UDP Port
                    when 20 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.portn    <= mem_read_data(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH);
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_UDP_PORT_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 21;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ Next Sequence Number 1/2
                    when 21 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.next_seq_nr(0)   <= unsigned(mem_read_data);
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Next Sequence Number 2/2
                    when 22 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.next_seq_nr(1)   <= unsigned(mem_read_data);
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_NEXT_SEQ_NR_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 23;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ Lease Deadline 1/2
                    when 23 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.lease_deadline(0)    <= unsigned(mem_read_data);
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Lease Deadline 2/2
                    when 24 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.lease_deadline(1)    <= unsigned(mem_read_data);
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LEASE_DEADLINE_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 25;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ Lifespan Duration 1/2
                    when 25 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.lifespan(0)  <= unsigned(mem_read_data);
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Lifespan Duration 2/2
                    when 26 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.lifespan(1)  <= unsigned(mem_read_data);
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LIFESPAN_DURATION_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 27;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ Response Time 1/2
                    when 27 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.res_time(0)  <= unsigned(mem_read_data);
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Response Time 2/2
                    when 28 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.res_time(1)  <= unsigned(mem_read_data);
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_RES_TIME_FLAG;
                            
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                mem_cnt_next    <= 29;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- READ Writer ID
                    when 29 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_endpoint_data_next.writer_id    <= to_integer(unsigned(mem_read_data));
                            mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_WRITER_ID_FLAG;
                            
                            -- DONE
                            mem_stage_next  <= IDLE;
                        end if;
                    when others =>
                        null;
                end case;
            when INSERT_ENDPOINT =>
                case (mem_cnt) is
                    -- GET Next Addr
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_read        <= '1';
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Entity ID
                    when 1 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_ENTITYID_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.guid(3);
                        mem_endpoint_data_next.guid(3)  <= mem_endpoint_latch_data.guid(3);
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_ENTITYID_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET GUID Prefix 1/3
                    when 2 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.guid(0);
                        mem_endpoint_data_next.guid(0)  <= mem_endpoint_latch_data.guid(0);
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET GUID Prefix 2/3
                    when 3 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 1;
                        mem_write_data  <= mem_endpoint_latch_data.guid(1);
                        mem_endpoint_data_next.guid(1)  <= mem_endpoint_latch_data.guid(1);
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET GUID Prefix 3/3
                    when 4 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2;
                        mem_write_data  <= mem_endpoint_latch_data.guid(2);
                        mem_endpoint_data_next.guid(2)  <= mem_endpoint_latch_data.guid(2);
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_GUIDPREFIX_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET IPv4 Address
                    when 5 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.ip_addr;
                        mem_endpoint_data_next.ip_addr <= mem_endpoint_latch_data.ip_addr;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_IPV4_ADDR_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET UDPv4 Ports
                    when 6 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_UDP_PORT_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.portn & (0 to (mem_write_data'length-mem_endpoint_latch_data.portn'length-1) => '0');
                        mem_endpoint_data_next.portn    <= mem_endpoint_latch_data.portn;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_UDP_PORT_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Next Sequence Number 1/2
                    when 7 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.next_seq_nr(0));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Next Sequence Number 2/2
                    when 8 =>
                        mem_write_data  <= (others => '0');
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.next_seq_nr(1));
                        mem_endpoint_data_next.next_seq_nr  <= mem_endpoint_latch_data.next_seq_nr;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_NEXT_SEQ_NR_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Lease Deadline 1/2
                    when 9 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(0));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Lease Deadline 2/2
                    when 10 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(1));
                        mem_endpoint_data_next.lease_deadline   <= mem_endpoint_latch_data.lease_deadline;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LEASE_DEADLINE_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Lifespan Duration 1/2
                    when 11 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lifespan(0));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Lifespan Duration 2/2
                    when 12 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lifespan(1));
                        mem_endpoint_data_next.lifespan <= mem_endpoint_latch_data.lifespan;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LIFESPAN_DURATION_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Response Time 1/2
                    when 13 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET;
                        mem_write_data  <= std_logic_vector(TIME_INVALID(0));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Response Time 2/2
                    when 14 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(TIME_INVALID(1));
                        mem_endpoint_data_next.res_time <= TIME_INVALID;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_RES_TIME_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Next Addr
                    when 15 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_occupied_head(mem_endpoint_latch_data.i),WORD_WIDTH));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Prev Addr
                    when 16 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_PREV_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(ENDPOINT_MEMORY_MAX_ADDRESS,WORD_WIDTH));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if (mem_occupied_head(mem_endpoint_latch_data.i) = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_cnt_next    <= mem_cnt + 2; -- Skip Next Step
                            else
                                mem_cnt_next    <= mem_cnt + 1;
                            end if;
                        end if;
                    -- SET Prev Addr (Occupied Head)
                    when 17 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_occupied_head(mem_endpoint_latch_data.i) + EMF_PREV_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_addr_base,WORD_WIDTH));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Next Addr
                    when 18 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            
                            -- Update List Heads
                            mem_empty_head_next(mem_endpoint_latch_data.i)      <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                            mem_occupied_head_next(mem_endpoint_latch_data.i)   <= mem_addr_base;
                            
                            -- DONE
                            mem_stage_next  <= IDLE;
                        end if;
                    when others => 
                        null;
                end case;
            when UPDATE_ENDPOINT =>
                case (mem_cnt) is
                    -- IPv4 Address
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.ip_addr;
                        mem_endpoint_data_next.ip_addr <= mem_endpoint_latch_data.ip_addr;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_IPV4_ADDR_FLAG;
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                mem_cnt_next    <= 1;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 2;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 4;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 8;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- UDPv4 Ports
                    when 1 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_UDP_PORT_OFFSET;
                        mem_write_data  <= mem_endpoint_latch_data.portn & (0 to (mem_write_data'length-mem_endpoint_latch_data.portn'length-1) => '0');
                        mem_endpoint_data_next.portn    <= mem_endpoint_latch_data.portn;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_UDP_PORT_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                mem_cnt_next    <= 2;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 4;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 8;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- Next Sequence Number 1/2
                    when 2 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.next_seq_nr(0));
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- Next Sequence Number 2/2
                    when 3 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_SEQ_NR_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.next_seq_nr(1));
                        mem_endpoint_data_next.next_seq_nr  <= mem_endpoint_latch_data.next_seq_nr;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_NEXT_SEQ_NR_FLAG;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                mem_cnt_next    <= 4;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 8;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- Lease Deadline 1/2
                    when 4 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(0));
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- Lease Deadline 2/2
                    when 5 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(1));
                        mem_endpoint_data_next.lease_deadline   <= mem_endpoint_latch_data.lease_deadline;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LEASE_DEADLINE_FLAG;
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                mem_cnt_next    <= 6;
                            elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 8;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- Lifespan Duration 1/2
                    when 6 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lifespan(0));
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- Lifespan Duration 2/2
                    when 7 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_LIFESPAN_DURATION_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.lifespan(1));
                        mem_endpoint_data_next.lifespan <= mem_endpoint_latch_data.lifespan;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_LIFESPAN_DURATION_FLAG;
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            if check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                mem_cnt_next    <= 8;
                            else
                                -- DONE
                                mem_stage_next  <= IDLE;
                            end if;
                        end if;
                    -- Response Time 1/2
                    when 8 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.res_time(0));
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- Response Time 2/2
                    when 9 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
                        mem_write_data  <= std_logic_vector(mem_endpoint_latch_data.res_time(1));
                        mem_endpoint_data_next.res_time <= mem_endpoint_latch_data.res_time;
                        mem_endpoint_data_next.field_flags  <= mem_endpoint_data.field_flags or EMF_RES_TIME_FLAG;
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1')  then
                            -- DONE
                            mem_stage_next  <= IDLE;
                        end if;
                    when others =>
                        null;
                end case;
            when REMOVE_ENDPOINT =>
                case (mem_cnt) is
                    -- GET Next Addr
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- GET Prev Addr
                    when 1 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_PREV_ADDR_OFFSET;
                        mem_read        <= '1';
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Next Addr
                    when 2 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_empty_head(mem_endpoint_latch_data.i),WORD_WIDTH));
                        
                        if (mem_ready_in = '1') then
                            -- Set New Empty Head
                            mem_empty_head_next(mem_endpoint_latch_data.i)  <= mem_addr_base;
                            
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Next Addr
                    when 3 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            mem_addr_latch_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Prev Addr
                    when 4 =>
                        mem_ready_out   <= '1';
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            if (mem_addr_latch = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                    -- RESET Occupied List Head
                                    mem_occupied_head_next(mem_endpoint_latch_data.i)   <= ENDPOINT_MEMORY_MAX_ADDRESS;
                                    
                                    mem_endpoint_data_next.addr <= ENDPOINT_MEMORY_MAX_ADDRESS;
                                    -- DONE
                                    mem_stage_next  <= IDLE;
                                else
                                    mem_addr_base_next  <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                                    mem_cnt_next        <= mem_cnt + 2; -- Skip Next Step
                                end if;
                            else
                                mem_addr_base_next  <= mem_addr_latch;
                                mem_addr_latch_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                                mem_cnt_next        <= mem_cnt + 1;
                            end if;
                        end if;
                    -- SET Prev Addr (Next Slot)
                    when 5 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_PREV_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH));
                        
                        if (mem_ready_in = '1') then
                            if (mem_addr_latch = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                -- Set New Occupied List Head
                                mem_occupied_head_next(mem_endpoint_latch_data.i)   <= mem_addr_base;
                                
                                mem_endpoint_data_next.addr <= mem_addr_base;
                                -- DONE
                                mem_stage_next  <= IDLE;
                            else
                                mem_addr_base_next  <= mem_addr_latch;
                                mem_addr_latch_next <= mem_addr_base;
                                mem_cnt_next        <= mem_cnt + 1;
                            end if;
                        end if;
                    -- SET Next Addr (Previous Slot)
                    when 6 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH));
                        
                        if (mem_ready_in = '1') then
                            mem_endpoint_data_next.addr <= mem_addr_latch;
                            -- DONE
                            mem_stage_next  <= IDLE;
                        end if;
                    when others => 
                        null;
                end case;
            when GET_NEXT_ENDPOINT =>
                case (mem_cnt) is
                    -- GET Next Addr
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_read        <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- READ Next Addr
                    when 1 =>
                        mem_ready_out   <= '1';
                        
                        -- Memory Flow Control Guard
                        if (mem_valid_out = '1') then
                            if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then
                                mem_endpoint_data_next.addr <= ENDPOINT_MEMORY_MAX_ADDRESS;
                                -- DONE
                                mem_stage_next  <= IDLE;
                            else
                                mem_endpoint_data_next.addr <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                                
                                -- Fetch Endpoint Data
                                mem_addr_base_next          <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH);
                                mem_stage_next  <= GET_ENDPOINT_DATA;
                                if check_mask(mem_endpoint_latch_data.field_flags,EMF_ENTITYID_FLAG) then
                                    mem_cnt_next    <= 0;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_GUIDPREFIX_FLAG) then
                                    mem_cnt_next    <= 1;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_IPV4_ADDR_FLAG) then
                                    mem_cnt_next    <= 4;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_UDP_PORT_FLAG) then
                                    mem_cnt_next    <= 5;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_NEXT_SEQ_NR_FLAG) then
                                    mem_cnt_next    <= 6;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LEASE_DEADLINE_FLAG) then
                                    mem_cnt_next    <= 8;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_LIFESPAN_DURATION_FLAG) then
                                    mem_cnt_next    <= 10;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_RES_TIME_FLAG) then
                                    mem_cnt_next    <= 12;
                                elsif check_mask(mem_endpoint_latch_data.field_flags,EMF_WRITER_ID_FLAG) then
                                    mem_cnt_next    <= 14;
                                else
                                    -- DONE
                                    mem_stage_next  <= IDLE;
                                end if;
                            end if;
                        end if;
                    when others =>
                        null;
                end case;
            when RESET_MEMORY =>
                multi_w <= '1';
                case (mem_cnt) is
                    -- SET Writer ID
                    when 0 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_WRITER_ID_OFFSET;
                        mem_write_data  <= std_logic_vector(to_unsigned(mem_endpoint_data.writer_id,WORD_WIDTH));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                            mem_endpoint_data_next.writer_id    <= mem_endpoint_data.writer_id + 1;
                        end if;
                    -- SET Next Pointer
                    when 1 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_NEXT_ADDR_OFFSET;
                        if (mem_addr_base = MAX_ENDPOINT_ADDRESS) then
                            mem_write_data  <= std_logic_vector(resize(ENDPOINT_MEMORY_MAX_ADDRESS,WORD_WIDTH));
                        else
                            mem_write_data  <= std_logic_vector(resize(mem_addr_base + ENDPOINT_FRAME_SIZE,WORD_WIDTH));
                        end if;
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            mem_cnt_next    <= mem_cnt + 1;
                        end if;
                    -- SET Previous Pointer
                    when 2 =>
                        mem_valid_in    <= '1';
                        mem_addr        <= mem_addr_base + EMF_PREV_ADDR_OFFSET;
                        mem_write_data  <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH));
                        
                        -- Memory Flow Control Guard
                        if (mem_ready_in = '1') then
                            if (mem_addr_base = MAX_ENDPOINT_ADDRESS) then
                                -- Initialize Empty and Occupied Heads
                                mem_empty_head_next     <= (others => FIRST_ENDPOINT_ADDRESS);
                                mem_occupied_head_next  <= (others => ENDPOINT_MEMORY_MAX_ADDRESS);
                                
                                -- Reset
                                mem_endpoint_data_next.writer_id    <= 0;
                                
                                -- DONE
                                mem_stage_next  <= IDLE;
                            else
                                mem_addr_latch_next <= mem_addr_base;
                                mem_addr_base_next  <= mem_addr_base + ENDPOINT_FRAME_SIZE;
                                mem_cnt_next        <= 0;
                            end if;
                        end if;
                    when others =>
                        null;
                end case;
        end case;
    end process;
    
    -- Process responsible for counting read words
    -- This process uses the actual FIFO read signals to determine reads
    word_counter_prc : process(clk, reset)
    begin
        if rising_edge(clk) then
            -- Reset Read counter
            if (reset = '1' or reset_read_cnt = '1') then
                read_cnt    <= (others => '0');
            -- Increment read counter each time rd_sig is high
            elsif (rd_sig = '1') then
                read_cnt    <= read_cnt + 1;
            end if;
        end if;
    end process;
    
    sync_prc : process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                stage                   <= IDLE;
                return_stage            <= IDLE;
                mem_stage               <= RESET_MEMORY;
                seq_nr                  <= SEQUENCENUMBER_UNKNOWN;
                next_seq_nr             <= SEQUENCENUMBER_UNKNOWN;
                sn_latch_1              <= SEQUENCENUMBER_UNKNOWN;
                sn_latch_2              <= SEQUENCENUMBER_UNKNOWN;
                sn_latch_3              <= SEQUENCENUMBER_UNKNOWN;
                ts                      <= TIME_INVALID;
                check_time              <= TIME_INVALID;
                lifespan                <= TIME_INVALID;
                guid                    <= GUID_UNKNOWN;
                addr                    <= IPv4_ADDRESS_INVALID;
                portn                   <= UDP_PORT_INVALID;
                mem_endpoint_data       <= ZERO_ENDPOINT_DATA;
                mem_endpoint_latch_data <= ZERO_ENDPOINT_DATA;
                cnt                     <= 0;
                cnt2                    <= 0;
                bitmap_pos              <= 0;
                mem_cnt                 <= 0;
                ind                     <= 0;
                is_meta                 <= '0';
                key_hash_rcvd           <= '0';
                last_word_in_latch      <= '0';
                stale_check             <= '0';
                r_map                   <= (others => '0');
                parameter_end           <= (others => '1');
                bitmap_cnt              <= (others => '0');
                meta_opcode             <= EMO_NOP;
                status_info             <= (others => '0');
                mem_addr_base           <= FIRST_ENDPOINT_ADDRESS;
                mem_empty_head          <= (others => ENDPOINT_MEMORY_MAX_ADDRESS);
                mem_occupied_head       <= (others => ENDPOINT_MEMORY_MAX_ADDRESS);
                mem_addr_latch          <= ENDPOINT_MEMORY_MAX_ADDRESS;
                payload_addr_base       <= (others => '0');
                payload_max_addr        <= (others => '0');
                flags                   <= (others => '0');
                opcode                  <= SID_PAD;
                count                   <= (others => (others => '0'));
                key_hash                <= KEY_HASH_NIL;
                bitmap_latch            <= (others => (others => '0'));
            else
                stage                   <= stage_next;
                return_stage            <= return_stage_next;
                mem_stage               <= mem_stage_next;
                seq_nr                  <= seq_nr_next;
                next_seq_nr             <= next_seq_nr_next;
                sn_latch_1              <= sn_latch_1_next;
                sn_latch_2              <= sn_latch_2_next;
                sn_latch_3              <= sn_latch_3_next;
                ts                      <= ts_next;
                check_time              <= check_time_next;
                lifespan                <= lifespan_next;
                guid                    <= guid_next;
                addr                    <= addr_next;
                portn                   <= portn_next;
                mem_endpoint_data       <= mem_endpoint_data_next;
                mem_endpoint_latch_data <= mem_endpoint_latch_data_next;
                cnt                     <= cnt_next;
                cnt2                    <= cnt2_next;
                bitmap_pos              <= bitmap_pos_next;
                mem_cnt                 <= mem_cnt_next;
                ind                     <= ind_next;
                is_meta                 <= is_meta_next;
                key_hash_rcvd           <= key_hash_rcvd_next;
                last_word_in_latch      <= last_word_in_latch_next;
                parameter_end           <= parameter_end_next;
                bitmap_cnt              <= bitmap_cnt_next;
                stale_check             <= stale_check_next;
                r_map                   <= r_map_next;
                meta_opcode             <= meta_opcode_next;
                status_info             <= status_info_next;
                mem_addr_base           <= mem_addr_base_next;
                mem_empty_head          <= mem_empty_head_next;
                mem_occupied_head       <= mem_occupied_head_next;
                mem_addr_latch          <= mem_addr_latch_next;
                payload_addr_base       <= payload_addr_base_next;
                payload_max_addr        <= payload_max_addr_next;
                flags                   <= flags_next;
                opcode                  <= opcode_next;
                count                   <= count_next;
                key_hash                <= key_hash_next;
                bitmap_latch            <= bitmap_latch_next;
            end if;
        end if;
    end process;
end architecture;
