library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library osvvm; -- Utility Library
context osvvm.OsvvmContext;

use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;

-- This testbench tests the metatraffic operation behaviour of the RTPS Writer. (Remote Endpoint matching and Memory behaviour)
-- This testbench is using external names to access the memory of the rtps_reader directly and check the contents at the supposed locations.
-- This testbench covers following:
--  * Mathing Endpoint
--  * Memory Full Behaviour
--  * Unmatching Endpoint
--  * Unmatching Participant
--  * Updating previously matched Endpoint
--  * Unknown Metatraffic Operation

entity L0_rtps_writer_test1 is
end entity;

architecture testbench of L0_rtps_writer_test1 is
    
    -- *CONSTANT DECLARATION*
    constant MAX_REMOTE_ENDPOINTS   : natural := 3;
    constant NUM_WRITERS            : natural := 2;
    
    impure function gen_test_config return CONFIG_ARRAY_TYPE is
        variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
    begin
        -- vrn
        ret(0).RELIABILITY_QOS              := RELIABLE_RELIABILITY_QOS;
        ret(0).LIVELINESS_QOS               := MANUAL_BY_TOPIC_LIVELINESS_QOS;
        ret(0).DURABILITY_QOS               := VOLATILE_DURABILITY_QOS;
        ret(0).DESTINATION_ORDER_QOS        := BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(0).ACKNACK_RESPONSE_DELAY       := DURATION_ZERO;
        ret(0).ACKNACK_SUPPRESSION_DELAY    := DURATION_ZERO;
        ret(0).LEASE_DURATION               := DURATION_INFINITE;
        ret(0).HEARTBEAT_PERIOD             := DURATION_INFINITE;
        ret(0).WITH_KEY                     := FALSE;
        ret(0).PUSH_MODE                    := FALSE;
        -- vbk
        ret(1).RELIABILITY_QOS              := BEST_EFFORT_RELIABILITY_QOS;
        ret(1).LIVELINESS_QOS               := AUTOMATIC_LIVELINESS_QOS;
        ret(1).DURABILITY_QOS               := VOLATILE_DURABILITY_QOS;
        ret(1).DESTINATION_ORDER_QOS        := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(1).ACKNACK_RESPONSE_DELAY       := DURATION_ZERO;
        ret(1).ACKNACK_SUPPRESSION_DELAY    := DURATION_ZERO;
        ret(1).LEASE_DURATION               := DURATION_INFINITE;
        ret(1).HEARTBEAT_PERIOD             := DURATION_INFINITE;
        ret(1).WITH_KEY                     := TRUE;
        ret(1).PUSH_MODE                    := TRUE;
        
        return ret;
    end function;
    constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
    
    -- *TYPE DECLARATION*
    type TEST_STAGE_TYPE is (IDLE, BUSY);
    type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*READER_ENDPOINT_FRAME_SIZE)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
    type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of natural;
    
    -- *SIGNAL DECLARATION*
    signal clk, last_word_in_meta, rd_meta : std_logic := '0';
    signal empty_user, empty_meta, start_hc, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
    signal reset : std_logic := '1';
    signal data_in_meta : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
    signal stim_stage : TEST_STAGE_TYPE := IDLE;
    shared variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
    signal packet_sent : std_logic := '0';
    signal cnt_stim : natural := 0;
    signal start : std_logic := '0';
    shared variable SB0_mem, SB1_mem : work.ScoreBoardPkg_MemoryTest.ScoreBoardPType;
    signal stim_done, mem_check_done, test_done : std_logic := '0';
    
    -- *FUNCTION DECLARATION*
    procedure wait_on_sig(signal sig : std_logic) is
    begin
        if (sig /= '1') then
            wait on sig until sig = '1';
        end if;
    end procedure;
begin

    -- Unit Under Test
    uut : entity work.rtps_writer(arch)
        generic map (
            NUM_WRITERS             => NUM_WRITERS,
            CONFIG_ARRAY            => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG),
            ENTITYID                => (0 => x"61d32d03", 1 => x"3c1f1902"),
            INLINE_QOS              => (0 to NUM_WRITERS-1 => gen_inline_qos(NUM_READERS+7)),
            MAX_REMOTE_ENDPOINTS    => MAX_REMOTE_ENDPOINTS
        )
        port map (
            clk                     => clk,
            reset                   => reset,
            time                    => TIME_ZERO,
            empty_user              => (others => '1'),
            rd_user                 => open,
            data_in_user            => (others => '0'),
            last_word_in_user       => '0',
            empty_meta              => empty_meta or (empty_meta'range => packet_sent),
            rd_meta                 => rd_meta,
            data_in_meta            => data_in_meta,
            last_word_in_meta       => last_word_in_meta,
            alive_sig               => open,
            wr_ro                   => open,
            full_ro                 => '0',
            last_word_out_ro        => open,
            data_out_ro             => open,
            liveliness_assertion    => (others => '0'),
            data_available          => (others => '0'),
            start_hc                => start_hc,
            opcode_hc               => open,
            ack_hc                  => (others => '1'),
            seq_nr_hc               => open,
            done_hc                 => (others => '1'),
            ret_hc                  => (others => OK),
            get_data_hc             => open,
            data_in_hc              => (others => (others => '0')),
            valid_in_hc             => (others => '0'),
            ready_in_hc             => open,
            last_word_in_hc         => (others => '0'),
            cc_instance_handle      => (others => HANDLE_NIL),
            cc_kind                 => (others => ALIVE),
            cc_source_timestamp     => (others => TIME_INVALID),
            cc_seq_nr               => (others => SEQUENCENUMBER_UNKNOWN)
        );
    
    stimulus_prc : process
        variable RV                         : RandomPType;
        variable p0, p1, participant        : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA;
        variable e0, e1, e2, e3, endpoint   : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA;
        
        alias empty_head is <<signal uut.empty_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE>>;
        
        -- Wrapper to use procedure as function
        impure function gen_rand_loc_2 return LOCATOR_TYPE is
            variable ret : LOCATOR_TYPE := EMPTY_LOCATOR;
        begin
            gen_rand_loc(RV, ret);
            return ret;
        end function;
        
        impure function gen_rand_guid_prefix return GUIDPREFIX_TYPE is
            variable ret : GUIDPREFIX_TYPE;
        begin
            ret := (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), 2 => RV.RandSlv(WORD_WIDTH));
            return ret;
        end function;
        
        procedure start_test is
        begin
            start <= '1';
            wait until rising_edge(clk);
            start <= '0';
            wait until rising_edge(clk);
        end procedure;
    begin
        
        SetAlertLogName("L0_rtps_writer_test1 - Metatraffic Handling");
        SetAlertEnable(FAILURE, TRUE);
        SetAlertEnable(ERROR, TRUE);
        SetAlertEnable(WARNING, TRUE);
        SetLogEnable(DEBUG, FALSE);
        SetLogEnable(PASSED, FALSE);
        SetLogEnable(INFO, TRUE);
        RV.InitSeed(RV'instance_name);
        
        p0.guidPrefix := gen_rand_guid_prefix;
        p1.guidPrefix := gen_rand_guid_prefix;
        
        -- Endpoint 1
        e0                      := DEFAULT_ENDPOINT_DATA;
        e0.participant          := p0;
        e0.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e0.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        e0.reliability          := RELIABLE_RELIABILITY_QOS;
        -- Endpoint 2
        e1                      := DEFAULT_ENDPOINT_DATA;
        e1.participant          := p0;
        e1.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e1.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        e1.reliability          := BEST_EFFORT_RELIABILITY_QOS;
        -- Endpoint 3
        e2                      := DEFAULT_ENDPOINT_DATA;
        e2.participant          := p1;
        e2.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e2.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        e2.expectsInlineQoS(0)  := '1';
        e2.durability           := TRANSIENT_LOCAL_DURABILITY_QOS;
        e2.reliability          := BEST_EFFORT_RELIABILITY_QOS;
        -- Endpoint 4
        e3                      := DEFAULT_ENDPOINT_DATA;
        e3.participant          := p1;
        e3.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e3.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        e3.expectsInlineQoS(0)  := '1';
        e3.reliability          := RELIABLE_RELIABILITY_QOS;
        
        Log("Initiating Test", INFO);
        stim_done   <= '0';
        start       <= '0';
        reset       <= '1';
        w_map       <= (others => '0');
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        -- MEMORY 0 STATE -/0,17,34
        -- MEMORY 1 STATE -/0,17,34
        
        
        Log("Insert Endpoint 0 Participant 0 {WRITER 0}", INFO);
        endpoint        := e0;
        endpoint.nr     := 0;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "10";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 17, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 0, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 0(P0E0)/17,34
        -- MEMORY 1 STATE -/0,17,34
        
        Log("Insert Endpoint 1 Participant 0 {WRITER 0, WRITER 1}", INFO);
        endpoint            := e1;
        endpoint.nr         := 1;
        endpoint.match      := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint.nr         := 0;
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 34, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 17, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 17(P0E1),0(P0E0)/34
        -- MEMORY 1 STATE 0(P0E1)/17,34
        
        Log("Insert Endpoint 2 Participant 1 {WRITER 0}", INFO);
        endpoint        := e2;
        endpoint.nr     := 2;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "10";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 17, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 34(P1E2),17(P0E1),0(P0E0)/-
        -- MEMORY 1 STATE 0(P0E1)/17,34
        
        Log("Insert Endpoint 3 Participant 1 {WRITER 0, WRITER 1}", INFO);
        Log("WRITER 0: Ignore", DEBUG);
        endpoint        := e3;
        endpoint.nr     := 1;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        -- Re-check Mem-State
        endpoint        := e0;
        endpoint.nr     := 0;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint        := e1;
        endpoint.nr     := 1;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint.nr     := 0;
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint        := e2;
        endpoint.nr     := 2;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 34(P1E2),17(P0E1),0(P0E0)/-
        -- MEMORY 1 STATE 17(P1E3),0(P0E1)/34
        
        Log("Remove Endpoint 2 Participant 1 {WRITER 0, WRITER 1}", INFO);
        Log("WRITER 1: Ignore", DEBUG);
        endpoint        := e2;
        endpoint.nr     := 2;
        endpoint.match  := UNMATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 34, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 17(P0E1),0(P0E0)/34
        -- MEMORY 1 STATE 17(P1E3),0(P0E1)/34
        
        Log("Insert Endpoint 3 Participant 1 {WRITER 0 ,WRITER 1}", INFO);
        Log("WRITER 1: Ignore", DEBUG);
        endpoint        := e3;
        endpoint.nr     := 2;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 34(P1E3),17(P0E1),0(P0E0)/-
        -- MEMORY 1 STATE 17(P1E3),0(P0E1)/34
        
        Log("Remove Participant 0 {WRITER 0, WRITER 1}", INFO);
        participant         := p0;
        participant.match   := UNMATCH;
        gen_participant_match_frame(participant, stimulus);
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 0, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 0, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 34(P1E3)/0,17
        -- MEMORY 1 STATE 17(P1E3)/0,34
        
        Log("Insert Endpoint 2 Participant 1 {WRITER 0}", INFO);
        endpoint        := e2;
        endpoint.nr     := 0;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "10";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 17, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 0, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 0(P1E2),34(P1E3)/17
        -- MEMORY 1 STATE 17(P1E3)/0,34
        
        Log("Unknown Metatraffic Operation followed by insertion of Enpoint 1 Participant 0 {WRITER 0, WRITER 1}", INFO);
        for i in 0 to 9 loop
            stimulus.data(i)    := RV.RandSlv(WORD_WIDTH);
        end loop;
        stimulus.last(9)    := '1';
        stimulus.length     := 10;
        endpoint        := e1;
        endpoint.nr     := 1;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus);
        -- Re-check Mem-State
        endpoint        := e2;
        endpoint.nr     := 0;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint        := e1;
        endpoint.nr     := 1;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint.nr     := 0;
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint        := e3;
        endpoint.nr     := 2;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint.nr     := 1;
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 17(P0E1),0(P1E2),34(P1E3)/-
        -- MEMORY 1 STATE 0(P0E1)17(P1E3)/34
        
        Log("Update Endpoint 3 Participant 1 {WRITER 0, WRITER 1}", INFO);
        endpoint        := e3;
        endpoint.match  := MATCH;
        endpoint.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        gen_endpoint_match_frame(endpoint, stimulus);
        endpoint.nr     := 2;
        SB0_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        endpoint.nr     := 1;
        SB1_mem.Push(gen_reader_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_test;
        wait_on_sig(packet_sent);
        stimulus            := EMPTY_TEST_PACKET;
        wait_on_sig(mem_check_done);
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        -- MEMORY 0 STATE 17(P0E1),0(P1E2),34(P1E3)/-
        -- MEMORY 1 STATE 0(P0E1)17(P1E3)/34
        
        stim_done   <= '1';
        wait_on_sig(test_done);
        TranscriptOpen(RESULTS_FILE, APPEND_MODE);
        SetTranscriptMirror;
        ReportAlerts;
        TranscriptClose;
        std.env.stop;
        wait;
    end process;
    
    clock_prc : process
    begin
        clk <= '0';
        wait for 25 ns;
        clk <= '1';
        wait for 25 ns;
    end process;
    
    in_empty_prc : process
    begin
        empty_meta  <= not w_map;
        wait until rising_edge(clk);
        empty_meta  <= (others => '1');
        wait until rising_edge(clk);
    end process;
    
    alert_prc : process(all)
    begin
        if rising_edge(clk) then
            alertif(empty_meta = (empty_meta'range => '1') and rd_meta = '1', "Input FIFO read signal high while empty signal high", FAILURE);
        end if;
    end process;
    
    input_prc : process(all)
    begin
        data_in_meta        <= stimulus.data(cnt_stim);
        last_word_in_meta   <= stimulus.last(cnt_stim);
        
        if rising_edge(clk) then
            if (reset = '1') then
                cnt_stim    <= 0;
                stim_stage  <= IDLE;
                packet_sent <= '1';
            else
                case (stim_stage) is
                    when IDLE =>
                        if (start = '1' and stimulus.length /= 0) then
                            stim_stage  <= BUSY;
                            packet_sent <= '0';
                        end if;
                    when BUSY =>
                        if (rd_meta = '1') then
                            if (cnt_stim = stimulus.length-1) then
                                stim_stage  <= IDLE;
                                packet_sent <= '1';
                                cnt_stim    <= 0;
                            else
                                cnt_stim    <= cnt_stim + 1;
                            end if;
                        end if;
                end case;
            end if;
        end if;
    end process;
    
    done_proc : process(clk)
    begin
        if rising_edge(clk) then
            if (stim_done = '1' and SB0_mem.empty and SB1_mem.empty) then
                test_done   <= '1';
            else
                test_done   <= '0';
            end if;
        end if;
    end process;
    
    mem_check_prc : process
        alias mem0 is <<signal uut.mem_ctrl_gen(0).mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
        alias mem1 is <<signal uut.mem_ctrl_gen(1).mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
        alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
        alias idle_sig is <<signal uut.idle_sig : std_logic>>;
        variable reference : TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE;
        
        -- NOTE: This procedure waits until the idle_sig is high for at least
        --       two consecutive clock cycles.
        procedure wait_on_idle is
            variable first : boolean := TRUE;
        begin
            loop
                if (idle_sig /= '1') then
                    wait until idle_sig = '1';
                elsif (not first) then
                    exit;
                end if;
                wait until rising_edge(clk);
                wait until rising_edge(clk);
                first := FALSE;
            end loop;
        end procedure;
    begin
        wait_on_sig(start);
        wait until falling_edge(packet_sent);
        mem_check_done  <= '0';
        -- Wait for Packet to be sent
        wait_on_sig(packet_sent);
        -- Wait for UUT IDLE state
        wait_on_idle;
        wait_on_sig(mem_op_done);
        -- MEM0
        while (not SB0_mem.empty) loop
            SB0_mem.Pop(reference);
            for i in 0 to reference'length-1 loop
                AffirmIf(?? (mem0(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem0(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
            end loop;
        end loop;
        -- MEM1
        while (not SB1_mem.empty) loop
            SB1_mem.Pop(reference);
            for i in 0 to reference'length-1 loop
                AffirmIf(?? (mem1(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem1(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
            end loop;
        end loop;
        -- Toggle High for one clock cycle
        mem_check_done  <= '1';
        wait until rising_edge(clk);
    end process;
    
    watchdog : process
    begin
        wait for 1 ms;
        Alert("Test timeout", FAILURE);
        std.env.stop;
    end process;
    
end architecture;