library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library osvvm; -- Utility Library
context osvvm.OsvvmContext;

use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;

-- This testbench tests the Liveliness handling of the RTPS Reader.
-- The testbench checks the memory contents at specific times, and also checks if the removal is propagated to the History Cache.

entity L0_rtps_reader_test3 is
end entity;

architecture testbench of L0_rtps_reader_test3 is
    
    -- *CONSTANT DECLARATION*
    constant ACCEPT_RES             : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
    constant REJECT_RES             : std_logic_vector(WORD_WIDTH downto 0) := (others => '1');
    constant MAX_REMOTE_ENDPOINTS   : natural := 3;
    constant NUM_READERS            : natural := 2;
    
    impure function gen_test_config return CONFIG_ARRAY_TYPE is
        variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_READER_CONFIG);
    begin
        -- vrka
        ret(0).RELIABILITY_QOS              := RELIABLE_RELIABILITY_QOS;
        ret(0).LIVELINESS_QOS               := AUTOMATIC_LIVELINESS_QOS;
        ret(0).DURABILITY_QOS               := VOLATILE_DURABILITY_QOS;
        ret(0).HEARTBEAT_RESPONSE_DELAY     := DURATION_ZERO;
        ret(0).HEARTBEAT_SUPPRESSION_DELAY  := DURATION_ZERO;
        ret(0).LEASE_DURATION               := gen_duration(5 sec);
        ret(0).WITH_KEY                     := TRUE;
        ret(0).MAX_PAYLOAD_SIZE             := 44;
        -- vrkm
        ret(1).RELIABILITY_QOS              := RELIABLE_RELIABILITY_QOS;
        ret(1).LIVELINESS_QOS               := MANUAL_BY_TOPIC_LIVELINESS_QOS;
        ret(1).DURABILITY_QOS               := VOLATILE_DURABILITY_QOS;
        ret(1).HEARTBEAT_RESPONSE_DELAY     := DURATION_ZERO;
        ret(1).HEARTBEAT_SUPPRESSION_DELAY  := DURATION_ZERO;
        ret(1).LEASE_DURATION               := gen_duration(5 sec);
        ret(1).WITH_KEY                     := TRUE;
        ret(1).MAX_PAYLOAD_SIZE             := 44;
        return ret;
    end function;
    constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
    
    -- *TYPE DECLARATION*
    type SEND_STAGE_TYPE is (IDLE, BUSY);
    type HC_STAGE_TYPE is (IDLE, CHECK, DONE);
    type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
    type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural;
    
    -- *SIGNAL DECLARATION*
    signal clk, rd_user, rd_meta, last_word_in_user, last_word_in_meta : std_logic := '0';
    signal empty_user, empty_meta, w_map : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal reset : std_logic := '1';
    signal data_in_user, data_in_meta : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
    signal data_out_hc : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0'));
    signal start_hc, ack_hc, done_hc, ready_out_hc, valid_out_hc, last_word_out_hc : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal opcode_hc : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP);
    signal ret_hc : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => OK);
    signal test_time : TIME_TYPE := TIME_INVALID;
    signal stim_stage_user, stim_stage_meta : SEND_STAGE_TYPE := IDLE;
    signal stage_hc : HC_STAGE_TYPE := IDLE;
    shared variable stimulus_user, stimulus_meta, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
    signal packet_sent_user, packet_sent_meta : std_logic := '0';
    signal cnt_stim_meta, cnt_stim_user : natural := 0;
    signal start_meta, start_user : std_logic := '0';
    shared variable SB_hc : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
    shared variable SB0_mem, SB1_mem : work.ScoreBoardPkg_MemoryTest.ScoreBoardPType;
    signal stim_done, mem_check_done, out_check_done, test_done, mem_check : std_logic := '0';
    
    -- *FUNCTION DECLARATION*
    function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
        variable ret : SEQUENCENUMBER_TYPE;
    begin
        ret(0)  := (others => '0');
        ret(1)  := unsigned(int(input, WORD_WIDTH));
        return ret;
    end function;
    
    procedure wait_on_sig(signal sig : std_logic) is
    begin
        if (sig /= '1') then
            wait on sig until sig = '1';
        end if;
    end procedure;
    
begin

    -- Unit Under Test
    uut : entity work.rtps_reader(arch)
        generic map (
            NUM_READERS             => NUM_READERS,
            CONFIG_ARRAY            => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG),
            ENTITYID                => (0 => x"2aa0b907",1 => x"a60db607"),
            MAX_REMOTE_ENDPOINTS    => MAX_REMOTE_ENDPOINTS
        )
        port map (
            -- SYSTEM
            clk                 => clk,
            reset               => reset,
            time                => test_time,
            empty_user          => empty_user or (empty_user'range => packet_sent_user),
            rd_user             => rd_user,
            data_in_user        => data_in_user,
            last_word_in_user   => last_word_in_user,
            empty_meta          => empty_meta or (empty_meta'range => packet_sent_meta),
            rd_meta             => rd_meta,
            data_in_meta        => data_in_meta,
            last_word_in_meta   => last_word_in_meta,
            wr_ro               => open,
            full_ro             => '0',
            last_word_out_ro    => open,
            data_out_ro         => open,
            start_hc            => start_hc,
            opcode_hc           => opcode_hc,
            ack_hc              => ack_hc,
            done_hc             => done_hc,
            ret_hc              => ret_hc,
            data_out_hc         => data_out_hc,
            valid_out_hc        => valid_out_hc,
            ready_out_hc        => ready_out_hc,
            last_word_out_hc    => last_word_out_hc
        );
    
    stimulus_prc : process
        variable RV                     : RandomPType;
        variable p0, p1, p2             : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA;
        variable e0, e1, e2, endpoint   : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA;
        variable payload                : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
        variable sub                    : RTPS_SUBMESSAGE_TYPE := DEFAULT_RTPS_SUBMESSAGE;
        variable cc                     : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
        
        alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
        alias idle_sig is <<signal uut.idle_sig : std_logic>>;
        alias empty_head is <<signal uut.empty_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE>>;
        
        -- Wrapper to use procedure as function
        impure function gen_rand_loc_2 return LOCATOR_TYPE is
            variable ret : LOCATOR_TYPE := EMPTY_LOCATOR;
        begin
            gen_rand_loc(RV, ret);
            return ret;
        end function;
        
        impure function gen_rand_guid_prefix return GUIDPREFIX_TYPE is
            variable ret : GUIDPREFIX_TYPE;
        begin
            ret := (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), 2 => RV.RandSlv(WORD_WIDTH));
            return ret;
        end function;
        
        procedure start_meta_test is
        begin
            start_meta  <= '1';
            wait until rising_edge(clk);
            start_meta  <= '0';
            wait until rising_edge(clk);
        end procedure;
        
        procedure start_user_test is
        begin
            start_user  <= '1';
            wait until rising_edge(clk);
            start_user  <= '0';
            wait until rising_edge(clk);
        end procedure;
        
        procedure start_mem_check is
        begin
            mem_check   <= '1';
            wait until rising_edge(clk);
            mem_check   <= '0';
            wait until rising_edge(clk);
        end procedure;
        
        procedure push_remove(writer_id,i : natural) is
            variable t : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
        begin
            t(i) := '1';
            SB_hc.Push(t);
            SB_hc.Push(std_logic_vector(to_unsigned(writer_id, WORD_WIDTH)));
        end procedure;
        
        procedure push_reference(accept : in boolean; i : in natural) is
            variable t : std_logic_vector(0 to NUM_READERS-1);
        begin
            t := (i => '1', others => '0');
            -- NOTE: First Word represents the Response that we will return.
            if (accept) then
                SB_hc.Push(ACCEPT_RES);
            else
                SB_hc.Push(REJECT_RES);
            end if;
            SB_hc.push(t);
            for i in 0 to reference.length-1 loop
                SB_hc.Push(reference.last(i) & reference.data(i));
            end loop;
        end procedure;
        
        impure function gen_payload return TEST_PACKET_TYPE is
            variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
        begin
            for i in 0 to RV.RandInt(1,10) loop
                ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
                ret.length  := ret.length + 1;
            end loop;
            ret.last(ret.length-1) := '1';
            return ret;
        end function;
        
        impure function gen_key_hash return KEY_HASH_TYPE is
            variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
        begin
            for i in 0 to KEY_HASH_TYPE'length-1 loop
                ret(i) := RV.RandSlv(WORD_WIDTH);
            end loop;
            return ret;
        end function;
        
        -- NOTE: This procedure waits until the idle_sig is high for at least
        --       two consecutive clock cycles.
        procedure wait_on_idle is
            variable first : boolean := TRUE;
        begin
            loop
                if (idle_sig /= '1') then
                    wait until idle_sig = '1';
                elsif (not first) then
                    exit;
                end if;
                wait until rising_edge(clk);
                wait until rising_edge(clk);
                first := FALSE;
            end loop;
        end procedure;
        
    begin
        
        SetAlertLogName("L0_rtps_reader_test3 - Liveliness Handling");
        SetAlertEnable(FAILURE, TRUE);
        SetAlertEnable(ERROR, TRUE);
        SetAlertEnable(WARNING, TRUE);
        SetLogEnable(DEBUG, FALSE);
        SetLogEnable(PASSED, FALSE);
        SetLogEnable(INFO, TRUE);
        RV.InitSeed(RV'instance_name);
        SB_hc.SetAlertLogID(Name => "HC", ParentID => OSVVM_ALERTLOG_ID);
        SB0_mem.SetAlertLogID(Name => "MEMORY 0", ParentID => OSVVM_ALERTLOG_ID);
        SB1_mem.SetAlertLogID(Name => "MEMORY 1", ParentID => OSVVM_ALERTLOG_ID);
        
        -- Participant 0
        p0              := DEFAULT_PARTICIPANT_DATA;
        p0.guidPrefix   := gen_rand_guid_prefix;
        -- Participant 1
        p1              := DEFAULT_PARTICIPANT_DATA;
        p1.guidPrefix   := gen_rand_guid_prefix;
        -- Participant 2
        p2              := DEFAULT_PARTICIPANT_DATA;
        p2.guidPrefix   := gen_rand_guid_prefix;
        
        -- Endpoint 0
        e0                      := DEFAULT_ENDPOINT_DATA;
        e0.nr                   := 0;
        e0.reader               := FALSE;
        e0.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e0.participant          := p0;
        e0.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        -- Endpoint 1
        e1                      := DEFAULT_ENDPOINT_DATA;
        e1.nr                   := 1;
        e1.reader               := FALSE;
        e1.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e1.participant          := p1;
        e1.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        -- Endpoint 2
        e2                      := DEFAULT_ENDPOINT_DATA;
        e2.nr                   := 2;
        e2.reader               := FALSE;
        e2.entityid             := RV.RandSlv(ENTITYID_WIDTH);
        e2.participant          := p2;
        e2.unicastLocatorList   := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
        
        Log("Initiating Test", INFO);
        Log("Current Time: 0 s", INFO);
        test_time   <= TIME_ZERO;
        stim_done   <= '0';
        start_meta  <= '0';
        start_user  <= '0';
        mem_check   <= '0';
        reset       <= '1';
        w_map       <= (others => '0');
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        -- MEMORY 0 STATE -/0,17,34
        -- MEMORY 1 STATE -/0,17,34
        
        Log("Insert Endpoint 0 Participant 0 {R0,R1}", INFO);
        endpoint        := e0;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus_meta);
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_meta_test;
        wait_on_sig(packet_sent_meta);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 17, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 17, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 0(P0E0)/17,34
        -- MEMORY 1 STATE 0(P0E0)/17,34
        
        Log("Insert Endpoint 1 Participant 1 {R0,R1}", INFO);
        endpoint        := e1;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus_meta);
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_meta_test;
        wait_on_sig(packet_sent_meta);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 34, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 17(P1E1),0(P0E0)/34
        -- MEMORY 1 STATE 17(P1E1),0(P0E0)/34
        
        Log("Insert Endpoint 2 Participant 2 {R0,R1}", INFO);
        endpoint        := e2;
        endpoint.match  := MATCH;
        gen_endpoint_match_frame(endpoint, stimulus_meta);
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        w_map   <= "11";
        start_meta_test;
        wait_on_sig(packet_sent_meta);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 50, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 50, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        -- MEMORY 1 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        
        Log("Current Time: 1 s", INFO);
        test_time   <= gen_duration(1 sec);
        wait until rising_edge(clk);
        
        Log("Endpoint 0 sent DATA [SN 1] {R0,R1}", INFO);
        Log("R0,R1: Accept", DEBUG);
        endpoint            := e0;
        sub                 := DEFAULT_RTPS_SUBMESSAGE;
        sub.submessageID    := SID_DATA;
        sub.writerId        := endpoint.entityid;
        sub.readerId        := DEFAULT_READER_ENTITYID;
        sub.writerSN        := gen_sn(1);
        sub.flags(SUBMESSAGE_DATA_FLAG_POS) := '1';
        sub.data := gen_payload;
        gen_rtps_handler_out(sub, get_loc(endpoint), FALSE, TIME_INVALID, endpoint.participant.guidPrefix, stimulus_user);
        cc := gen_cache_change(sub);
        gen_add_cache_change_dds(cc, TIME_INVALID, endpoint.nr, reference);
        push_reference(TRUE,0);
        push_reference(TRUE,1);
        w_map   <= "11";
        start_user_test;
        wait_on_sig(packet_sent_user);
        wait_on_sig(out_check_done);
        wait_on_idle;
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        -- MEMORY 1 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        
        Log("Current Time: 2 s", INFO);
        test_time   <= gen_duration(2 sec);
        wait until rising_edge(clk);
        
        Log("Participant 1 Liveliness Update {R0,R1}", INFO);
        Log("R1: Ignore", DEBUG);
        gen_liveliness_update_frame(p1, stimulus_meta);
        w_map   <= "11";
        start_meta_test;
        wait_on_sig(packet_sent_meta);
        wait_on_idle;
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        -- MEMORY 1 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        
        Log("Current Time: 3 s", INFO);
        test_time   <= gen_duration(3 sec);
        wait until rising_edge(clk);
        
        Log("Endpoint 2 HEARTBEAT Liveliness Update {R1}", INFO);
        Log("R0: Ignore", DEBUG);
        endpoint            := e2;
        sub                 := DEFAULT_RTPS_SUBMESSAGE;
        sub.submessageID    := SID_HEARTBEAT;
        sub.writerId        := endpoint.entityid;
        sub.readerId        := DEFAULT_READER_ENTITYID;
        sub.firstSN         := gen_sn(0);
        sub.lastSN          := gen_sn(1);
        sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS)   := '1';
        gen_rtps_handler_out(sub, get_loc(endpoint), FALSE, TIME_INVALID, endpoint.participant.guidPrefix, stimulus_user);
        w_map   <= "01";
        start_user_test;
        wait_on_sig(packet_sent_user);
        wait_on_idle;
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        -- MEMORY 1 STATE 34(P2E2),17(P1E1),0(P0E0)/-
        
        Log("Current Time: 5 s", INFO);
        test_time   <= gen_duration(5 sec);
        wait until rising_edge(clk);
        
        Log("R0: Remove of Endpoint 2", INFO);
        Log("R1: Remove of Endpoint 1", INFO);
        endpoint    := e0;
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        endpoint    := e1;
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        endpoint    := e2;
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        push_remove(2,0);
        push_remove(1,1);
        wait_on_sig(out_check_done);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 34, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 17, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 17(P1E1),0(P0E0)/34
        -- MEMORY 1 STATE 34(P2E2),0(P0E0)/17
        
        Log("Current Time: 6 s", INFO);
        test_time   <= gen_duration(6 sec);
        wait until rising_edge(clk);
        
        Log("R0,R1: Remove of Endpoint 0", INFO);
        endpoint    := e0;
        endpoint    := e1;
        SB0_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        endpoint    := e2;
        SB1_mem.Push(gen_writer_endpoint_mem_frame(endpoint));
        push_remove(0,0);
        push_remove(0,1);
        wait_on_sig(out_check_done);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 0, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 0, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE 17(P1E1)/0,34
        -- MEMORY 1 STATE 34(P2E2)/0,17
        
        Log("Current Time: 7 s", INFO);
        test_time   <= gen_duration(7 sec);
        wait until rising_edge(clk);
        
        Log("R0: Remove of Endpoint 1", INFO);
        push_remove(1,0);
        wait_on_sig(out_check_done);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 17, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 0, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE -/17,0,34
        -- MEMORY 1 STATE 34(P2E2)/0,17
        
        Log("Current Time: 8 s", INFO);
        test_time   <= gen_duration(8 sec);
        wait until rising_edge(clk);
        
        Log("R0: Remove of Endpoint 1", INFO);
        push_remove(2,1);
        wait_on_sig(out_check_done);
        start_mem_check;
        wait_on_sig(mem_check_done);
        wait_on_idle;
        AlertIf(empty_head(0) /= 17, "Memory 0 Empty List Head incorrect", FAILURE);
        AlertIf(empty_head(1) /= 34, "Memory 1 Empty List Head incorrect", FAILURE);
        stimulus_meta   := EMPTY_TEST_PACKET;
        stimulus_user   := EMPTY_TEST_PACKET;
        reference       := EMPTY_TEST_PACKET;
        -- MEMORY 0 STATE -/17,0,34
        -- MEMORY 1 STATE -/34,0,17
        
        stim_done   <= '1';
        wait_on_sig(test_done);
        TranscriptOpen(RESULTS_FILE, APPEND_MODE);
        SetTranscriptMirror;
        ReportAlerts;
        TranscriptClose;
        std.env.stop;
        wait;
    end process;
    
    clock_prc : process
    begin
        clk <= '0';
        wait for 25 ns;
        clk <= '1';
        wait for 25 ns;
    end process;
    
    empty_meta_prc : process
    begin
        empty_meta  <= not w_map;
        wait until rising_edge(clk);
        empty_meta  <= (others => '1');
        wait until rising_edge(clk);
    end process;
    
    empty_user_prc : process
    begin
        empty_user  <= not w_map;
        wait until rising_edge(clk);
        empty_user  <= (others => '1');
        wait until rising_edge(clk);
    end process;
    
    alert_prc : process(all)
    begin
        if rising_edge(clk) then
            alertif(empty_meta = (empty_meta'range => '1') and rd_meta = '1', "Input FIFO read signal high while empty signal high (meta)", FAILURE);
            alertif(empty_user = (empty_user'range => '1') and rd_user = '1', "Input FIFO read signal high while empty signal high (user)", FAILURE);
        end if;
    end process;
    
    input_meta_prc : process(all)
    begin
        data_in_meta        <= stimulus_meta.data(cnt_stim_meta);
        last_word_in_meta   <= stimulus_meta.last(cnt_stim_meta);
        
        if rising_edge(clk) then
            if (reset = '1') then
                cnt_stim_meta       <= 0;
                stim_stage_meta     <= IDLE;
                packet_sent_meta    <= '1';
            else
                case (stim_stage_meta) is
                    when IDLE =>
                        if (start_meta = '1' and stimulus_meta.length /= 0) then
                            stim_stage_meta     <= BUSY;
                            packet_sent_meta    <= '0';
                        end if;
                    when BUSY =>
                        if (rd_meta = '1') then
                            if (cnt_stim_meta = stimulus_meta.length-1) then
                                stim_stage_meta     <= IDLE;
                                packet_sent_meta    <= '1';
                                cnt_stim_meta       <= 0;
                            else
                                cnt_stim_meta   <= cnt_stim_meta + 1;
                            end if;
                        end if;
                end case;
            end if;
        end if;
    end process;
    
    input_user_prc : process(all)
    begin
        data_in_user        <= stimulus_user.data(cnt_stim_user);
        last_word_in_user   <= stimulus_user.last(cnt_stim_user);
        
        if rising_edge(clk) then
            if (reset = '1') then
                cnt_stim_user       <= 0;
                stim_stage_user     <= IDLE;
                packet_sent_user    <= '1';
            else
                case (stim_stage_user) is
                    when IDLE =>
                        if (start_user = '1' and stimulus_user.length /= 0) then
                            stim_stage_user     <= BUSY;
                            packet_sent_user    <= '0';
                        end if;
                    when BUSY =>
                        if (rd_user = '1') then
                            if (cnt_stim_user = stimulus_user.length-1) then
                                stim_stage_user     <= IDLE;
                                packet_sent_user    <= '1';
                                cnt_stim_user       <= 0;
                            else
                                cnt_stim_user   <= cnt_stim_user + 1;
                            end if;
                        end if;
                end case;
            end if;
        end if;
    end process;
    
    done_proc : process(clk)
    begin
        if rising_edge(clk) then
            if (stim_done = '1' and SB_hc.empty and SB0_mem.empty and SB1_mem.empty) then
                test_done   <= '1';
            else
                test_done   <= '0';
            end if;
        end if;
    end process;
    
    hc_prc : process (all)
        variable ind    : natural := 0;
        variable accept : std_logic_vector(WORD_WIDTH downto 0);
        
        function one_hot_converter(input : std_logic_vector) return natural is
        begin
            for i in 0 to input'length-1 loop
                if (input(i) = '1') then
                    return i;
                end if;
            end loop;
            return 0; -- DEFAULT
        end function;
    begin
        if (SB_hc.empty) then
            out_check_done  <= '1';
        else
            out_check_done  <= '0';
        end if;
        if rising_edge(clk) then
            case (stage_hc) is
                when IDLE =>
                    if (start_hc /= (start_hc'range => '0')) then
                        alertif((signed(start_hc) and (- signed(start_hc))) = (start_hc'range => '0'), "start_hc not in one-hot encoding", FAILURE);
                        ind := one_hot_converter(start_hc);
                        case (opcode_hc(ind)) is
                            when REMOVE_WRITER =>
                                SB_hc.check(start_hc);
                                SB_hc.check(data_out_hc(ind));
                                accept := ACCEPT_RES;
                                stage_hc    <= DONE;
                            when ADD_CACHE_CHANGE =>
                                -- Pop Response Value
                                SB_hc.pop(accept);
                                SB_hc.Check(start_hc);
                                stage_hc    <= CHECK;
                            when others =>
                                Alert("Unexpected HC Opcode", FAILURE);
                                stage_hc    <= DONE;
                        end case;
                    end if;
                when CHECK =>
                    if (valid_out_hc(ind) = '1') then
                        SB_hc.Check(last_word_out_hc(ind) & data_out_hc(ind));
                        
                        if (last_word_out_hc(ind) = '1') then
                            stage_hc    <= DONE;
                        end if;
                    end if;
                when DONE =>
                    stage_hc    <= IDLE;
                when others =>
                    null;
            end case;
        end if;
        
        -- DEFAULT
        ack_hc          <= (others => '0');
        done_hc         <= (others => '0');
        ret_hc          <= (others => ERROR);
        ready_out_hc    <= (others => '0');
        
        case (stage_hc) is
            when IDLE =>
                if (start_hc /= (start_hc'range => '0')) then
                    -- HACK: We trigger all acks because we cannot use 'ind' variable in the same clock cycle
                    --       Since the uut only interfaces with 1 HC at a time (one-hot encoded start_hc) this
                    --       is still valid.
                    ack_hc  <= (others => '1');
                end if;
            when CHECK =>
                ready_out_hc(ind)   <= '1';
            when DONE =>
                done_hc(ind)    <= '1';
                if (accept = ACCEPT_RES) then
                    ret_hc(ind) <= OK;
                else
                    ret_hc(ind) <= REJECTED;
                end if;
            when others =>
                null;
        end case;
    end process;
    
    mem_check_prc : process
        alias mem0 is <<signal uut.mem_ctrl_gen(0).mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
        alias mem1 is <<signal uut.mem_ctrl_gen(1).mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
        alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
        alias idle_sig is <<signal uut.idle_sig : std_logic>>;
        variable reference : TEST_WRITER_ENDPOINT_MEMORY_FRAME_TYPE;
        
        -- NOTE: This procedure waits until the idle_sig is high for at least
        --       two consecutive clock cycles.
        procedure wait_on_idle is
            variable first : boolean := TRUE;
        begin
            loop
                if (idle_sig /= '1') then
                    wait until idle_sig = '1';
                elsif (not first) then
                    exit;
                end if;
                wait until rising_edge(clk);
                wait until rising_edge(clk);
                first := FALSE;
            end loop;
        end procedure;
    begin
        wait_on_sig(mem_check);
        mem_check_done  <= '0';
        -- Wait for UUT IDLE state
        wait_on_idle;
        wait_on_sig(mem_op_done);
        -- MEM0
        while (not SB0_mem.empty) loop
            SB0_mem.Pop(reference);
            for i in 0 to reference'length-1 loop
                AffirmIf(?? (mem0(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem0(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
            end loop;
        end loop;
        -- MEM1
        while (not SB1_mem.empty) loop
            SB1_mem.Pop(reference);
            for i in 0 to reference'length-1 loop
                AffirmIf(?? (mem1(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem1(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
            end loop;
        end loop;
        -- Toggle High for one clock cycle
        mem_check_done  <= '1';
        wait until rising_edge(clk);
    end process;
    
    watchdog : process
    begin
        wait for 1 ms;
        Alert("Test timeout", FAILURE);
        std.env.stop;
    end process;
    
end architecture;