-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;

-- Test synthesis of SLV bit counter

entity test is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        input           : in std_logic_vector(31 downto 0);
        output          : out std_logic_vector(31 downto 0)
    );
end entity;

architecture arch of test is
    
    function bitmap_converter(input : std_logic_vector) return natural is
        variable ret : natural := 0;
    begin
        for i in 0 to input'length-1 loop
            ret := ret + 1;
            if (input(i) = '1') then
                exit;
            end if;
        end loop;
        return ret;
    end function;
    
begin
    
    output <= std_logic_vector(to_unsigned(bitmap_converter(input), output'length));

end architecture;
