-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;

-- Test synthesis of 3-way min comparison

entity test2 is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        t1              : in TIME_TYPE;
        t2              : in TIME_TYPE;
        t3              : in TIME_TYPE;
        t               : in TIME_TYPE;
        t_out           : out TIME_TYPE
    );
end entity;

architecture arch of test2 is
    
    function min_time(t1, t2, t3, t : TIME_TYPE) return TIME_TYPE is
        variable ret : TIME_TYPE;
    begin
        if (not (t1 <= t)) then
            ret := t1;
        end if;
        if (not (t2 <= t) and t2 < ret) then
            ret := t2;
        end if;
        if (not (t3 <= t) and t3 < ret) then
            ret := t3;
        end if;
        return ret;
    end function;
    
begin
    
    process (all)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                t_out   <= TIME_INVALID;
            else
                t_out   <= min_time(t1,t2,t3,t);
            end if;
        end if;
    end process;

end architecture;
