library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library osvvm; -- Utility Library
context osvvm.OsvvmContext;

use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;

-- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations.
-- Implicitly some DDS Operations are also tested, since they are used for state checking.
-- More specifically the testbench covers following tests:
-- TEST: NORMAL ADD_CACHE_CHANGE
-- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: SAMPLE WITH ALIGNED PAYLOAD
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
-- TEST: NORMAL SAMPLE [KNOWN INSTANCE]
-- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE]
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER]
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER]
-- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE]
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION]
-- TEST: DISPOSE SAMPLE [KNOWN INSTANCE]
-- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE]
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
-- TEST: FILTER SAMPLE [KNOWN INSTANCE]
-- TEST: FILTER SAMPLE [UNKNOWN INSTANCE]
-- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
-- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
-- TEST: SAMPLE WITH KEY_HASH
-- TEST: SAMPLE WITHOUT KEY_HASH
-- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH]
-- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH]
-- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
-- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE

entity L0_dds_reader_test1 is
end entity;


architecture testbench of L0_dds_reader_test1 is
    
    -- *CONSTANT DECLARATION*
    constant MAX_REMOTE_ENDPOINTS   : natural := 3;
    constant NUM_READERS            : natural := 6;
    
    impure function gen_test_config return CONFIG_ARRAY_TYPE is
        variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG);
    begin
        -- arzkriu
        ret(0).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(0).DEADLINE_QOS             := DURATION_INFINITE;
        ret(0).MAX_SAMPLES              := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
        ret(0).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(0).HISTORY_QOS              := KEEP_ALL_HISTORY_QOS;
        ret(0).RELIABILITY_QOS          := RELIABLE_RELIABILITY_QOS;
        ret(0).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(0).DESTINATION_ORDER_QOS    := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(0).COHERENT_ACCESS          := FALSE;
        ret(0).ORDERED_ACCESS           := FALSE;
        ret(0).WITH_KEY                 := TRUE;
        ret(0).MAX_PAYLOAD_SIZE         := 40;
        -- lrzkriu
        ret(1).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(1).DEADLINE_QOS             := DURATION_INFINITE;
        ret(1).MAX_SAMPLES              := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
        ret(1).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(1).HISTORY_QOS              := KEEP_LAST_HISTORY_QOS;
        ret(1).RELIABILITY_QOS          := RELIABLE_RELIABILITY_QOS;
        ret(1).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(1).DESTINATION_ORDER_QOS    := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(1).COHERENT_ACCESS          := FALSE;
        ret(1).ORDERED_ACCESS           := FALSE;
        ret(1).WITH_KEY                 := TRUE;
        ret(1).MAX_PAYLOAD_SIZE         := 40;
        -- lbzkriu
        ret(2).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(2).DEADLINE_QOS             := DURATION_INFINITE;
        ret(2).MAX_SAMPLES              := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
        ret(2).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(2).HISTORY_QOS              := KEEP_LAST_HISTORY_QOS;
        ret(2).RELIABILITY_QOS          := BEST_EFFORT_RELIABILITY_QOS;
        ret(2).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(2).DESTINATION_ORDER_QOS    := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(2).COHERENT_ACCESS          := FALSE;
        ret(2).ORDERED_ACCESS           := FALSE;
        ret(2).WITH_KEY                 := TRUE;
        ret(2).MAX_PAYLOAD_SIZE         := 40;
        -- abzkriu
        ret(3).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(3).DEADLINE_QOS             := DURATION_INFINITE;
        ret(3).MAX_SAMPLES              := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
        ret(3).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(3).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(3).HISTORY_QOS              := KEEP_ALL_HISTORY_QOS;
        ret(3).RELIABILITY_QOS          := BEST_EFFORT_RELIABILITY_QOS;
        ret(3).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(3).DESTINATION_ORDER_QOS    := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(3).COHERENT_ACCESS          := FALSE;
        ret(3).ORDERED_ACCESS           := FALSE;
        ret(3).WITH_KEY                 := TRUE;
        ret(3).MAX_PAYLOAD_SIZE         := 40;
        -- arznriu
        ret(4).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(4).DEADLINE_QOS             := DURATION_INFINITE;
        ret(4).MAX_SAMPLES              := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(4).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(4).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(4).HISTORY_QOS              := KEEP_ALL_HISTORY_QOS;
        ret(4).RELIABILITY_QOS          := RELIABLE_RELIABILITY_QOS;
        ret(4).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(4).DESTINATION_ORDER_QOS    := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(4).COHERENT_ACCESS          := FALSE;
        ret(4).ORDERED_ACCESS           := FALSE;
        ret(4).WITH_KEY                 := FALSE;
        ret(4).MAX_PAYLOAD_SIZE         := 35;
        -- arzksiu
        ret(5).TIME_BASED_FILTER_QOS    := DURATION_ZERO;
        ret(5).DEADLINE_QOS             := DURATION_INFINITE;
        ret(5).MAX_SAMPLES              := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
        ret(5).MAX_INSTANCES            := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
        ret(5).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
        ret(5).HISTORY_QOS              := KEEP_ALL_HISTORY_QOS;
        ret(5).RELIABILITY_QOS          := RELIABLE_RELIABILITY_QOS;
        ret(5).PRESENTATION_QOS         := INSTANCE_PRESENTATION_QOS;
        ret(5).DESTINATION_ORDER_QOS    := BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS;
        ret(5).COHERENT_ACCESS          := FALSE;
        ret(5).ORDERED_ACCESS           := FALSE;
        ret(5).WITH_KEY                 := TRUE;
        ret(5).MAX_PAYLOAD_SIZE         := 40;
        return ret;
    end function;
    constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
    
    -- *TYPE DECLARATION*
    type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
    type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
    type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural;
    type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE;
    
    -- *SIGNAL DECLARATION*
    signal clk : std_logic := '0';
    signal reset : std_logic := '1';
    signal check_time : TIME_TYPE := TIME_ZERO;
    signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP);
    signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP);
    signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR);
    signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0'));
    signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0');
    signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0'));
    signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0'));
    signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE);
    signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE);
    signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE);
    signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL);
    signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0'));
    signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1);
    
    signal ind : natural := 0;
    signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
    signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
    signal dds_stage  : DDS_STAGE_TYPE := IDLE;
    signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
    shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
    shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
    shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM);
    signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
    
    -- *FUNCTION DECLARATION*
    function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
        variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
    begin
        for i in 0 to 3 loop
            ret(i) := not payload.data(i);
        end loop;
        
        return ret;
    end function;
    
    function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
        variable ret : SEQUENCENUMBER_TYPE;
    begin
        ret(0)  := (others => '0');
        ret(1)  := unsigned(int(input, WORD_WIDTH));
        return ret;
    end function;
    
    procedure wait_on_sig(signal sig : std_logic) is
    begin
        if (sig /= '1') then
            wait on sig until sig = '1';
        end if;
    end procedure;
    
begin

    -- Unit Under Test
    uut : entity work.dds_reader(arch)
        generic map (
            NUM_READERS             => NUM_READERS,
            CONFIG_ARRAY            => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG),
            MAX_REMOTE_ENDPOINTS    => MAX_REMOTE_ENDPOINTS
        )
        port map (
            clk                 => clk,
            reset               => reset,
            time                => check_time,
            start_rtps          => start_rtps,
            opcode_rtps         => opcode_rtps,
            ack_rtps            => ack_rtps,
            done_rtps           => done_rtps,
            ret_rtps            => ret_rtps,
            data_in_rtps        => data_in_rtps,
            valid_in_rtps       => valid_in_rtps,
            ready_in_rtps       => ready_in_rtps,
            last_word_in_rtps   => last_word_in_rtps,
            start_dds           => start_dds,
            ack_dds             => ack_dds,
            opcode_dds          => opcode_dds,
            instance_state_dds  => instance_state_dds,
            view_state_dds      => view_state_dds,
            sample_state_dds    => sample_state_dds,
            instance_handle_dds => instance_handle_dds,
            max_samples_dds     => max_samples_dds,
            get_data_dds        => get_data_dds,
            done_dds            => done_dds,
            return_code_dds     => return_code_dds,
            ready_out_dds       => ready_out_dds,
            valid_out_dds       => valid_out_dds,
            data_out_dds        => data_out_dds,
            last_word_out_dds   => last_word_out_dds,
            sample_info         => sample_info,
            sample_info_valid   => si_valid,
            sample_info_ack     => (others => '1'),
            eoc                 => eoc,
            status              => status
        );
    
    stimulus_prc : process
        variable RV : RandomPType;
        variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
        variable s  : SAMPLE_TYPE := DEFAULT_SAMPLE;
        variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
        
        alias idle_sig is <<signal uut.idle_sig : std_logic>>;
        alias inst_op_done is <<signal uut.inst_op_done : std_logic>>;
        alias empty_inst_head is <<signal uut.empty_inst_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE>>;
        alias empty_sample_head is <<signal uut.empty_sample_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE>>;
        alias empty_payload_head is <<signal uut.empty_payload_head_sig : EMPTY_HEAD_SIG_ARRAY_TYPE>>;
        
        impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
            variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
        begin
            assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
            
            for i in 0 to len-1 loop
                if (i < 4) then
                    -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
                    ret.data(ret.length) := not key_hash(i);
                else
                    ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
                end if;
                ret.length  := ret.length + 1;
            end loop;
            ret.last(ret.length-1)  := '1';
            
            return ret;
        end function;
        
        impure function gen_key_hash return KEY_HASH_TYPE is
            variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
        begin
            for i in 0 to KEY_HASH_TYPE'length-1 loop
                ret(i) := RV.RandSlv(WORD_WIDTH);
            end loop;
            return ret;
        end function;
        
        procedure start_dds is
        begin
            dds_start   <= '1';
            wait until rising_edge(clk);
            dds_start   <= '0';
            wait until rising_edge(clk);
        end procedure;
        
        procedure start_rtps is
        begin
            rtps_start   <= '1';
            wait until rising_edge(clk);
            rtps_start   <= '0';
            wait until rising_edge(clk);
        end procedure;
        
        procedure wait_on_completion is
        begin
            if (rtps_done /= '1' or dds_done  /= '1') then
                wait until rtps_done = '1' and dds_done  = '1';
            end if;
        end procedure;
        
        -- NOTE: This procedure waits until the idle_sig is high for at least
        --       two consecutive clock cycles.
        procedure wait_on_idle is
            variable first : boolean := TRUE;
        begin
            loop
                if (idle_sig /= '1') then
                    wait until idle_sig = '1';
                elsif (not first) then
                    exit;
                end if;
                wait until rising_edge(clk);
                wait until rising_edge(clk);
                first := FALSE;
            end loop;
            wait_on_sig(inst_op_done);
        end procedure;
        
    begin
        
        SetAlertLogName("L0_dds_reader_test1 - RTPS Handling");
        SetAlertEnable(FAILURE, TRUE);
        SetAlertEnable(ERROR, TRUE);
        SetAlertEnable(WARNING, TRUE);
        SetLogEnable(DEBUG, FALSE);
        SetLogEnable(PASSED, FALSE);
        SetLogEnable(INFO, TRUE);
        RV.InitSeed(RV'instance_name);
        sstate_id       <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID);
        vstate_id       <= GetAlertLogID("View State", ALERTLOG_BASE_ID);
        istate_id       <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID);
        ts_id           <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID);
        inst_id         <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
        pub_id          <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID);
        dis_gen_cnt_id  <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID);
        no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID);
        srank_id        <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID);
        grank_id        <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID);
        agrank_id       <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID);
        eoc_id          <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID);
        valid_id        <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
        data_id         <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
        ret_id          <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
        status_id       <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
        
        -- Key Hashes
        kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
        kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
        kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
        kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
        
        
        
        Log("Initiating Test", INFO);
        reset   <= '1';
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        reset   <= '0';
        wait_on_idle;
        
        Log("*READER 0 / READER 5*", INFO);
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 0, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22,33,44
        -- PAYLOAD MEMORY:     -/0,11,22,33,44
        -- INSTANCE MEMORY:    -/0,13,26
        -- ISTATE: -
        -- WRITER: -
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 0, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22,33,44
        -- PAYLOAD MEMORY:     -/0,11,22,33,44
        -- INSTANCE MEMORY:    -/0,13,26
        -- ISTATE: -
        -- WRITER: -
        
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(1 sec);
        
        -- TEST: NORMAL ADD_CACHE_CHANGE
        -- TEST: SAMPLE WITH ALIGNED PAYLOAD
        -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE]
        -- TEST: SAMPLE WITH KEY_HASH
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1)/11,22,33,44
        -- PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1)/11,22,33,44
        -- PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := HANDLE_NIL;
        cc.payload          := gen_payload(kh1,18);
        cc.src_timestamp    := gen_duration(2 sec);
        
        -- TEST: SAMPLE WITHOUT KEY_HASH
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
        -- TEST: NORMAL SAMPLE [KNOWN INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        s.inst          := kh1;
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VAILDATE STATE
        
        Log("R0,R5: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(3 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO);
        Log("R0,R5: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2)/22,33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2)/0,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2)/22,33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2)/0,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE]
        -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH]
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        s.inst          := kh1;
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2)/0,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:DISPOSED 
        -- WRITER: W0:I1
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2)/0,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:DISPOSED 
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,20);
        cc.src_timestamp    := gen_duration(4 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1)/44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1)/44
        -- INSTANCE MEMORY:    13(I2),0(I1)/26
        -- ISTATE: I1:DISPOSED, I2:ALIVE
        -- WRITER: W0:I1, W1:I2
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 26, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1)/44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1)/44
        -- INSTANCE MEMORY:    13(I2),0(I1)/26
        -- ISTATE: I1:DISPOSED, I2:ALIVE
        -- WRITER: W0:I1, W1:I2
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(5 sec);
        
        -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [UNKNOWN WRITER]
        
        Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 2]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := NOT_READ_SAMPLE_STATE;
        dds.istate      := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),33(I2S1),44(I3S1)/0,22
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),33(I2S1),44(I3S1)/0,22
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(6 sec);
        
        -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [Payload Memory Full]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),33(I2S1),44(I3S1)/0,22
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),33(I2S1),44(I3S1)/0,22
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R0: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1)/0,22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1)/11,22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1)/0,22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1)/11,22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,10);
        cc.src_timestamp    := gen_duration(7 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
        
        Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 0]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 0;
        change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0));
        change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5));
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W1:I2,I3, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2)/22,11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        remove_inst(kh1, mem(0));
        remove_inst(kh1, mem(5));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R0,R5: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11
        -- PAYLOAD MEMORY:     0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1)/11,33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1)/0,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1)/11,33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1)/0,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(8 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1)/11,33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1)/0,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1)/11,33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1)/0,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,10);
        cc.src_timestamp    := gen_duration(9 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,10);
        cc.src_timestamp    := gen_duration(10 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(11 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
        -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
        -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
        
        Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 1]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 1;
        change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0));
        change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5));
        change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0));
        change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5));
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33
        -- PAYLOAD MEMORY:     44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        
        -- NOTE: Because of the NOT_ALIVE_NO_WRITERS transition 2 Samples are pending generation, 
        --       but are waiting for space.
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.src_timestamp    := check_time;
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44
        -- PAYLOAD MEMORY:     11(I3S2),22(I4S1),0(I4S2)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44
        -- PAYLOAD MEMORY:     11(I3S2),22(I4S1),0(I4S2)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        
        -- NOTE: Even though the sample of I4 should be generated first, because it hits the MAX_SAMPLES_PER_INSTANCE
        --       Limit, it is skipped and the I2 sample is generated instead.
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- NOTE: We read the current KH4 Samples, so that we can easily remove the new KH4 Sample
        Log("R0,R5: DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ_INSTANCE;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        dds.inst        := kh4;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44
        -- PAYLOAD MEMORY:     11(I3S2),22(I4S1),0(I4S2)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44
        -- PAYLOAD MEMORY:     11(I3S2),22(I4S1),0(I4S2)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.src_timestamp    := check_time;
        
        Log("R0,R5: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE_INSTANCE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        dds.inst        := kh4;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),44(I4S3)/22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),44(I4S3)/22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R0: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE_INSTANCE;
        dds.max_samples := 1;
        dds.sstate      := NOT_READ_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        dds.inst        := kh4;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2)/22,44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2)/22,44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
        -- WRITER: W2:I3
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := HANDLE_NIL;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(12 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        s.inst          := kh4;
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(13 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE]
        -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 2;
        dds.sstate      := NOT_READ_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2)/44,33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2)/44,33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2)/22,44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(14 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3)/33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3)/33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,30);
        cc.src_timestamp    := gen_duration(15,0);
        
        -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)]", INFO);
        Log("R0,R5: REJECTED [Payload Memory Full]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3)/33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3)/33,22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3)/44,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,20);
        cc.src_timestamp    := gen_duration(16 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_inst(kh2, mem(0));
        remove_inst(kh2, mem(5));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3),33(I1S1)/22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3),44(I1S1),33(I1S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S2),11(I4S2),44(I3S3),33(I1S1)/22
        -- PAYLOAD MEMORY:     11(I3S2),0(I4S2),22(I3S3),44(I1S1),33(I1S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        -- NOTE: Samples are removed in INSTANCE presentation order
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(17 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0]", INFO);
        Log("R0,R5: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1,I4 W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1,I4 W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(18 sec);
        
        -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER]
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(19 sec);
        
        -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1]", INFO);
        Log("R0,R5: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,5);
        cc.src_timestamp    := gen_duration(20 sec);
        
        -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1]", INFO);
        Log("R0,R5: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W0:I1 W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(21 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2)/0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2)/0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(22 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2]", INFO);
        Log("R0,R5: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2)/0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2)/0,44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(23 sec);
        
        -- TEST: FILTER SAMPLE [KNOWN INSTANCE]
        -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3)/44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3)/44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(24 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3)/44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3)/44,11,33
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,10);
        cc.src_timestamp    := gen_duration(25 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_inst(kh4, mem(0));
        remove_inst(kh4, mem(5));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3),44(I2S1)/11,33
        -- PAYLOAD MEMORY:     44(I2S1)/33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S2),0(I1S3),44(I2S1)/11,33
        -- PAYLOAD MEMORY:     44(I2S1)/33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/11,33,22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11,
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/11,33,22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11,
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(26 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4)/33,22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11,
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4)/33,22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11,
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(27 sec);
        
        -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5)/22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5)/22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(28 sec);
        
        -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1]", INFO);
        Log("R0,R5: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5)/22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5)/22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(10 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R0: ACCEPTED", DEBUG);
        Log("R5: DROPPED [Timestamp earlier than last read]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5),22(I3S4)/0,44
        -- PAYLOAD MEMORY:     44(I3S4)/33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5)/22,0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,5);
        cc.src_timestamp    := gen_duration(29 sec);
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5),22(I3S4),0(I2S2)/44
        -- PAYLOAD MEMORY:     44(I3S4)/33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S4),33(I1S5),22(I2S2)/0,44
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/44,11,33,22,0
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,44,11,33,22
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(30 sec);
        
        -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE]
        
        Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO);
        Log("R0,R5: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 0
        ind <= 0;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 5
        ind <= 5;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S1)/11,33,22,0
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I4S1)/44,11,33,22
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R0: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 0
        ind <= 0;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 5
        ind <= 5;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 0
        AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S1)/11,33,22,0
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 5
        AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I4S1)/44,11,33,22
        -- PAYLOAD MEMORY:     -/44,33,0,22,11
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("*READER 1 / READER 2 / READER 3*", INFO);
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 0, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22,33,44
        -- PAYLOAD MEMORY:     -/0,11,22,33,44
        -- INSTANCE MEMORY:    -/0,13,26
        -- ISTATE: -
        -- WRITER: -
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 0, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22,33,44
        -- PAYLOAD MEMORY:     -/0,11,22,33,44
        -- INSTANCE MEMORY:    -/0,13,26
        -- ISTATE: -
        -- WRITER: -
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 0, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22,33,44
        -- PAYLOAD MEMORY:     -/0,11,22,33,44
        -- INSTANCE MEMORY:    -/0,13,26
        -- ISTATE: -
        -- WRITER: -
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(1 sec);
        
        -- TEST: NORMAL ADD_CACHE_CHANGE
        -- TEST: SAMPLE WITH ALIGNED PAYLOAD
        -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE]
        -- TEST: SAMPLE WITH KEY_HASH
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1)/11,22,33,44
        -- PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1)/11,22,33,44
        -- PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1)/11,22,33,44
        -- PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := HANDLE_NIL;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(2 sec);
        
        -- TEST: SAMPLE WITHOUT KEY_HASH
        -- TEST: NORMAL SAMPLE [KNOWN INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        s.inst          := kh1;
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2)/22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2)/22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I1S1),11(I1S2)/22,33,44
        -- PAYLOAD MEMORY:     0(I1S1),11(I1S2)/22,33,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,18);
        cc.src_timestamp    := gen_duration(3 sec);
        
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
        -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I1S2),22(I1S3)/33,44,0
        -- PAYLOAD MEMORY:     11(I1S2),22(I1S3),33(I1S3)/0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3)/33,44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3)/33,44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3)/33,44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:ALIVE
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(4 sec);
        
        -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE]
        -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH]
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        s.inst          := kh1;
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4)/44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:DISPOSED 
        -- WRITER: W0:I1
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4)/44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:DISPOSED 
        -- WRITER: W0:I1
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4)/44,0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3)/11,0,44
        -- INSTANCE MEMORY:    0(I1)/13,26
        -- ISTATE: I1:DISPOSED 
        -- WRITER: W0:I1
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,20);
        cc.src_timestamp    := gen_duration(5 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1)/0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44
        -- INSTANCE MEMORY:    13(I2),0(I1)/26
        -- ISTATE: I1:DISPOSED, I2:ALIVE
        -- WRITER: W0:I1, W1:I2
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1)/0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44
        -- INSTANCE MEMORY:    13(I2),0(I1)/26
        -- ISTATE: I1:DISPOSED, I2:ALIVE
        -- WRITER: W0:I1, W1:I2
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1)/0,11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44
        -- INSTANCE MEMORY:    13(I2),0(I1)/26
        -- ISTATE: I1:DISPOSED, I2:ALIVE
        -- WRITER: W0:I1, W1:I2
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(6 sec);
        
        -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [UNKNOWN WRITER]
        
        Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 2]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := NOT_READ_SAMPLE_STATE;
        dds.istate      := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),44(I2S1),0(I3S1)/11,33
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),44(I2S1),0(I3S1)/11,33
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I1S3),44(I2S1),0(I3S1)/11,33
        -- PAYLOAD MEMORY:     22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/-
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(7 sec);
        
        -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,10);
        cc.src_timestamp    := gen_duration(8 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := REJECTED;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I1, W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
        
        Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 0]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 0;
        change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(1));
        change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(2));
        change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(3));
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W1:I2,I3, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W1:I2,I3, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2)/33,22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33
        -- INSTANCE MEMORY:    26(I3),13(I2),0(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W1:I2,I3, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        remove_inst(kh1, mem(1));
        remove_inst(kh1, mem(2));
        remove_inst(kh1, mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22
        -- PAYLOAD MEMORY:     11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(9 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1)/22,44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,10);
        cc.src_timestamp    := gen_duration(10 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(11 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44
        -- PAYLOAD MEMORY:     44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE
        -- WRITER: W1:I2,I3,I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
        -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
        
        Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 1]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 1;
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.src_timestamp    := check_time;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        remove_sample(1,mem(1));
        remove_sample(1,mem(2));
        remove_sample(1,mem(3));
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.src_timestamp    := check_time;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R1,R2,R3: DDS Operation TAKE_INSTANCE [Instance 2, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE_INSTANCE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        dds.inst        := kh2;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2)/44,33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(12 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33
        -- PAYLOAD MEMORY:     22(I3S2),11(I4S2),44(I3S3)/33,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I2)/-
        -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W2:I3
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(13 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE]
        -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_inst(kh2,mem(1));
        remove_inst(kh2,mem(2));
        remove_inst(kh2,mem(3));
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11
        -- PAYLOAD MEMORY:     11(I4S2),44(I3S3),33(I1S1)/22,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11
        -- PAYLOAD MEMORY:     11(I4S2),44(I3S3),33(I1S1)/22,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11
        -- PAYLOAD MEMORY:     11(I4S2),44(I3S3),33(I1S1)/22,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(14 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4)/11,0
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,15);
        cc.src_timestamp    := gen_duration(15 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44
        -- PAYLOAD MEMORY:     44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/-
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,10);
        cc.src_timestamp    := gen_duration(16 sec);
        
        -- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove)
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_sample(1,mem(1));
        remove_sample(1,mem(2));
        remove_sample(1,mem(3));
        remove_sample(0,mem(1));
        remove_sample(0,mem(2));
        remove_sample(0,mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,30);
        cc.src_timestamp    := gen_duration(17 sec);
        
        -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 0, Aligned Payload (3 Slots)]", INFO);
        Log("R1,R2,R3: REJECTED [Payload memory Full]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3)/0,33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS
        -- WRITER: W0:I1, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := HANDLE_NIL;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(18 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        s.inst          := kh4;
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33
        -- PAYLOAD MEMORY:     22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(19 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0]", INFO);
        Log("R1,R2,R3: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1,I4 W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1,I4 W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1,I4 W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(20 sec);
        
        -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER]
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(21 sec);
        
        -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1]", INFO);
        Log("R1,R2,R3: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,5);
        cc.src_timestamp    := gen_duration(22 sec);
        
        -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1]", INFO);
        Log("R1,R2,R3: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/33,11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W0:I1, W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(23 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(24 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2]", INFO);
        Log("R1,R2,R3: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4)/11,22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(25 sec);
        
        -- TEST: FILTER SAMPLE [KNOWN INSTANCE]
        -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(26 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5)/22,44,0
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,10);
        cc.src_timestamp    := gen_duration(27 sec);
        
        -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        remove_inst(kh4, mem(1));
        remove_inst(kh4, mem(2));
        remove_inst(kh4, mem(3));
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5),22(I2S1)/44,0
        -- PAYLOAD MEMORY:     44(I2S1)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5),22(I2S1)/44,0
        -- PAYLOAD MEMORY:     44(I2S1)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      33(I1S4),11(I1S5),22(I2S1)/44,0
        -- PAYLOAD MEMORY:     44(I2S1)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/44,0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/44,0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/44,0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(28 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6)/0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6)/0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6)/0,33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh1;
        cc.payload          := gen_payload(kh1,5);
        cc.src_timestamp    := gen_duration(29 sec);
        
        -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := ALIVE_FILTERED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(30 sec);
        
        -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1]", INFO);
        Log("R1,R2,R3: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7)/33,11,22
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.instance         := kh3;
        cc.payload          := gen_payload(kh3,10);
        cc.src_timestamp    := gen_duration(10 sec);
        
        -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5)/11,22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5)/11,22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5)/11,22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE
        -- WRITER: W0:I2, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.instance         := kh2;
        cc.payload          := gen_payload(kh2,5);
        cc.src_timestamp    := gen_duration(31 sec);
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22
        -- PAYLOAD MEMORY:     44(I3S5)/11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I2),13(I1)/-
        -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
        -- WRITER: W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.instance         := kh4;
        cc.payload          := gen_payload(kh4,5);
        cc.src_timestamp    := gen_duration(32 sec);
        
        -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE]
        
        Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO);
        Log("R1,R2,R3: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        rtps.ret_code   := OK;
        -- READER 1
        ind <= 1;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 2
        ind <= 2;
        start_rtps;
        wait_on_sig(rtps_done);
        -- READER 3
        ind <= 3;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 4;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 1
        ind <= 1;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 2
        ind <= 2;
        start_dds;
        wait_on_sig(dds_done);
        -- READER 3
        ind <= 3;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 1
        AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 2
        AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        -- READER 3
        AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(I4S1)/44,0,33,11
        -- PAYLOAD MEMORY:     -/44,11,0,22,33
        -- INSTANCE MEMORY:    26(I3),0(I4),13(I1)/-
        -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
        -- WRITER: W1:I4, W2:I1,I3
        
        AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        Log("*READER 4*", INFO);
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: -
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(1 sec);
        
        -- TEST: NORMAL ADD_CACHE_CHANGE
        -- TEST: NORMAL SAMPLE
        -- TEST: SAMPLE WITH ALIGNED PAYLOAD
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S1)/11,22
        -- PAYLOAD MEMORY:     0(S1)/10,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,27);
        cc.src_timestamp    := gen_duration(2 sec);
        
        -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)]", INFO);
        Log("R4: REJECTED [Payload Memory exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S1)/11,22
        -- PAYLOAD MEMORY:     0(S1)/10,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(3 sec);
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S1),11(S2)/22
        -- PAYLOAD MEMORY:     0(S1),10(S2)/20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(4 sec);
        
        -- TEST: ADD SAMPLE ON MAX_SAMPLES
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S1),11(S2)/22
        -- PAYLOAD MEMORY:     0(S1),10(S2)/20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,11
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.src_timestamp    := gen_duration(5 sec);
        
        -- TEST: DISPOSE SAMPLE
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S3)/0,11
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: DISPOSED
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.src_timestamp    := gen_duration(6 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S3)/0,11
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: DISPOSED
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE_FILTERED;
        cc.src_timestamp    := gen_duration(7 sec);
        
        -- TEST: FILTER SAMPLE
        -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 0]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S3),0(S4)/11
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/11,22,0
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,27);
        cc.src_timestamp    := gen_duration(8 sec);
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(S5)/22,0
        -- PAYLOAD MEMORY:     10(S5),0(S5),20(S5)/-
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(9 sec);
        
        -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: REJECTED [Payload Memory Full]", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := REJECTED;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(S5)/22,0
        -- PAYLOAD MEMORY:     10(S5),0(S5),20(S5)/-
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [UNKNOWN WRITER]
        
        Log("R4: RTPS Operation REMOVE_WRITER [Writer 1]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(S5)/22,0
        -- PAYLOAD MEMORY:     10(S5),0(S5),20(S5)/-
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,11
        -- PAYLOAD MEMORY:     -/10,0,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(10 sec);
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S6)/0,11
        -- PAYLOAD MEMORY:     10(S6)/0,20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(11 sec);
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S6),0(S7)/11
        -- PAYLOAD MEMORY:     10(S6),0(S7)/20
        -- ISTATE: ALIVE
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- TEST: REMOVE_WRITER [KNOWN WRITER]
        -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
        -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
        
        Log("R4: RTPS Operation REMOVE_WRITER [Writer 0]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := REMOVE_WRITER;
        rtps.writer_pos := 0;
        change_istate(HANDLE_NIL, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(4));
        rtps.ret_code   := OK;
        -- READER 4
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S6),0(S7)/11
        -- PAYLOAD MEMORY:     10(S6),0(S7)/20
        -- ISTATE: NO_WRITERS
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := TRUE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.src_timestamp    := check_time;
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S7),11(S8)/22
        -- PAYLOAD MEMORY:     0(S7)/10,20
        -- ISTATE: NO_WRITERS
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 1;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(S8)/22,0
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: NO_WRITERS
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE_FILTERED;
        cc.src_timestamp    := gen_duration(12 sec);
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 1]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      11(S8),22(S9)/0
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: ALIVE
        -- WRITER: W1
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: ALIVE
        -- WRITER: W1
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.src_timestamp    := gen_duration(13 sec);
        
        -- TEST: UNREGISTER SAMPLE [UNKNOWN WRITER]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/0,11,22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: ALIVE
        -- WRITER: W1
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.src_timestamp    := gen_duration(14 sec);
        
        -- TEST: UNREGISTER SAMPLE [KNOWN WRITER]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 1]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        s               := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S10)/11,22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: NO_WRITERS
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.src_timestamp    := gen_duration(15 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S10)/11,22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: NO_WRITERS
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_DISPOSED;
        cc.src_timestamp    := gen_duration(16 sec);
        
        -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        s               := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      0(S10),11(S11)/22
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: DISPOSED
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := TAKE;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,11
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: DISPOSED
        -- WRITER: W0
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := NOT_ALIVE_UNREGISTERED;
        cc.src_timestamp    := gen_duration(17 sec);
        
        -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO);
        Log("R4: DROPPED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 0;
        rtps.ret_code   := OK;
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      -/22,0,11
        -- PAYLOAD MEMORY:     -/0,10,20
        -- ISTATE: DISPOSED
        -- WRITER: -
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,6);
        cc.src_timestamp    := gen_duration(18 sec);
        
        -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 2, Unaligned Payload (1 Slot)]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 2;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S12)/0,11
        -- PAYLOAD MEMORY:     0(S12)/10,20
        -- ISTATE: ALIVE
        -- WRITER: W2
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        cc                  := DEFAULT_CACHE_CHANGE;
        cc.serialized_key   := FALSE;
        cc.kind             := ALIVE;
        cc.payload          := gen_payload(KEY_HASH_NIL,9);
        cc.src_timestamp    := gen_duration(19 sec);
        
        -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
        
        Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 1, Aligned Payload]", INFO);
        Log("R4: ACCEPTED", DEBUG);
        rtps            := DEFAULT_RTPS_READER_TEST;
        rtps.opcode     := ADD_CACHE_CHANGE;
        rtps.cc         := cc;
        rtps.writer_pos := 1;
        rtps.ret_code   := OK;
        s               := to_sample(cc,ALIVE_INSTANCE_STATE);
        add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
        -- READER 4
        ind <= 4;
        start_rtps;
        wait_on_sig(rtps_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S12),0(S13)/11
        -- PAYLOAD MEMORY:     0(S12),10(S13)/20
        -- ISTATE: ALIVE
        -- WRITER: W1, W2
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
        
        -- VALIDATE STATE
        
        Log("R4: DDS Operation READ [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
        dds             := DEFAULT_DDS_READER_TEST;
        dds.opcode      := READ;
        dds.max_samples := 2;
        dds.sstate      := ANY_SAMPLE_STATE;
        dds.istate      := ANY_INSTANCE_STATE;
        dds.vstate      := ANY_VIEW_STATE;
        -- READER 4
        ind <= 4;
        start_dds;
        wait_on_sig(dds_done);
        wait_on_idle;
        -- READER 4
        AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE);
        AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE);
        -- SAMPLE MEMORY:      22(S12),0(S13)/11
        -- PAYLOAD MEMORY:     0(S12),10(S13)/20
        -- ISTATE: ALIVE
        -- WRITER: W1, W2
        
        AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
        
        wait_on_completion;
        TranscriptOpen(RESULTS_FILE, APPEND_MODE);
        SetTranscriptMirror;
        ReportAlerts;
        TranscriptClose;
        std.env.stop;
        wait;
    end process;
    
    clock_prc : process
    begin
        clk <= '0';
        wait for 25 ns;
        clk <= '1';
        wait for 25 ns;
    end process;
    
    dds_prc : process(all)
        variable col : COLLECTION_TYPE := DEFAULT_COLLECTION;
    begin
        if rising_edge(clk) then
            dds_done    <= '0';
            case (dds_stage ) is
                when IDLE =>
                    if (dds_start  = '1') then
                        dds_stage   <= START;
                    else
                        dds_done    <= '1';
                    end if;
                when START =>
                    if (ack_dds(ind) = '1') then
                        dds_stage   <= DONE;
                        dds_cnt     <= 0;
                    end if;
                when DONE =>
                    if (done_dds(ind) = '1') then
                        AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code);
                        case (dds.ret_code) is
                            when RETCODE_OK =>
                                gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS);
                                dds_stage   <= CHECK_SI;
                                dds_cnt     <= 0;
                            when others =>
                                dds_stage   <= IDLE;
                        end case;
                    end if;
                when CHECK_SI =>
                    if (si_valid(ind) = '1') then
                        AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate);
                        AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate);
                        AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate);
                        AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts));
                        AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst));
                        AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL));
                        AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH)));
                        AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH)));
                        AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH)));
                        AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH)));
                        AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH)));
                        if (sample_info(ind).valid_data = '1') then
                            AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected");
                            dds_stage   <= CHECK_DATA;
                            dds_cnt2    <= 0;
                        else
                            AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected");
                            if (dds_cnt = col.len-1) then
                                -- DONE
                                dds_stage   <= WAIT_EOC;
                            else
                                dds_cnt     <= dds_cnt + 1;
                            end if;
                        end if;
                    end if;
                    AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high");
                when CHECK_DATA =>
                    if (valid_out_dds(ind) = '1') then
                        AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2));
                        dds_cnt2    <= dds_cnt2 + 1;
                        if (dds_cnt2  = col.s(dds_cnt).data.length-1) then
                            AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR);
                            if (dds_cnt = col.len-1) then
                                -- DONE
                                dds_stage   <= WAIT_EOC;
                            else
                                dds_stage   <= CHECK_SI;
                                dds_cnt     <= dds_cnt + 1;
                            end if;
                        end if;
                    end if;
                when WAIT_EOC =>
                    if (eoc(ind) = '1') then
                        dds_stage   <= IDLE;
                    end if;
            end case;
        end if;
        
        -- DEFAULT
        start_dds           <= (others => '0');
        opcode_dds          <= (others => NOP);
        instance_state_dds  <= (others => ANY_INSTANCE_STATE);
        view_state_dds      <= (others => ANY_VIEW_STATE);
        sample_state_dds    <= (others => ANY_SAMPLE_STATE);
        instance_handle_dds <= (others => HANDLE_NIL);
        max_samples_dds     <= (others => (others => '0'));
        get_data_dds        <= (others => '0');
        ready_out_dds       <= (others => '0');
        
        
        case (dds_stage ) is
            when START =>
                start_dds(ind)              <= '1';
                opcode_dds(ind)             <= dds.opcode;
                instance_state_dds(ind)     <= dds.istate;
                view_state_dds(ind)         <= dds.vstate;
                sample_state_dds(ind)       <= dds.sstate;
                instance_handle_dds(ind)    <= dds.inst;
                max_samples_dds(ind)        <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH));
            when CHECK_SI =>
                if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then
                    get_data_dds(ind)   <= '1';
                end if;
            when CHECK_DATA =>
                ready_out_dds(ind)  <= '1';
            when others =>
                null;
        end case;
    end process;
    
    rtps_prc : process(all)
        variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
    begin
        if rising_edge(clk) then
            rtps_done    <= '0';
            case (rtps_stage) is
                when IDLE =>
                    if (rtps_start = '1') then
                        rtps_stage   <= START;
                    else
                        rtps_done    <= '1';
                    end if;
                when START =>
                    if (ack_rtps(ind) = '1') then
                        case (rtps.opcode) is
                            when ADD_CACHE_CHANGE =>
                                gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus);
                                rtps_stage  <= PUSH;
                            when others =>
                                rtps_stage  <= DONE;
                        end case;
                    end if;
                when PUSH =>
                    if (ready_in_rtps(ind) = '1') then
                        rtps_cnt    <= rtps_cnt + 1;
                        if (rtps_cnt = stimulus.length-1) then
                            rtps_stage  <= DONE;
                        end if;
                    end if;
                when DONE =>
                    if (done_rtps(ind) = '1') then
                        AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
                        rtps_stage   <= IDLE;
                    end if;
            end case;
        end if;
        
        -- DEFAULT
        start_rtps          <= (others => '0');
        opcode_rtps         <= (others => NOP);
        valid_in_rtps       <= (others => '0');
        last_word_in_rtps   <= (others => '0');
        data_in_rtps        <= (others => (others => '0'));
        
        case (rtps_stage) is
            when START =>
                start_rtps(ind)     <= '1';
                opcode_rtps(ind)    <= rtps.opcode;
                case (rtps.opcode) is
                    when REMOVE_WRITER =>
                        data_in_rtps(ind)   <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH));
                    when others =>
                        null;
                end case;
            when PUSH =>
                valid_in_rtps(ind)      <= '1';
                data_in_rtps(ind)       <= stimulus.data(rtps_cnt);
                last_word_in_rtps(ind)  <= stimulus.last(rtps_cnt);
            when others =>
                null;
        end case;
    end process;
    
    watchdog : process
    begin
        wait for 2 ms;
        Alert("Test timeout", FAILURE);
        std.env.stop;
    end process;
    
end architecture;