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#
# Copyright (C) 2020  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
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#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 13:33:09  November 02, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		top_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
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# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY test_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09  NOVEMBER 02, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE ../test7.vhd -hdl_version VHDL_2008
set_global_assignment -name SDC_FILE ../top.sdc
set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Fibonacci.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_client.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_client.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_client.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_feedback_pub.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_feedback_sub.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_pub.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_action_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/AddTwoInts.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_server.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_client.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_time_converter.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_static_discovery_writer.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_config.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_interface.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_interface.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/verbatim_key_hash_generator.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/key_hash_generator.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/key_holder.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../rtps_reader_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_reader.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../rtps_writer_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_discovery_module.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test2.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/mult_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/mult_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/mult.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dp_mem_ctrl.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_config_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/dds_user_config.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../syn_ros_action_config.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top