-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;
use work.rtps_config_package.all;

-- Test synthesis of array indexing

entity test5 is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        input           : in std_logic_vector(31 downto 0);
        input2          : in std_logic_vector(31 downto 0);
        output          : out std_logic_vector(7 downto 0)
    );
end entity;

architecture arch of test5 is
    
begin
    
    process (all)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                output  <= (others => '0');
            else
                output  <= get_sub_vector(input, to_integer(unsigned(input2(1 downto 0))), 8, TRUE);
            end if;
        end if;
    end process;

end architecture;
