-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;

entity rtps_reader_syn is
    port (
        -- SYSTEM
        clk                 : in std_logic;
        reset               : in std_logic;
        time                : in TIME_TYPE;
        -- FROM RTPS HANDLER (USER TRAFFIC)
        empty_user          : in std_logic;
        rd_user             : out std_logic;
        data_in_user        : in std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_in_user   : in std_logic;
        -- FROM RTPS BUILTIN ENDPOINT (META TRAFFIC)
        empty_meta          : in std_logic;
        rd_meta             : out std_logic;
        data_in_meta        : in std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_in_meta   : in std_logic;
        -- RTPS OUTPUT
        full_ro             : in std_logic;
        wr_ro               : out std_logic;
        data_out_ro         : out std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_out_ro    : out std_logic;
        -- TO HISTORY CACHE
        start_hc            : out std_logic;
        opcode_hc           : out HISTORY_CACHE_OPCODE_TYPE;
        ack_hc              : in std_logic;
        done_hc             : in std_logic;
        ret_hc              : in HISTORY_CACHE_RESPONSE_TYPE;
        data_out_hc         : out std_logic_vector(WORD_WIDTH-1 downto 0);
        valid_out_hc        : out std_logic;
        ready_out_hc        : in std_logic;
        last_word_out_hc    : out std_logic
    );
end entity;

architecture arch of rtps_reader_syn is
begin
    
    if_gen : if (NUM_READERS > 0) generate
        syn_inst : entity work.rtps_reader(arch)
            generic map (
                ENTITYID                    => ENTITYID(0),
                RELIABILITY_QOS             => ENDPOINT_CONFIG(0).RELIABILITY_QOS,
                LIVELINESS_QOS              => ENDPOINT_CONFIG(0).LIVELINESS_QOS,
                DURABILITY_QOS              => ENDPOINT_CONFIG(0).DURABILITY_QOS,
                HEARTBEAT_RESPONSE_DELAY    => ENDPOINT_CONFIG(0).HEARTBEAT_RESPONSE_DELAY,
                HEARTBEAT_SUPPRESSION_DELAY => ENDPOINT_CONFIG(0).HEARTBEAT_SUPPRESSION_DELAY,
                LEASE_DURATION              => ENDPOINT_CONFIG(0).LEASE_DURATION,
                WITH_KEY                    => ENDPOINT_CONFIG(0).WITH_KEY
            )
            port map (
                clk                 => clk,
                reset               => reset,
                time                => time,
                empty_user          => empty_user,
                rd_user             => rd_user,
                data_in_user        => data_in_user,
                last_word_in_user   => last_word_in_user,
                empty_meta          => empty_meta,
                rd_meta             => rd_meta,
                data_in_meta        => data_in_meta,
                last_word_in_meta   => last_word_in_meta,
                full_ro             => full_ro,
                wr_ro               => wr_ro,
                data_out_ro         => data_out_ro,
                last_word_out_ro    => last_word_out_ro,
                start_hc            => start_hc,
                opcode_hc           => opcode_hc,
                ack_hc              => ack_hc,
                done_hc             => done_hc,
                ret_hc              => ret_hc,
                data_out_hc         => data_out_hc,
                valid_out_hc        => valid_out_hc,
                ready_out_hc        => ready_out_hc,
                last_word_out_hc    => last_word_out_hc
            );
    end generate;

end architecture;
