-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY lpm;
USE lpm.all;

architecture altera of mult is
    function gen_hint return string is
    begin
        if (DATAB_CONST) then
            return "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
        else
            return "MAXIMIZE_SPEED=5";
        end if;
    end function;
    
    component lpm_mult
        generic (
            lpm_hint		    : string;
            lpm_pipeline		: natural;
            lpm_representation	: string;
            lpm_type		    : string;
            lpm_widtha		    : natural;
            lpm_widthb		    : natural;
            lpm_widthp		    : natural
        );
        port (
            clock	: IN std_logic;
            dataa	: IN std_logic_vector(DATAA_WIDTH-1 DOWNTO 0);
            datab	: IN std_logic_vector(DATAB_WIDTH-1 DOWNTO 0);
            result	: OUT std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 DOWNTO 0)
        );
	END COMPONENT;
    
begin
    
    lpm_mult_component : lpm_mult
        generic map (
            lpm_hint            => gen_hint,
            lpm_pipeline        => PIPELINE_STAGES,
            lpm_representation  => "UNSIGNED",
            lpm_type            => "LPM_MULT",
            lpm_widtha          => DATAA_WIDTH,
            lpm_widthb          => DATAB_WIDTH,
            lpm_widthp          => DATAA_WIDTH+DATAB_WIDTH
        )
        port map (
            clock   => clk,
            dataa   => dataa,
            datab   => datab,
            result  => result
        );

end architecture;