-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.Type1_package.all;

entity dds_reader_syn is
    port (
        -- SYSTEM
        clk                             : in std_logic;
        reset                           : in std_logic;
        time                            : in TIME_TYPE;
        -- FROM RTPS ENDPOINT
        start_rtps                      : in std_logic;
        opcode_rtps                     : in HISTORY_CACHE_OPCODE_TYPE;
        ack_rtps                        : out std_logic;
        done_rtps                       : out std_logic;
        ret_rtps                        : out HISTORY_CACHE_RESPONSE_TYPE;
        data_in_rtps                    : in std_logic_vector(WORD_WIDTH-1 downto 0);
        valid_in_rtps                   : in std_logic;
        ready_in_rtps                   : out std_logic;
        last_word_in_rtps               : in std_logic;
        -- TO USER ENTITY
        start_dds                       : in std_logic;
        ack_dds                         : out std_logic;
        opcode_dds                      : in DDS_READER_OPCODE_TYPE;
        instance_state_dds              : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
        view_state_dds                  : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
        sample_state_dds                : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
        instance_handle_dds             : in INSTANCE_HANDLE_TYPE;
        max_samples_dds                 : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
        get_data_dds                    : in std_logic;
        done_dds                        : out std_logic;
        return_code_dds                 : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
        ready_out_dds                   : in std_logic;
        valid_out_dds                   : out std_logic;
        data_out_dds                    : out std_logic_vector(WORD_WIDTH-1 downto 0);
        last_word_out_dds               : out std_logic;
        -- Sample Info
        sample_info                     : out SAMPLE_INFO_TYPE;
        sample_info_valid               : out std_logic;
        sample_info_ack                 : in std_logic;
        eoc                             : out std_logic;
        -- Communication Status
        status                          : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0)
    );
end entity;

architecture arch of dds_reader_syn is
begin
    
    if_gen : if (NUM_READERS > 0) generate
        syn_inst : entity work.dds_reader(arch)
            generic map (
                TIME_BASED_FILTER_QOS       => ENDPOINT_CONFIG(0).TIME_BASED_FILTER_QOS,
                DEADLINE_QOS                => ENDPOINT_CONFIG(0).DEADLINE_QOS,
                MAX_INSTANCES               => ENDPOINT_CONFIG(0).MAX_INSTANCES,
                MAX_SAMPLES_PER_INSTANCE    => ENDPOINT_CONFIG(0).MAX_SAMPLES_PER_INSTANCE,
                MAX_SAMPLES                 => ENDPOINT_CONFIG(0).MAX_SAMPLES,
                HISTORY_QOS                 => ENDPOINT_CONFIG(0).HISTORY_QOS,
                RELIABILITY_QOS             => ENDPOINT_CONFIG(0).RELIABILITY_QOS,
                PRESENTATION_QOS            => ENDPOINT_CONFIG(0).PRESENTATION_QOS,
                DESTINATION_ORDER_QOS       => ENDPOINT_CONFIG(0).DESTINATION_ORDER_QOS,
                COHERENT_ACCESS             => ENDPOINT_CONFIG(0).COHERENT_ACCESS,
                ORDERED_ACCESS              => ENDPOINT_CONFIG(0).ORDERED_ACCESS,
                WITH_KEY                    => ENDPOINT_CONFIG(0).WITH_KEY,
                PAYLOAD_FRAME_SIZE          => MAX_TYPE1_SIZE
            )
            port map (
                clk                             => clk,
                reset                           => reset,
                time                            => time,
                start_rtps                      => start_rtps,
                opcode_rtps                     => opcode_rtps,
                ack_rtps                        => ack_rtps,
                done_rtps                       => done_rtps,
                ret_rtps                        => ret_rtps,
                data_in_rtps                    => data_in_rtps,
                valid_in_rtps                   => valid_in_rtps,
                ready_in_rtps                   => ready_in_rtps,
                last_word_in_rtps               => last_word_in_rtps,
                start_dds                       => start_dds,
                ack_dds                         => ack_dds,
                opcode_dds                      => opcode_dds,
                instance_state_dds              => instance_state_dds,
                view_state_dds                  => view_state_dds,
                sample_state_dds                => sample_state_dds,
                instance_handle_dds             => instance_handle_dds,
                max_samples_dds                 => max_samples_dds,
                get_data_dds                    => get_data_dds,
                done_dds                        => done_dds,
                return_code_dds                 => return_code_dds,
                ready_out_dds                   => ready_out_dds,
                valid_out_dds                   => valid_out_dds,
                data_out_dds                    => data_out_dds,
                last_word_out_dds               => last_word_out_dds,
                sample_info                     => sample_info,
                sample_info_valid               => sample_info_valid,
                sample_info_ack                 => sample_info_ack,
                eoc                             => eoc,
                status                          => status
            );
    end generate;
    
end architecture;
