-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;

-- Test how FSM states guarded with a synthesis guard are handled.

entity test3 is
    generic (
        BUILD : boolean := FALSE
    );
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        input           : in std_logic_vector(31 downto 0);
        output          : out std_logic_vector(31 downto 0)
    );
end entity;

architecture arch of test3 is
    
    type STAGE_TYPE is (IDLE, STATE1, STATE2);
    
    signal stage, stage_next : STAGE_TYPE := IDLE;
    
begin
    
    process(all)
    begin
        stage_next  <= stage;
        output      <= (others => '0');
        
        case (stage) is
            when IDLE =>
                case (input) is
                    when x"00000000" =>
                        if (BUILD) then
                            stage_next  <= STATE1;
                        else
                            stage_next  <= STATE2;
                        end if;
                    when x"00000001" =>
                        stage_next  <= STATE2;
                    when others =>
                        null;
                end case;
            when STATE1 =>
                if (BUILD) then
                    stage_next  <= IDLE;
                    output      <= x"DEADBEEF";
                end if;
            when STATE2 =>
                stage_next  <= IDLE;
                output      <= x"BEEFDEAD";
            when others =>
                null;
        end case;
    end process;
    
    sync : process(all)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                stage   <= IDLE;
            else
                stage   <= stage_next;
            end if;
        end if;
    end process;

end architecture;
