library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.test_package.all;
use work.rtps_package.all;

-- TODO: Remove alignment logic for RTPS Submessages, since all Submessages are 32-bit aligned
-- Checksum has to be checked before

entity test is
    generic (
        BUILD : boolean := FALSE
    );
    port (
        clk             : in std_logic;                                     -- Input Clock
        reset           : in std_logic;                                     -- Synchronous Reset
        input           : in std_logic_vector(31 downto 0);
        output          : out std_logic_vector(31 downto 0)
    );
end entity;

architecture arch of test is
    
    type STAGE_TYPE is (IDLE, STATE1, STATE2);
    
    signal test_var : natural := 0;
    signal stage, stage_next : STAGE_TYPE := IDLE;
    
    function bitmap_converter(input : std_logic_vector) return natural is
        variable ret : natural := 0;
    begin
        for i in 0 to input'length-1 loop
            ret := ret + 1;
            if (input(i) = '1') then
                exit;
            end if;
        end loop;
        return ret;
    end function;
    
begin
    
    output <= std_logic_vector(to_unsigned(bitmap_converter(input), output'length));
    
--    process(all)
--    begin
--        stage_next  <= stage;
--        output      <= (others => '0');
--        
--        case (stage) is
--            when IDLE =>
--                case (input) is
--                    when x"00000000" =>
--                        if (BUILD) then
--                            stage_next  <= STATE1;
--                        else
--                            stage_next  <= STATE2;
--                        end if;
--                    when x"00000001" =>
--                        stage_next  <= STATE2;
--                    when others =>
--                        null;
--                end case;
--            when STATE1 =>
--                if (BUILD) then
--                    stage_next  <= IDLE;
--                    output      <= x"DEADBEEF";
--                end if;
--            when STATE2 =>
--                stage_next  <= IDLE;
--                output      <= x"BEEFDEAD";
--            when others =>
--                null;
--        end case;
--    end process;
    
--    sync : process(all)
--    begin
--        if rising_edge(clk) then
--            if (reset = '1') then
--                stage   <= IDLE;
--            else
--                stage   <= stage_next;
--            end if;
--        end if;
--    end process;

end architecture;
