    SAMPLE MEMORY:      -/0,9,18,27,36
    PAYLOAD MEMORY:     -/0,11,22,33,44
    INSTANCE MEMORY:    -/0,8,16
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)
DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S1)/9,18,27,36
    PAYLOAD MEMORY:     0(I1S1)/11,22,33,44
    INSTANCE MEMORY:    0(I1)/8,16
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 1)
DDS Operation WRITE [TS 1s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S1),9(I1S2)/18,27,36
    PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
    INSTANCE MEMORY:    0(I1)/8,16
DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered)
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
    SAMPLE MEMORY:      0(I1S1),9(I1S2)/18,27,36
    PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2)/33,44
    INSTANCE MEMORY:    8(I2),0(I1)/16
DDS Operation DISPOSE [TS 3s, Instance 1] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S1),9(I1S2),18(I2S3)/27,36
    PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2),33(I2S3)/44
    INSTANCE MEMORY:    8(I2),0(I1)/16
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 3)
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 1
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 4s, Instance 1, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S1),9(I1S2),18(I2S3),27(I2S4)/36
    PAYLOAD MEMORY:     0(I1S1),11(I1S2),22(I1S2),33(I2S3),44(I2S4)/-
    INSTANCE MEMORY:    8(I2),0(I1)/16
DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      9(I1S2),18(I2S3),27(I2S4),36(I3S5)/0
    PAYLOAD MEMORY:     11(I1S2),22(I1S2),33(I2S3),44(I2S4),0(I3S5)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      9(I1S2),27(I2S4),36(I3S5),0(I3S6)/18
    PAYLOAD MEMORY:     11(I1S2),22(I1S2),44(I2S4),0(I3S5),33(I3S6)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 2)
RTPS Operation GET_MAX_SN (Expected SN 6)
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 4
RTPS Operation GET_CACHE_CHANGE SN 5
RTPS Operation GET_CACHE_CHANGE SN 6
DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED)
    SAMPLE MEMORY:      27(I2S4),36(I3S5),0(I3S6),18(I1S7)/9
    PAYLOAD MEMORY:     44(I2S4),0(I3S5),33(I3S6),11(I1S7)/22
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 5
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid)
RTPS Operation REMOVE_CACHE_CHANGE SN 5
    SAMPLE MEMORY:      27(I2S4),0(I3S6),18(I1S7)/9,36
    PAYLOAD MEMORY:     44(I2S4),33(I3S6),11(I1S7)/0,22
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED)
    SAMPLE MEMORY:      27(I2S4),0(I3S6),18(I1S7),9(I2S8)/36
    PAYLOAD MEMORY:     44(I2S4),33(I3S6),11(I1S7),0(I2S8),22(I2S8)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 7
DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED)
    SAMPLE MEMORY:      27(I2S4),0(I3S6),9(I2S8),36(I3S9)/18
    PAYLOAD MEMORY:     44(I2S4),33(I3S6),0(I2S8),22(I2S8),11(I3S9)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 9)
RTPS Operation GET_CACHE_CHANGE SN 4
RTPS Operation GET_CACHE_CHANGE SN 6
RTPS Operation GET_CACHE_CHANGE SN 8
RTPS Operation GET_CACHE_CHANGE SN 9
DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED)
    SAMPLE MEMORY:      0(I3S6),9(I2S8),36(I3S9),18(I1S10)/27
    PAYLOAD MEMORY:     33(I3S6),0(I2S8),22(I2S8),11(I3S9),44(I1S10)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 9
DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED)
    SAMPLE MEMORY:      0(I3S6),9(I2S8),18(I1S10),27(I2S11)/36
    PAYLOAD MEMORY:     33(I3S6),0(I2S8),22(I2S8),44(I1S10),11(I2S11)/-
    INSTANCE MEMORY:    16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 6
RTPS Operation ACK_CACHE_CHANGE SN 8
RTPS Operation ACK_CACHE_CHANGE SN 11
DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I1S10),36(I4S12)/0,9,27
    PAYLOAD MEMORY:     44(I1S10),33(I4S12)/11,0,22
    INSTANCE MEMORY:    8(I4),16(I3),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 10)
RTPS Operation GET_MAX_SN (Expected SN 12)
RTPS Operation GET_CACHE_CHANGE SN 10
RTPS Operation GET_CACHE_CHANGE SN 12
DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 10
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12)/0,9,27,18
    PAYLOAD MEMORY:     33(I4S12)/44,11,0,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),0(I2S13)/9,27,18
    PAYLOAD MEMORY:     33(I4S12),44(I2S13)/11,0,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),0(I2S13),9(I2S14)/27,18
    PAYLOAD MEMORY:     33(I4S12),44(I2S13),11(I2S14)/0,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),9(I2S14),27(I2S15)/18,0
    PAYLOAD MEMORY:     33(I4S12),11(I2S14),0(I2S15)/44,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 15
DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),9(I2S14),18(I2S16)/0,27
    PAYLOAD MEMORY:     33(I4S12),11(I2S14),44(I2S16)/0,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 12
DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),18(I2S16),0(I2S17)/27,9
    PAYLOAD MEMORY:     33(I4S12),44(I2S16),0(I2S17)/11,22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation GET_MIN_SN (Expected SN 12)
RTPS Operation GET_MAX_SN (Expected SN 17)
RTPS Operation GET_CACHE_CHANGE SN 12
RTPS Operation GET_CACHE_CHANGE SN 16
RTPS Operation GET_CACHE_CHANGE SN 17
DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),18(I2S16),0(I2S17),27(I4S18)/9
    PAYLOAD MEMORY:     33(I4S12),44(I2S16),0(I2S17),11(I4S178)/22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation NACK_CACHE_CHANGE SN 12
RTPS Operation ACK_CACHE_CHANGE SN 18
DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED)
    SAMPLE MEMORY:      36(I4S12),18(I2S16),0(I2S17),9(I3S19)/27
    PAYLOAD MEMORY:     33(I4S12),44(I2S16),0(I2S17),22(I3S19)/11
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I2S16),0(I2S17),9(I3S19),27(I3S20)/36
    PAYLOAD MEMORY:     44(I2S16),0(I2S17),22(I3S19),11(I3S20)/33
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I2S16),0(I2S17),27(I3S20),36(I3S21)/9
    PAYLOAD MEMORY:     44(I2S16),0(I2S17),11(I3S20),33(I3S21)/22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 16
DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I2S16),0(I2S17),36(I3S21),9(I3S22)/27
    PAYLOAD MEMORY:     44(I2S16),0(I2S17),33(I3S21),22(I3S22)/11
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 22
DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I2S16),0(I2S17),36(I3S21),27(I3S23)/9
    PAYLOAD MEMORY:     44(I2S16),0(I2S17),33(I3S21),11(I3S23)/22
    INSTANCE MEMORY:    0(I2),8(I4),16(I3)/-
RTPS Operation GET_MIN_SN (Expected SN 16)
RTPS Operation GET_MAX_SN (Expected SN 23)
RTPS Operation GET_CACHE_CHANGE SN 21
RTPS Operation GET_CACHE_CHANGE SN 22
RTPS Operation GET_CACHE_CHANGE SN 23
DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (REJECTED: Instance not Registered)
DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      0(I2S17),36(I3S21),27(I3S23),9(I1S24)/18
    PAYLOAD MEMORY:     0(I2S17),33(I3S21),11(I3S23),22(I1S24)/44
    INSTANCE MEMORY:    8(I1),0(I2),16(I3)/-
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 21
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 17
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      36(I3S21),27(I3S23),9(I1S24),18(I4S25)/0
    PAYLOAD MEMORY:     33(I3S21),11(I3S23),22(I1S24),22(I4S25)/0
    INSTANCE MEMORY:    0(I4),8(I1),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 21
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 24
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED)
    SAMPLE MEMORY:      27(I3S23),9(I1S24),18(I4S25),0(I1S26)/36
    PAYLOAD MEMORY:     11(I3S23),22(I1S24),22(I4S25),0(I1S26)/33
    INSTANCE MEMORY:    0(I4),8(I1),16(I3)/-
DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)
DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED)
    SAMPLE MEMORY:      27(I3S23),18(I4S25),0(I1S26),36(I3S27)/9
    PAYLOAD MEMORY:     11(I3S23),22(I4S25),0(I1S26),33(I3S27)/22
    INSTANCE MEMORY:    0(I4),8(I1),16(I3)/-
DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED)
    SAMPLE MEMORY:      18(I4S25),0(I1S26),36(I3S27),9(I3S28)/27
    PAYLOAD MEMORY:     22(I4S25),0(I1S26),33(I3S27),22(I3S28)/11
    INSTANCE MEMORY:    0(I4),8(I1),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 27
RTPS Operation ACK_CACHE_CHANGE SN 28
DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I4S25),0(I1S26),27(I2S29)/36,9
    PAYLOAD MEMORY:     22(I4S25),0(I1S26),11(I2S29)/22,33
    INSTANCE MEMORY:    16(I2),0(I4),8(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 25)
RTPS Operation GET_MAX_SN (Expected SN 29)
RTPS Operation GET_CACHE_CHANGE SN 25
RTPS Operation GET_CACHE_CHANGE SN 26
RTPS Operation GET_CACHE_CHANGE SN 29
DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      18(I4S25),0(I1S26),27(I2S29),36(I2S30)/9
    PAYLOAD MEMORY:     22(I4S25),0(I1S26),11(I2S29),22(I2S30)/33
    INSTANCE MEMORY:    16(I2),0(I4),8(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 25
RTPS Operation ACK_CACHE_CHANGE SN 26
DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S26),27(I2S29),36(I2S30),9(I4S31)/18
    PAYLOAD MEMORY:     0(I1S26),11(I2S29),22(I2S30),33(I4S31)/22
    INSTANCE MEMORY:    16(I2),0(I4),8(I1)/-
RTPS Operation REMOVE_CACHE_CHANGE SN 31
    SAMPLE MEMORY:      0(I1S26),27(I2S29),36(I2S30)/18,9
    PAYLOAD MEMORY:     0(I1S26),11(I2S29),22(I2S30)/33,22
    INSTANCE MEMORY:    16(I2),0(I4),8(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 29
RTPS Operation ACK_CACHE_CHANGE SN 30
DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED)
    SAMPLE MEMORY:      0(I1S26),36(I2S30),18(I2S32)/9,27
    PAYLOAD MEMORY:     0(I1S26),22(I2S30),33(I2S32)/11,22
    INSTANCE MEMORY:    16(I2),0(I4),8(I1)/-