From 1e2a835c027eee077bc1c896cbe5e34db9a84499 Mon Sep 17 00:00:00 2001 From: Greek64 Date: Fri, 11 Mar 2022 10:41:18 +0100 Subject: [PATCH] Change memory format of rtps_writer to use double linked list --- sim/L0_rtps_writer_test1_vbkdp.do | 65 ++ sim/L0_rtps_writer_test1_vrkdp.do | 11 +- src/REF.txt | 6 +- .../Level_0/L0_rtps_writer_test1_vbkdp.vhd | 38 +- .../Level_0/L0_rtps_writer_test1_vrkdp.vhd | 38 +- .../Level_0/L0_rtps_writer_test2_vrkdp.vhd | 77 +- .../Level_1/L1_rtps_writer_test1_tbkdp.vhd | 8 +- .../Level_1/L1_rtps_writer_test1_trkdp.vhd | 96 +- .../Level_1/L1_rtps_writer_test1_vbkdp.vhd | 8 +- .../Level_1/L1_rtps_writer_test1_vrkdp.vhd | 96 +- .../Level_1/L1_rtps_writer_test1_vrksp.vhd | 96 +- .../Level_1/L1_rtps_writer_test1_vrndp.vhd | 96 +- .../Level_1/L1_rtps_writer_test2_vrkdn.vhd | 24 +- .../Level_1/L1_rtps_writer_test2_vrksn.vhd | 24 +- .../Level_1/L1_rtps_writer_test3_vrkdn.vhd | 36 +- src/rtps_test_package.vhd | 4 +- src/rtps_writer.vhd | 936 ++++++++++-------- 17 files changed, 922 insertions(+), 737 deletions(-) create mode 100644 sim/L0_rtps_writer_test1_vbkdp.do diff --git a/sim/L0_rtps_writer_test1_vbkdp.do b/sim/L0_rtps_writer_test1_vbkdp.do new file mode 100644 index 0000000..3c0d1a5 --- /dev/null +++ b/sim/L0_rtps_writer_test1_vbkdp.do @@ -0,0 +1,65 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/clk +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/reset +add wave -noupdate -divider INPUT +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/empty_meta +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/rd_meta +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/last_word_in_meta +add wave -noupdate -radix hexadecimal /l0_rtps_writer_test1_vbkdp/uut/data_in_meta +add wave -noupdate -divider OUTPUT +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/start_hc +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/opcode_hc +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/ack_hc +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/done_hc +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/stage +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/stage_next +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/cnt +add wave -noupdate -divider {MEMORY FSM} +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_op_done +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_op_start +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_opcode +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_stage +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_cnt +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vbkdp/uut/mem_occupied_head +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vbkdp/uut/mem_empty_head +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vbkdp/uut/mem_prev_addr +add wave -noupdate /l0_rtps_writer_test1_vbkdp/uut/mem_prev_addr_valid +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vbkdp/uut/mem_addr_base +add wave -noupdate -expand -group MEM_CTRL -radix unsigned /l0_rtps_writer_test1_vbkdp/uut/mem_addr +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/mem_valid_in +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/mem_ready_in +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/mem_read +add wave -noupdate -expand -group MEM_CTRL -radix hexadecimal /l0_rtps_writer_test1_vbkdp/uut/mem_write_data +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/abort_read +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/mem_valid_out +add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vbkdp/uut/mem_ready_out +add wave -noupdate -expand -group MEM_CTRL -radix hexadecimal /l0_rtps_writer_test1_vbkdp/uut/mem_read_data +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/start +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/cnt_stim +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/packet_sent +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/mem_check_done +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/stim_done +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/test_done +add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vbkdp/uut/idle_sig +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {Begin {8325000 ps} 1} {Error {9725000 ps} 1} {Cursor {5753724 ps} 0} +quietly wave cursor active 3 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {1024 ns} diff --git a/sim/L0_rtps_writer_test1_vrkdp.do b/sim/L0_rtps_writer_test1_vrkdp.do index aede90b..11f4cdc 100644 --- a/sim/L0_rtps_writer_test1_vrkdp.do +++ b/sim/L0_rtps_writer_test1_vrkdp.do @@ -13,7 +13,6 @@ add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/start_hc add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/opcode_hc add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/ack_hc add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/done_hc -add wave -noupdate -radix hexadecimal /l0_rtps_writer_test1_vrkdp/uut/data_out_hc add wave -noupdate -divider {MAIN FSM} add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/stage add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/stage_next @@ -23,9 +22,11 @@ add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_op_done add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_op_start add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_opcode add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_stage -add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_stage_next add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_cnt -add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_pos +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vrkdp/uut/mem_occupied_head +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vrkdp/uut/mem_empty_head +add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vrkdp/uut/mem_prev_addr +add wave -noupdate /l0_rtps_writer_test1_vrkdp/uut/mem_prev_addr_valid add wave -noupdate -radix unsigned /l0_rtps_writer_test1_vrkdp/uut/mem_addr_base add wave -noupdate -expand -group MEM_CTRL -radix unsigned /l0_rtps_writer_test1_vrkdp/uut/mem_addr add wave -noupdate -expand -group MEM_CTRL /l0_rtps_writer_test1_vrkdp/uut/mem_valid_in @@ -45,7 +46,7 @@ add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vrkdp/stim_done add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vrkdp/test_done add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1_vrkdp/uut/idle_sig TreeUpdate [SetDefaultTree] -WaveRestoreCursors {Begin {8325000 ps} 1} {Error {9725000 ps} 1} {Cursor {9175000 ps} 0} +WaveRestoreCursors {Begin {8325000 ps} 1} {Error {9725000 ps} 1} {Cursor {5753724 ps} 0} quietly wave cursor active 3 configure wave -namecolwidth 150 configure wave -valuecolwidth 100 @@ -61,4 +62,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {8888200 ps} {9912200 ps} +WaveRestoreZoom {0 ps} {1024 ns} diff --git a/src/REF.txt b/src/REF.txt index 71a3182..4d6545a 100644 --- a/src/REF.txt +++ b/src/REF.txt @@ -406,7 +406,11 @@ WRITER + REQ_SEQ_NR_BASE + [Reliable Only] 13| | +---------------------------------------------------------------+ -14| REQ_BITMAP | [Reliable Only] +14| REQ_BITMAP | [Reliable Only] + +---------------------------------------------------------------+ +15| NEXT_ADDR | + +---------------------------------------------------------------+ +16| PREV_ADDR | +---------------------------------------------------------------+ READER_FLAGS diff --git a/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd index 260d407..a27bb69 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd @@ -125,6 +125,8 @@ begin variable p0, p1, participant : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA; variable e0, e1, e2, e3, endpoint : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA; + alias empty_head is <>; + -- Wrapper to use procedure as function impure function gen_rand_loc_2 return LOCATOR_TYPE is variable ret : LOCATOR_TYPE := EMPTY_LOCATOR; @@ -196,7 +198,7 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; - + -- MEMORY STATE -/0,8,16 Log("Insert Endpoint 0 Participant 0", INFO); endpoint := e0; @@ -208,7 +210,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,0,0] + AlertIf(empty_head /= 8, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(P0E0)/8,16 Log("Insert Endpoint 1 Participant 0", INFO); endpoint := e1; @@ -220,7 +223,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,0] + AlertIf(empty_head /= 16, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 8(P0E1),0(P0E0)/16 Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -232,7 +236,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e2] + AlertIf(empty_head /= 23, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 16(P1E2),8(P0E1),0(P0E0)/- Log("Ignore Endpoint 3 Participant 1 [Memory Full]", INFO); endpoint := e3; @@ -255,19 +260,20 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e3] + AlertIf(empty_head /= 23, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 16(P1E2),8(P0E1),0(P0E0)/- Log("Remove Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 2; endpoint.match := UNMATCH; gen_endpoint_match_frame(endpoint, stimulus); - SB_mem.Push(gen_reader_endpoint_mem_frame_b(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,0] + AlertIf(empty_head /= 16, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 8(P0E1),0(P0E0)/16 Log("Insert Endpoint 3 Participant 1", INFO); endpoint := e3; @@ -279,7 +285,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e3] + AlertIf(empty_head /= 23, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 16(P1E3),8(P0E1),0(P0E0)/- Log("Remove Participant 0", INFO); participant := p0; @@ -289,17 +296,16 @@ begin endpoint := e0; endpoint.nr := 0; endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_b(endpoint)); -- Remove Endpoint 1 endpoint := e1; endpoint.nr := 1; endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_b(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [0,0,p1e3] + AlertIf(empty_head /= 0, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 16(P1E3)/0,8 Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -311,7 +317,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,0,p1e3] + AlertIf(empty_head /= 8, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(P1E2),16(P1E3)/8 Log("Unknown Metatraffic Operation followed by insertion of Enpoint 0 Participant 0", INFO); for i in 0 to 9 loop @@ -340,7 +347,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,p0e0,p1e3] + AlertIf(empty_head /= 23, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 8(P0E0),0(P1E2),16(P1E3)/- Log("Update Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -353,8 +361,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,p0e0,p1e3] - + AlertIf(empty_head /= 23, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 8(P0E0),0(P1E2),16(P1E3)/- stim_done <= '1'; diff --git a/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd index 1ffcd01..a2ed161 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd @@ -125,6 +125,8 @@ begin variable p0, p1, participant : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA; variable e0, e1, e2, e3, endpoint : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA; + alias empty_head is <>; + -- Wrapper to use procedure as function impure function gen_rand_loc_2 return LOCATOR_TYPE is variable ret : LOCATOR_TYPE := EMPTY_LOCATOR; @@ -196,6 +198,7 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; + -- MEMORY STATE -/0,17,34 Log("Insert Endpoint 0 Participant 0", INFO); @@ -208,7 +211,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,0,0] + AlertIf(empty_head /= 17, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(P0E0)/17,34 Log("Insert Endpoint 1 Participant 0", INFO); endpoint := e1; @@ -220,7 +224,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,0] + AlertIf(empty_head /= 34, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 17(P0E1),0(P0E0)/34 Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -232,7 +237,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e2] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 34(P1E2),17(P0E1),0(P0E0)/- Log("Ignore Endpoint 3 Participant 1 [Memory Full]", INFO); endpoint := e3; @@ -255,19 +261,20 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e3] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 34(P1E2),17(P0E1),0(P0E0)/- Log("Remove Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 2; endpoint.match := UNMATCH; gen_endpoint_match_frame(endpoint, stimulus); - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,0] + AlertIf(empty_head /= 34, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 17(P0E1),0(P0E0)/34 Log("Insert Endpoint 3 Participant 1", INFO); endpoint := e3; @@ -279,7 +286,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p0e0,p0e1,p1e3] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 34(P1E3),17(P0E1),0(P0E0)/- Log("Remove Participant 0", INFO); participant := p0; @@ -289,17 +297,16 @@ begin endpoint := e0; endpoint.nr := 0; endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); -- Remove Endpoint 1 endpoint := e1; endpoint.nr := 1; endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [0,0,p1e3] + AlertIf(empty_head /= 0, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 34(P1E3)/0,17 Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -311,7 +318,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,0,p1e3] + AlertIf(empty_head /= 17, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(P1E2),34(P1E3)/17 Log("Unknown Metatraffic Operation followed by insertion of Enpoint 0 Participant 0", INFO); for i in 0 to 9 loop @@ -340,7 +348,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,p0e0,p1e3] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 17(E0P0),0(P1E2),34(P1E3)/- Log("Update Endpoint 2 Participant 1", INFO); endpoint := e2; @@ -353,9 +362,8 @@ begin wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; - -- MEMORY STATE [p1e2,p0e0,p1e3] - - + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 17(E0P0),0(P1E2),34(P1E3)/- stim_done <= '1'; wait_on_completion; diff --git a/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd index b891150..a62e617 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd @@ -110,6 +110,7 @@ begin variable sub : RTPS_SUBMESSAGE_TYPE := DEFAULT_RTPS_SUBMESSAGE; alias idle_sig is <>; + alias empty_head is <>; -- Wrapper to use procedure as function impure function gen_rand_loc_2 return LOCATOR_TYPE is @@ -231,6 +232,11 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; + wait until rising_edge(clk); + start_mem_check; + wait_on_mem_check; + AlertIf(empty_head /= 0, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE -/0,17,34 Log("Insert Endpoint 0", INFO); @@ -245,7 +251,8 @@ begin stimulus_user := EMPTY_TEST_PACKET; start_mem_check; wait_on_mem_check; - -- MEMORY STATE [e0,0,0] + AlertIf(empty_head /= 17, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(E0)/17,34 Log("Insert Endpoint 1", INFO); endpoint := e1; @@ -259,7 +266,8 @@ begin stimulus_user := EMPTY_TEST_PACKET; start_mem_check; wait_on_mem_check; - -- MEMORY STATE [e0,e1,0] + AlertIf(empty_head /= 34, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 17(E1),0(E0)/34 Log("Insert Endpoint 2", INFO); endpoint := e2; @@ -273,7 +281,8 @@ begin stimulus_user := EMPTY_TEST_PACKET; start_mem_check; wait_on_mem_check; - -- MEMORY STATE [e0,e1,e2] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 34(E2),17(E1),0(E0)/- Log("Current Time: 0.5s", INFO); test_time <= gen_duration(0,500); @@ -296,33 +305,15 @@ begin stimulus_user := EMPTY_TEST_PACKET; wait_on_idle; - Log("Current Time: 1s", INFO); + Log("Current Time: 1s [Removal of Enpoint 0]", INFO); test_time <= gen_duration(1,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low + start_mem_check; + wait_on_mem_check; + AlertIf(empty_head /= 0, "Memory Empty List Head incorrect", FAILURE); wait_on_idle; - - Log("Check Removal of Endpoint 0", INFO); - -- Re-check Mem-State - endpoint := e0; - endpoint.nr := 0; - endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - endpoint := e1; - endpoint.nr := 1; - endpoint.match := MATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - endpoint := e2; - endpoint.nr := 2; - endpoint.match := MATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - -- MEMORY STATE [0,e1,e2] + -- MEMORY STATE 34(E2),17(E1)/0 Log("Insert Endpoint 3", INFO); endpoint := e3; @@ -336,35 +327,18 @@ begin stimulus_user := EMPTY_TEST_PACKET; start_mem_check; wait_on_mem_check; - -- MEMORY STATE [e3,e1,e2] + AlertIf(empty_head /= 50, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(E3),34(E2),17(E1)/- - Log("Current Time: 1.5s", INFO); + Log("Current Time: 1.5s [Removal of Enpoint 2]", INFO); test_time <= gen_duration(1,500); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low + start_mem_check; + wait_on_mem_check; + AlertIf(empty_head /= 34, "Memory Empty List Head incorrect", FAILURE); wait_on_idle; - - Log("Check Removal of Endpoint 2", INFO); - -- Re-check Mem-State - endpoint := e3; - endpoint.nr := 0; - endpoint.match := MATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - endpoint := e1; - endpoint.nr := 1; - endpoint.match := MATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - endpoint := e2; - endpoint.nr := 2; - endpoint.match := UNMATCH; - SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); - start_mem_check; - wait_on_mem_check; - -- MEMORY STATE [e3,e1,0] + -- MEMORY STATE 0(E3),17(E1)/34 Log("Current Time: 2s", INFO); test_time <= gen_duration(2,0); @@ -386,7 +360,8 @@ begin SB_mem.Push(gen_reader_endpoint_mem_frame_a(endpoint)); start_mem_check; wait_on_mem_check; - -- MEMORY STATE [e3,e1,0] + AlertIf(empty_head /= 34, "Memory Empty List Head incorrect", FAILURE); + -- MEMORY STATE 0(E3),17(E1)/34 stim_done <= '1'; wait_on_completion; diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd index 2e2b3ab..5509da3 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd @@ -598,14 +598,14 @@ begin wait until rising_edge(clk); push_hc(ACK_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd index ce62980..4b3f084 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd @@ -432,14 +432,14 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(0)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(0)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(0)); @@ -481,22 +481,22 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(1)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(1)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(2)); + gen_data(e1, test_cc(1)); push_reference; wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(2)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -616,36 +616,36 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); + gen_header(e2); + gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(4)); + gen_header(e3); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; wait_on_idle; @@ -755,52 +755,52 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e0); - gen_data(e0, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; gen_header(e2); gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); + gen_header(e0); + gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; gen_header(e3); - gen_data(e3, test_cc(5)); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e2); + gen_data(e2, test_cc(5)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(5)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(5)); + gen_header(e3); + gen_data(e3, test_cc(5)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(5)); push_reference; wait_on_out_check; wait_on_idle; @@ -934,14 +934,14 @@ begin wait until rising_edge(clk); push_hc(ACK_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd index 01f06f6..fbf8303 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd @@ -572,14 +572,14 @@ begin wait until rising_edge(clk); push_hc(REMOVE_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd index 2d73457..8da433f 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd @@ -432,14 +432,14 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(0)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(0)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(0)); @@ -481,22 +481,22 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(1)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(1)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(2)); + gen_data(e1, test_cc(1)); push_reference; wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(2)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -599,36 +599,36 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); + gen_header(e2); + gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(4)); + gen_header(e3); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; wait_on_idle; @@ -736,52 +736,52 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e0); - gen_data(e0, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; gen_header(e2); gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); + gen_header(e0); + gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; gen_header(e3); - gen_data(e3, test_cc(5)); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e2); + gen_data(e2, test_cc(5)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(5)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(5)); + gen_header(e3); + gen_data(e3, test_cc(5)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(5)); push_reference; wait_on_out_check; wait_on_idle; @@ -888,14 +888,14 @@ begin wait until rising_edge(clk); push_hc(REMOVE_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd index 52992af..c20c954 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd @@ -433,14 +433,14 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(0)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(0)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(0)); @@ -482,22 +482,22 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(1)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(1)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(2)); + gen_data(e1, test_cc(1)); push_reference; wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(2)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -600,36 +600,36 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); + gen_header(e2); + gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(4)); + gen_header(e3); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; wait_on_idle; @@ -737,52 +737,52 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e0); - gen_data(e0, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; gen_header(e2); gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); + gen_header(e0); + gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; gen_header(e3); - gen_data(e3, test_cc(5)); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e2); + gen_data(e2, test_cc(5)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(5)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(5)); + gen_header(e3); + gen_data(e3, test_cc(5)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(5)); push_reference; wait_on_out_check; wait_on_idle; @@ -889,14 +889,14 @@ begin wait until rising_edge(clk); push_hc(REMOVE_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd index a49f8b0..0ccb861 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd @@ -434,14 +434,14 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(0)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(0)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(0)); @@ -481,22 +481,22 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(1)); - push_reference; - wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(1)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(2)); + gen_data(e1, test_cc(1)); push_reference; wait_on_out_check; gen_header(e3); gen_data(e3, test_cc(2)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -597,36 +597,36 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); + gen_header(e2); + gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(4)); + gen_header(e3); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; wait_on_idle; @@ -731,52 +731,52 @@ begin new_cc <= '0'; wait until rising_edge(clk); - gen_header(e1); - gen_data(e1, test_cc(3)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(3)); + gen_header(e2); + gen_data(e2, test_cc(3)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(3)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(3)); + gen_header(e3); + gen_data(e3, test_cc(3)); push_reference; wait_on_out_check; gen_header(e1); - gen_data(e1, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e3); - gen_data(e3, test_cc(4)); - push_reference; - wait_on_out_check; - gen_header(e0); - gen_data(e0, test_cc(4)); + gen_data(e1, test_cc(3)); push_reference; wait_on_out_check; gen_header(e2); gen_data(e2, test_cc(4)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); + gen_header(e0); + gen_data(e0, test_cc(4)); push_reference; wait_on_out_check; gen_header(e3); - gen_data(e3, test_cc(5)); + gen_data(e3, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(4)); + push_reference; + wait_on_out_check; + gen_header(e2); + gen_data(e2, test_cc(5)); push_reference; wait_on_out_check; gen_header(e0); gen_data(e0, test_cc(5)); push_reference; wait_on_out_check; - gen_header(e2); - gen_data(e2, test_cc(5)); + gen_header(e3); + gen_data(e3, test_cc(5)); + push_reference; + wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(5)); push_reference; wait_on_out_check; wait_on_idle; @@ -882,14 +882,14 @@ begin wait until rising_edge(clk); push_hc(REMOVE_CACHE_CHANGE, gen_sn(16)); - gen_header(e1); - gen_data(e1, test_cc(6)); - push_reference; - wait_on_out_check; gen_header(e4); gen_data(e4, test_cc(6)); push_reference; wait_on_out_check; + gen_header(e1); + gen_data(e1, test_cc(6)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(SEQUENCENUMBER_UNKNOWN); diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd index 83e33d7..5f2d626 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd @@ -471,14 +471,14 @@ begin test_time <= gen_duration(1,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - gen_header(e0); - gen_gap(gen_sn(1), gen_sn(2)); - push_reference; - wait_on_out_check; gen_header(e1); gen_data(e1, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e0); + gen_gap(gen_sn(1), gen_sn(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -647,14 +647,14 @@ begin test_time <= gen_duration(3,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - gen_header(e0); - gen_data(e0, test_cc(3)); - push_reference; - wait_on_out_check; gen_header(e1); gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; + gen_header(e0); + gen_data(e0, test_cc(3)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(3)); @@ -795,6 +795,10 @@ begin test_time <= gen_duration(5,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low + gen_header(e1); + gen_data(e1, test_cc(5)); + push_reference; + wait_on_out_check; gen_header(e0); gen_gap(gen_sn(14), gen_sn(15)); gen_data(e0, test_cc(4)); @@ -804,10 +808,6 @@ begin gen_gap(gen_sn(16), gen_sn(17)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); - push_reference; - wait_on_out_check; wait_on_idle; check_gsn(gen_sn(10)); diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd index 471f1d4..ec00690 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd @@ -472,14 +472,14 @@ begin test_time <= gen_duration(1,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - gen_header(e0); - gen_gap(gen_sn(1), gen_sn(2)); - push_reference; - wait_on_out_check; gen_header(e1); gen_data(e1, test_cc(0)); push_reference; wait_on_out_check; + gen_header(e0); + gen_gap(gen_sn(1), gen_sn(2)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(1)); @@ -648,14 +648,14 @@ begin test_time <= gen_duration(3,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - gen_header(e0); - gen_data(e0, test_cc(3)); - push_reference; - wait_on_out_check; gen_header(e1); gen_data(e1, test_cc(4)); push_reference; wait_on_out_check; + gen_header(e0); + gen_data(e0, test_cc(3)); + push_reference; + wait_on_out_check; wait_on_idle; check_gsn(gen_sn(3)); @@ -796,6 +796,10 @@ begin test_time <= gen_duration(5,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low + gen_header(e1); + gen_data(e1, test_cc(5)); + push_reference; + wait_on_out_check; gen_header(e0); gen_gap(gen_sn(14), gen_sn(15)); gen_data(e0, test_cc(4)); @@ -805,10 +809,6 @@ begin gen_gap(gen_sn(16), gen_sn(17)); push_reference; wait_on_out_check; - gen_header(e1); - gen_data(e1, test_cc(5)); - push_reference; - wait_on_out_check; wait_on_idle; check_gsn(gen_sn(10)); diff --git a/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd index 3960e32..94b44aa 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd @@ -355,8 +355,8 @@ begin test_time <= gen_duration(1,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - push_hb(e0, gen_sn(1), gen_sn(0), FALSE); push_hb(e1, gen_sn(1), gen_sn(0), FALSE); + push_hb(e0, gen_sn(1), gen_sn(0), FALSE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -380,8 +380,8 @@ begin test_time <= gen_duration(2,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - push_hb(e0, gen_sn(1), gen_sn(1), FALSE); push_hb(e1, gen_sn(1), gen_sn(1), FALSE); + push_hb(e0, gen_sn(1), gen_sn(1), FALSE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -409,8 +409,8 @@ begin wait_on_idle; Log("Send HEARTBEAT to Endpoint 0,1 [Liveliness Flag]", INFO); - push_hb(e0, gen_sn(1), gen_sn(3), TRUE); push_hb(e1, gen_sn(1), gen_sn(3), TRUE); + push_hb(e0, gen_sn(1), gen_sn(3), TRUE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -428,10 +428,10 @@ begin test_time <= gen_duration(3,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - push_hb(e0, gen_sn(1), gen_sn(3), FALSE); - push_hb(e1, gen_sn(1), gen_sn(3), FALSE); - push_hb(e2, gen_sn(1), gen_sn(3), FALSE); push_hb(e3, gen_sn(1), gen_sn(3), FALSE); + push_hb(e2, gen_sn(1), gen_sn(3), FALSE); + push_hb(e1, gen_sn(1), gen_sn(3), FALSE); + push_hb(e0, gen_sn(1), gen_sn(3), FALSE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -486,11 +486,11 @@ begin test_time <= gen_duration(4,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - push_hb(e0, gen_sn(10), gen_sn(50), FALSE); - push_hb(e1, gen_sn(10), gen_sn(50), FALSE); - push_hb(e2, gen_sn(10), gen_sn(50), FALSE); - push_hb(e3, gen_sn(10), gen_sn(50), FALSE); push_hb(e4, gen_sn(10), gen_sn(50), FALSE); + push_hb(e3, gen_sn(10), gen_sn(50), FALSE); + push_hb(e2, gen_sn(10), gen_sn(50), FALSE); + push_hb(e1, gen_sn(10), gen_sn(50), FALSE); + push_hb(e0, gen_sn(10), gen_sn(50), FALSE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -506,11 +506,11 @@ begin test_time <= gen_duration(5,0); wait until rising_edge(clk); wait until rising_edge(clk); -- Allow idle_sig to go low - push_hb(e0, gen_sn(51), gen_sn(50), FALSE); - push_hb(e1, gen_sn(51), gen_sn(50), FALSE); - push_hb(e2, gen_sn(51), gen_sn(50), FALSE); - push_hb(e3, gen_sn(51), gen_sn(50), FALSE); push_hb(e4, gen_sn(51), gen_sn(50), FALSE); + push_hb(e3, gen_sn(51), gen_sn(50), FALSE); + push_hb(e2, gen_sn(51), gen_sn(50), FALSE); + push_hb(e1, gen_sn(51), gen_sn(50), FALSE); + push_hb(e0, gen_sn(51), gen_sn(50), FALSE); count <= count + 1; wait_on_out_check; wait_on_idle; @@ -523,11 +523,11 @@ begin wait_on_idle; Log("Send HEARTBEAT to Endpoint 0,1,2,3,4", INFO); - push_hb(e0, gen_sn(51), gen_sn(50), TRUE); - push_hb(e1, gen_sn(51), gen_sn(50), TRUE); - push_hb(e2, gen_sn(51), gen_sn(50), TRUE); - push_hb(e3, gen_sn(51), gen_sn(50), TRUE); push_hb(e4, gen_sn(51), gen_sn(50), TRUE); + push_hb(e3, gen_sn(51), gen_sn(50), TRUE); + push_hb(e2, gen_sn(51), gen_sn(50), TRUE); + push_hb(e1, gen_sn(51), gen_sn(50), TRUE); + push_hb(e0, gen_sn(51), gen_sn(50), TRUE); count <= count + 1; wait_on_out_check; wait_on_idle; diff --git a/src/rtps_test_package.vhd b/src/rtps_test_package.vhd index 6c31f78..ac3a5dd 100644 --- a/src/rtps_test_package.vhd +++ b/src/rtps_test_package.vhd @@ -28,9 +28,9 @@ package rtps_test_package is -- rtps_reader Endpoint Frame Size (RELIABLE=FALSE) constant WRITER_ENDPOINT_FRAME_SIZE_B : natural := 10; -- rtps_writer Endpoint Frame Size (RELIABLE=TRUE) - constant READER_ENDPOINT_FRAME_SIZE_A : natural := 15; + constant READER_ENDPOINT_FRAME_SIZE_A : natural := 17; -- rtps_writer Endpoint Frame Size (RELIABLE=FALSE) - constant READER_ENDPOINT_FRAME_SIZE_B : natural := 6; + constant READER_ENDPOINT_FRAME_SIZE_B : natural := 8; constant DEFAULT_GUIDPREFIX : GUIDPREFIX_TYPE; -- Deferred to Package Body constant DEFAULT_READER_ENTITYID : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Deferred to Package Body diff --git a/src/rtps_writer.vhd b/src/rtps_writer.vhd index 3fd8f25..ac80d45 100644 --- a/src/rtps_writer.vhd +++ b/src/rtps_writer.vhd @@ -83,9 +83,9 @@ architecture arch of rtps_writer is variable ret : natural := 0; begin if (qos = RELIABLE_RELIABILITY_QOS) then - ret := 15; + ret := 17; else - ret := 6; + ret := 8; end if; return ret; end function; @@ -126,6 +126,18 @@ architecture arch of rtps_writer is constant EMF_ACK_SEQ_NR_BASE_OFFSET : natural := 10; constant EMF_REQ_SEQ_NR_BASE_OFFSET : natural := 12; constant EMF_REQ_SEQ_NR_BITMAP_OFFSET : natural := 14; + function gen_emf_next_addr_offset(qos : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0)) return natural is + variable ret : natural := 0; + begin + if (qos = RELIABLE_RELIABILITY_QOS) then + ret := EMF_REQ_SEQ_NR_BITMAP_OFFSET + 1; + else + ret := EMF_LEASE_DEADLINE_OFFSET; + end if; + return ret; + end function; + constant EMF_NEXT_ADDR_OFFSET : natural := gen_emf_next_addr_offset(RELIABILITY_QOS); + constant EMF_PREV_ADDR_OFFSET : natural := EMF_NEXT_ADDR_OFFSET + 1; --*****TYPE DECLARATION***** @@ -135,24 +147,22 @@ architecture arch of rtps_writer is GET_MIN_SN, GET_MAX_SN, HANDLE_REQUESTS, HANDLE_HEARTBEATS, HANDLE_NEW, HANDLE_HISTORICAL, SEND_HEADER, SEND_INFO_TS, SEND_DATA_A, SEND_INLINE_QOS, SEND_DATA_B, SEND_GAP_A, SEND_GAP_B, SEND_HEARTBEAT, SKIP_PACKET, SKIP_META_OPERATION); -- Memory FSM states. Explained below in detail - type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, FIND_EMPTY_SLOT, - RESET_MAX_POINTER, GET_NEXT_ENDPOINT, RESET_MEMORY); + type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, + GET_NEXT_ENDPOINT, RESET_MEMORY); -- *Memory FSM Opcodes* -- OPCODE DESCRIPTION -- SEARCH_ENDPOINT Search memory for Endpoint with GUID equal to "guid" signal. -- Set "mem_addr_base" to base Address of found Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if nothing found. -- "mem_endpoint_data" contains Endpoint Data according to "mem_field_flags". - -- INSERT_ENDPOINT Insert Endpoint to first available empty slot in memory - -- UPDATE_ENDPOINT Update Endpoint pointed by "mem_addr_base" according to "mem_field_flags". - -- REMOVE_ENDPOINT Remove Endpoint pointed by "mem_addr_base" - -- GET_FIRST_ENDPOINT Get Endpoint Data of first Endpoint stored in Memory according to "mem_field_flags". - -- Set "mem_addr_base" to Address of Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if no Endpoint in Memory. - -- GET_NEXT_ENDPOINT Get Endpoint Data of next Endpoint (from the Endpoint pointed by "mem_addr_base") according to "mem_field_flags". + -- INSERT_ENDPOINT Insert Endpoint in memory + -- UPDATE_ENDPOINT Update Endpoint pointed by "mem_addr_update" according to "mem_field_flags". + -- REMOVE_ENDPOINT Remove Endpoint pointed by "mem_addr_update". + -- "mem_addr_base" is set to the next Endpoint (or ENDPOINT_MEMORY_MAX_ADDRESS if no next Endpoint exists) + -- GET_NEXT_ENDPOINT Get Endpoint Data of next Endpoint (from the Endpoint pointed by "mem_addr_update") according to "mem_field_flags". -- Set "mem_addr_base" to Address of Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if no other Endpoint in Memory. -- GET_ENDPOINT Get Endpoint Data from Endpoint pointed by "mem_addr_update" according to "mem_field_flags". -- Already fetched data of the same Endpoint is not modified. - type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_FIRST_ENDPOINT, GET_NEXT_ENDPOINT, - GET_ENDPOINT); + type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, GET_ENDPOINT); -- Record of Endpoint Data type ENDPOINT_DATA_TYPE is record guid : GUID_TYPE; @@ -291,30 +301,30 @@ architecture arch of rtps_writer is signal req_seq_nr_bitmap, req_seq_nr_bitmap_next : std_logic_vector(0 to WORD_WIDTH-1); -- Signal used to iterate through Request Bitmaps signal req_bitmap_pos, req_bitmap_pos_next : natural range 0 to req_seq_nr_bitmap'length; - -- Test signal used for testbench synchronisation - signal idle_sig : std_logic; -- Signal used to pass Endpoint Pointers to the Endpoint Memory Process signal mem_addr_update : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); + -- Test signal used for testbench synchronisation + signal idle_sig : std_logic; + -- Test signal used in testbenches for removal check + signal empty_head_sig : natural; -- *MEMORY PROCESS* -- Memory FSM state signal mem_stage, mem_stage_next : MEM_STAGE_TYPE; + -- Head of Occupied Memory Endpoint List + signal mem_occupied_head, mem_occupied_head_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); + -- Head of Empty Memory Endpoint List + signal mem_empty_head, mem_empty_head_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to current relevant Endpoint Address signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); - -- Help signal used to reset the MAX Endpoint Memory Pointer - signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Memory Address Latch signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); - -- Highest Endpoint Memory Address (Points to first Address of last occupied Endpoint Frame) - signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Couter signal mem_cnt, mem_cnt_next : natural range 0 to 29; -- Latch for Endpoint Data from Memory signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE; -- Latch for Endpoint Data from main process signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE; - -- Position (In Endpoint Memory Frame Granularity) of current relevant Endpoint - signal mem_pos, mem_pos_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1; -- Endpoint Memory Flag Array denoting which mem_endpoint_data Fields are up-to-date with the respective fields of the Endpoint (Pointed by mem_addr_base) signal current_emf, current_emf_next : std_logic_vector(0 to EMF_FLAG_WIDTH-1); @@ -368,6 +378,17 @@ architecture arch of rtps_writer is return ret; end function; + -- HACK: Due to delta cycle race condition some assertions trigger false positives, + -- so we check the signals on the falling edge + function stable(clk : std_logic; a : boolean) return boolean is + begin + if (clk = '0') then + return a; + else + return TRUE; + end if; + end function; + begin --*****COMPONENT INSTANTIATION***** @@ -556,9 +577,10 @@ begin if (mem_op_done = '1') then stale_check_next <= '1'; stage_next <= ENDPOINT_STALE_CHECK; - cnt_next <= 1; + cnt_next <= 2; -- CHECK Endpoint mem_op_start <= '1'; - mem_opcode <= GET_FIRST_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_occupied_head; mem_field_flags <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG; -- Reset Timeout check_time_next <= TIME_INFINITE; @@ -646,7 +668,7 @@ begin end if; if (is_meta = '1' and (meta_opcode = EMO_PARTICIPANT_UNMATCH or meta_opcode = EMO_LIVELINESS_UPDATE)) then - --assert (last_word_in_meta = '1') report "last_word_in_meta not set" severity FAILURE; + assert stable(clk, last_word_in_meta = '1') severity FAILURE; -- DONE Parsing stage_next <= INITIATE_ENDPOINT_SEARCH; else @@ -660,7 +682,7 @@ begin -- Input FIFO Guard if ((is_meta = '1' and empty_meta = '0') or (is_meta = '0' and empty_user = '0')) then if (is_meta = '1') then - --assert (meta_opcode /= EMO_ENDPOINT_UNMATCH or (meta_opcode = EMO_ENDPOINT_UNMATCH and last_word_in_meta = '1')) report "last_word_in_meta not set" severity FAILURE; + assert stable(clk, meta_opcode /= EMO_ENDPOINT_UNMATCH or (meta_opcode = EMO_ENDPOINT_UNMATCH and last_word_in_meta = '1')) severity FAILURE; rd_meta <= '1'; guid_next(3) <= data_in_meta; -- Memory Operation Guard @@ -690,7 +712,8 @@ begin stage_next <= METATRAFFIC_OPERATION; when EMO_PARTICIPANT_UNMATCH => mem_op_start <= '1'; - mem_opcode <= GET_FIRST_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_occupied_head; mem_field_flags <= EMF_GUIDPREFIX_FLAG; stage_next <= METATRAFFIC_OPERATION; cnt_next <= 0; @@ -725,7 +748,7 @@ begin cnt_next <= cnt + 1; -- UDP Port when 1 => - --assert (last_word_in_meta = '1') report "last_word_in_meta not set" severity FAILURE; + assert stable(clk, last_word_in_meta = '1') severity FAILURE; portn_next <= data_in_meta(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH); reader_flags_next <= data_in_meta(reader_flags'length-1 downto 0); @@ -746,10 +769,17 @@ begin -- NOTE: The Lease is NOT renewed in case of an update. That is the responsibility of the Liveliness Update mem_op_start <= '1'; mem_opcode <= UPDATE_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; -- DONE stage_next <= IDLE; + -- Endpoint Memory Full + elsif (mem_empty_head = ENDPOINT_MEMORY_MAX_ADDRESS) then + -- Ignore + stage_next <= IDLE; else + assert stable(clk, mem_empty_head /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Insert Matched Remote Endpoint mem_op_start <= '1'; mem_opcode <= INSERT_ENDPOINT; @@ -800,16 +830,18 @@ begin end if; end if; when EMO_ENDPOINT_UNMATCH => - assert check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG) severity FAILURE; -- Endpoint not in Memory if (mem_addr_base = ENDPOINT_MEMORY_MAX_ADDRESS) then -- Ignore stage_next <= IDLE; else + assert stable(clk, check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG)) severity FAILURE; + -- Remove Unmatched Remote Endpoint mem_op_start <= '1'; mem_opcode <= REMOVE_ENDPOINT; + mem_addr_update <= mem_addr_base; -- Global ACK SN possibly changed if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and global_ack_seq_nr_base /= SEQUENCENUMBER_UNKNOWN and global_ack_seq_nr_base = mem_endpoint_data.ack_seq_nr_base) then @@ -824,8 +856,6 @@ begin when EMO_PARTICIPANT_UNMATCH => case (cnt) is when 0 => - assert check_mask(current_emf, EMF_GUIDPREFIX_FLAG) severity FAILURE; - -- Reached End of Endpoints if (mem_addr_base = ENDPOINT_MEMORY_MAX_ADDRESS) then -- Global ACK SN possibly changed @@ -840,18 +870,35 @@ begin stage_next <= IDLE; end if; else + assert stable(clk, check_mask(current_emf, EMF_GUIDPREFIX_FLAG)) severity FAILURE; + -- Participant Match if (guid(0) = mem_endpoint_data.guid(0) and guid(1) = mem_endpoint_data.guid(1) and guid(2) = mem_endpoint_data.guid(2)) then -- Remove Unmatched Remote Endpoint mem_op_start <= '1'; mem_opcode <= REMOVE_ENDPOINT; + mem_addr_update <= mem_addr_base; + -- NOTE: After removal, mem_addr_base is pointing to the next slot (or ENDPOINT_MEMORY_MAX_ADDRESS) + cnt_next <= 2; -- GET + else + cnt_next <= 1; -- GET NEXT end if; - cnt_next <= 1; + end if; + -- GET NEXT ENDPOINT when 1 => -- Continue Search mem_op_start <= '1'; mem_opcode <= GET_NEXT_ENDPOINT; + mem_addr_update <= mem_addr_base; + mem_field_flags <= EMF_GUIDPREFIX_FLAG; + cnt_next <= 0; + -- GET ENDPOINT + when 2 => + -- Continue Search + mem_op_start <= '1'; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_GUIDPREFIX_FLAG; cnt_next <= 0; when others => @@ -966,14 +1013,14 @@ begin if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Wait for Endpoint Data if (mem_op_done = '1') then - assert check_mask(current_emf, EMF_RES_TIME_FLAG) severity FAILURE; - -- Known Remote Endpoint if (mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) then + assert stable(clk, check_mask(current_emf, EMF_RES_TIME_FLAG)) severity FAILURE; -- Liveliness Assertion mem_op_start <= '1'; mem_opcode <= UPDATE_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_LEASE_DEADLINE_FLAG; if (LEASE_DURATION /= DURATION_INFINITE) then lease_deadline <= time + LEASE_DURATION; @@ -1027,18 +1074,19 @@ begin -- Wait for Endpoint Search if (mem_op_done = '1') then - assert check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG) severity FAILURE; - -- DEFAULT stage_next <= SKIP_PACKET; -- Known Remote Endpoint if (mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) then + assert stable(clk, check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG)) severity FAILURE; + -- New Sequence Numbers are ACKed if (ack_base > mem_endpoint_data.ack_seq_nr_base) then -- Update ACK Sequence Number Base mem_op_start <= '1'; mem_opcode <= UPDATE_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_ACK_SEQ_NR_BASE_FLAG; seq_nr <= ack_base; -- NOTE: The global_ack_seq_nr_base contains the lowest SN of all remote Endpoints. @@ -1063,14 +1111,13 @@ begin -- Initiate Search when 0 => mem_op_start <= '1'; - mem_opcode <= GET_FIRST_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_occupied_head; mem_field_flags <= EMF_ACK_SEQ_NR_BASE_FLAG; cnt_next <= 1; new_global_ack_next <= SEQUENCENUMBER_UNKNOWN; -- Find new global_ack_seq_nr_base when 1 => - assert check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG) severity FAILURE; - -- End of Endpoints if (mem_addr_base = ENDPOINT_MEMORY_MAX_ADDRESS) then -- No Reliable Remote Endpoints @@ -1112,6 +1159,8 @@ begin end if; end if; else + assert stable(clk, check_mask(current_emf, EMF_ACK_SEQ_NR_BASE_FLAG)) severity FAILURE; + -- NOTE: Remote Endpoints with RELIABILITY BEST_EFFORT have a ack_seq_nr_base = SEQUENCENUMBER_UNKNOWN, since -- they cannot send ACKNACKs. -- XXX: Assumes SEQUENCENUMBER_UNKNOWN is higher than all valid Sequence Numbers. @@ -1122,6 +1171,7 @@ begin mem_op_start <= '1'; mem_opcode <= GET_NEXT_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_ACK_SEQ_NR_BASE_FLAG; end if; -- ACK Sequence Numbers @@ -1163,16 +1213,22 @@ begin -- Memory Operation Guard if (mem_op_done = '1') then case (cnt) is - -- Get Next Endpoint + -- GET Endpoint when 0 => mem_op_start <= '1'; - mem_opcode <= GET_NEXT_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG; - cnt_next <= 1; - -- Check Endpoint + cnt_next <= 2; -- CHECK Endpoint + -- GET NEXT Endpoint when 1 => - assert check_mask(current_emf, EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG) severity FAILURE; - + mem_op_start <= '1'; + mem_opcode <= GET_NEXT_ENDPOINT; + mem_addr_update <= mem_addr_base; + mem_field_flags <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG; + cnt_next <= 2; -- CHECK Endpoint + -- CHECK Endpoint + when 2 => -- End of Endpoints if (mem_addr_base = ENDPOINT_MEMORY_MAX_ADDRESS) then -- Reset @@ -1180,13 +1236,16 @@ begin -- DONE stage_next <= IDLE; else + assert stable(clk, check_mask(current_emf, EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG)) severity FAILURE; + -- Endpoint Lease Expired if (mem_endpoint_data.lease_deadline /= TIME_INVALID and mem_endpoint_data.lease_deadline <= time) then -- Remove Participant mem_op_start <= '1'; mem_opcode <= REMOVE_ENDPOINT; + mem_addr_update <= mem_addr_base; -- Continue Search - cnt_next <= 0; + cnt_next <= 0; -- GET Endpoint -- Synthesis Guard/Response Time Reached elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.res_time <= time) then -- If Suppression Delay passed, zero the time @@ -1194,21 +1253,22 @@ begin -- Disable Suppression mem_op_start <= '1'; mem_opcode <= UPDATE_ENDPOINT; + mem_addr_update <= mem_addr_base; res_time <= TIME_INVALID; mem_field_flags <= EMF_RES_TIME_FLAG; -- Continue Search - cnt_next <= 0; + cnt_next <= 1; -- GET NEXT Endpoint -- If Response Delay Passed else -- Get Additional Data mem_op_start <= '1'; mem_opcode <= GET_ENDPOINT; - mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG; mem_addr_update <= mem_addr_base; + mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG; -- Send Requests stage_next <= HANDLE_REQUESTS; - cnt_next <= 4; + cnt_next <= 4; -- Initialize end if; -- Update Check Time @@ -1232,14 +1292,16 @@ begin end if; -- Continue Search - cnt_next <= 0; + cnt_next <= 1; -- GET NEXT Endpoint end if; end if; - when 2 => + -- UPDATE Endpoint + when 3 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_op_start <= '1'; mem_opcode <= UPDATE_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG or EMF_RES_TIME_FLAG; -- Reset Requests @@ -1319,7 +1381,8 @@ begin if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Wait for Endpoint Data if (mem_op_done = '1') then - assert check_mask(current_emf, EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG) severity FAILURE; + assert stable(clk, check_mask(current_emf, EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG)) severity FAILURE; + assert stable(clk, mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE; case (cnt) is -- Next Bitmap Pos @@ -1338,12 +1401,12 @@ begin cnt_next <= 0; -- DONE return_stage_next <= ENDPOINT_STALE_CHECK; - return_cnt_next <= 2; + return_cnt_next <= 3; -- Upadte Endpoint gap_is_last_next <= '1'; else -- DONE stage_next <= ENDPOINT_STALE_CHECK; - cnt_next <= 2; + cnt_next <= 3; -- Update Endpoint end if; -- Next Requested SN found elsif (mem_endpoint_data.req_seq_nr_bitmap(req_bitmap_pos) = '1') then @@ -1438,7 +1501,8 @@ begin -- Get FIRST Destination when 0 => mem_op_start <= '1'; - mem_opcode <= GET_FIRST_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_occupied_head; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; cnt_next <= cnt + 2; @@ -1451,6 +1515,7 @@ begin when 1 => mem_op_start <= '1'; mem_opcode <= GET_NEXT_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; cnt_next <= cnt + 1; -- Initiate Heartbeat Sending @@ -1494,7 +1559,8 @@ begin -- Memory Operation Guard if (mem_op_done = '1') then mem_op_start <= '1'; - mem_opcode <= GET_FIRST_ENDPOINT; + mem_opcode <= GET_ENDPOINT; + mem_addr_update <= mem_occupied_head; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; cnt_next <= cnt + 1; end if; @@ -1568,6 +1634,7 @@ begin if (mem_op_done = '1') then mem_op_start <= '1'; mem_opcode <= GET_NEXT_ENDPOINT; + mem_addr_update <= mem_addr_base; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; -- Loop cnt_next <= 2; @@ -1805,7 +1872,8 @@ begin -- Wait for Endpoint Data if (mem_op_done = '1') then - assert check_mask(current_emf, EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG) severity FAILURE; + assert stable(clk, check_mask(current_emf, EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG)) severity FAILURE; + assert stable(clk, mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE; -- Output FIFO Guard if (full_ro = '0') then @@ -1879,7 +1947,8 @@ begin -- Wait for Endpoint Data if (mem_op_done = '1') then - assert check_mask(current_emf, EMF_UDP_PORT_FLAG) severity FAILURE; + assert stable(clk, check_mask(current_emf, EMF_UDP_PORT_FLAG)) severity FAILURE; + assert stable(clk, mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE; -- Output FIFO Guard if (full_ro = '0') then @@ -2271,11 +2340,11 @@ begin stage_next <= IDLE; end if; end if; - when others => - null; end case; end process; + empty_head_sig <= to_integer(mem_empty_head); + -- *Memory State Machine* -- STATE DESCRIPTION -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations @@ -2284,8 +2353,6 @@ begin -- INSERT_ENDPOINT See Memory OPCODE Description -- UPDATE_ENDPOINT See Memory OPCODE Description -- REMOVE_ENDPOINT See Memory OPCODE Description - -- FIND_EMPTY_SLOT Find first empty_user slot in memory. - -- RESET_MAX_POINTER Reset the max_endpoint_addr pointer to last occupied slot in memory. -- GET_NEXT_ENDPOINT See Memory OPCODE Description -- RESET_MEMORY Reset Endpoint Memory to Empty State mem_ctrl_prc : process(all) @@ -2293,13 +2360,12 @@ begin -- DEFAULT Registered mem_stage_next <= mem_stage; mem_addr_base_next <= mem_addr_base; + mem_occupied_head_next <= mem_occupied_head; + mem_empty_head_next <= mem_empty_head; mem_cnt_next <= mem_cnt; - last_addr_next <= last_addr; mem_addr_latch_next <= mem_addr_latch; mem_endpoint_data_next <= mem_endpoint_data; - max_endpoint_addr_next <= max_endpoint_addr; mem_endpoint_latch_data_next <= mem_endpoint_latch_data; - mem_pos_next <= mem_pos; current_emf_next <= current_emf; -- DEFAULT Unregistered mem_addr <= (others => '0'); @@ -2332,111 +2398,126 @@ begin case(mem_opcode) is when SEARCH_ENDPOINT => - current_emf_next <= mem_field_flags; mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - - mem_addr_base_next <= FIRST_ENDPOINT_ADDRESS; - mem_pos_next <= 0; - mem_stage_next <= SEARCH_ENDPOINT; - mem_cnt_next <= 0; - when INSERT_ENDPOINT => - current_emf_next <= (others => '1'); - -- Set Endpoint Data - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - mem_endpoint_data_next.guid <= guid_next; - mem_endpoint_data_next.addr <= addr_next; - mem_endpoint_data_next.portn <= portn_next; - mem_endpoint_data_next.flags <= reader_flags_next; - mem_endpoint_data_next.lease_deadline <= lease_deadline; - mem_endpoint_data_next.res_time <= TIME_INVALID; - mem_endpoint_data_next.ack_seq_nr_base <= seq_nr; - mem_endpoint_data_next.req_seq_nr_base <= SEQUENCENUMBER_UNKNOWN; - mem_endpoint_data_next.req_seq_nr_bitmap <= (others => '0'); - - mem_addr_base_next <= FIRST_ENDPOINT_ADDRESS; - mem_pos_next <= 0; - mem_stage_next <= FIND_EMPTY_SLOT; - mem_cnt_next <= 0; - when UPDATE_ENDPOINT => - current_emf_next <= current_emf or mem_field_flags; - mem_stage_next <= UPDATE_ENDPOINT; - - if check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG) then - mem_cnt_next <= 0; - elsif check_mask(mem_field_flags,EMF_UDP_PORT_FLAG) then - mem_cnt_next <= 1; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_LEASE_DEADLINE_FLAG)) then - mem_cnt_next <= 2; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_RES_TIME_FLAG)) then - mem_cnt_next <= 4; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_ACK_SEQ_NR_BASE_FLAG)) then - mem_cnt_next <= 6; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BASE_FLAG)) then - mem_cnt_next <= 8; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then - mem_cnt_next <= 10; + if (RELIABILITY_QOS /= RELIABLE_RELIABILITY_QOS) then + current_emf_next <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_ACK_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG; else - -- DONE - mem_stage_next <= IDLE; + current_emf_next <= (others => '0'); end if; - when REMOVE_ENDPOINT => - current_emf_next <= (others => '0'); - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - mem_stage_next <= REMOVE_ENDPOINT; - mem_cnt_next <= 0; - when GET_FIRST_ENDPOINT => - current_emf_next <= mem_field_flags; - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - - mem_addr_base_next <= FIRST_ENDPOINT_ADDRESS; - mem_pos_next <= 0; - mem_stage_next <= GET_NEXT_ENDPOINT; - mem_cnt_next <= 0; - when GET_NEXT_ENDPOINT => - current_emf_next <= mem_field_flags; - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - - -- Memory Bound Guard - if (mem_addr_base >= max_endpoint_addr) then + if (mem_occupied_head = ENDPOINT_MEMORY_MAX_ADDRESS) then mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; else - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; + mem_addr_base_next <= mem_occupied_head; + mem_stage_next <= SEARCH_ENDPOINT; + mem_cnt_next <= 0; + end if; + when INSERT_ENDPOINT => + assert (mem_empty_head /= ENDPOINT_MEMORY_MAX_ADDRESS) severity FAILURE; + + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + if (RELIABILITY_QOS /= RELIABLE_RELIABILITY_QOS) then + current_emf_next <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_ACK_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG; + else + current_emf_next <= (others => '0'); + end if; + + mem_addr_base_next <= mem_empty_head; + mem_stage_next <= INSERT_ENDPOINT; + mem_cnt_next <= 0; + when UPDATE_ENDPOINT => + if (mem_addr_update = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + current_emf_next <= (others => '0'); + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + else + current_emf_next <= current_emf or mem_field_flags; + + mem_addr_base_next <= mem_addr_update; + mem_stage_next <= UPDATE_ENDPOINT; + if check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG) then + mem_cnt_next <= 0; + elsif check_mask(mem_field_flags,EMF_UDP_PORT_FLAG) then + mem_cnt_next <= 1; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_LEASE_DEADLINE_FLAG)) then + mem_cnt_next <= 2; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_RES_TIME_FLAG)) then + mem_cnt_next <= 4; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_ACK_SEQ_NR_BASE_FLAG)) then + mem_cnt_next <= 6; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BASE_FLAG)) then + mem_cnt_next <= 8; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then + mem_cnt_next <= 10; + else + -- DONE + mem_stage_next <= IDLE; + end if; + end if; + when REMOVE_ENDPOINT => + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + current_emf_next <= (others => '0'); + + if (mem_addr_update = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + else + mem_addr_base_next <= mem_addr_update; + mem_stage_next <= REMOVE_ENDPOINT; + mem_cnt_next <= 0; + end if; + when GET_NEXT_ENDPOINT => + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + if (RELIABILITY_QOS /= RELIABLE_RELIABILITY_QOS) then + current_emf_next <= EMF_LEASE_DEADLINE_FLAG or EMF_RES_TIME_FLAG or EMF_ACK_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BASE_FLAG or EMF_REQ_SEQ_NR_BITMAP_FLAG; + else + current_emf_next <= (others => '0'); + end if; + + if (mem_addr_update = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + else + mem_addr_base_next <= mem_addr_update; mem_stage_next <= GET_NEXT_ENDPOINT; mem_cnt_next <= 0; end if; when GET_ENDPOINT => - if (mem_addr_base /= mem_addr_update) then + if (mem_addr_update = ENDPOINT_MEMORY_MAX_ADDRESS) then mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; - current_emf_next <= mem_field_flags; + current_emf_next <= (others => '0'); + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; else - current_emf_next <= current_emf or mem_field_flags; - end if; - - -- Fetch Endpoint Data - mem_stage_next <= GET_ENDPOINT_DATA; - if check_mask(mem_field_flags,EMF_ENTITYID_FLAG) then - mem_cnt_next <= 0; - elsif check_mask(mem_field_flags,EMF_GUIDPREFIX_FLAG) then - mem_cnt_next <= 1; - elsif check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG) then - mem_cnt_next <= 4; - elsif check_mask(mem_field_flags,EMF_UDP_PORT_FLAG) then - mem_cnt_next <= 5; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_LEASE_DEADLINE_FLAG)) then - mem_cnt_next <= 6; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_RES_TIME_FLAG)) then - mem_cnt_next <= 8; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_ACK_SEQ_NR_BASE_FLAG)) then - mem_cnt_next <= 10; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BASE_FLAG)) then - mem_cnt_next <= 12; - elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then - mem_cnt_next <= 14; - else - -- DONE - mem_stage_next <= IDLE; + if (mem_addr_base /= mem_addr_update) then + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + current_emf_next <= mem_field_flags; + else + current_emf_next <= current_emf or mem_field_flags; + end if; + + -- Fetch Endpoint Data + mem_addr_base_next <= mem_addr_update; + mem_stage_next <= GET_ENDPOINT_DATA; + if check_mask(mem_field_flags,EMF_ENTITYID_FLAG) then + mem_cnt_next <= 0; + elsif check_mask(mem_field_flags,EMF_GUIDPREFIX_FLAG) then + mem_cnt_next <= 1; + elsif check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG) then + mem_cnt_next <= 4; + elsif check_mask(mem_field_flags,EMF_UDP_PORT_FLAG) then + mem_cnt_next <= 5; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_LEASE_DEADLINE_FLAG)) then + mem_cnt_next <= 6; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_RES_TIME_FLAG)) then + mem_cnt_next <= 8; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_ACK_SEQ_NR_BASE_FLAG)) then + mem_cnt_next <= 10; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BASE_FLAG)) then + mem_cnt_next <= 12; + elsif (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then + mem_cnt_next <= 14; + else + -- DONE + mem_stage_next <= IDLE; + end if; end if; when others => null; @@ -2487,19 +2568,8 @@ begin if (mem_valid_out = '1') then -- No Match if (mem_read_data /= mem_endpoint_latch_data.guid(3)) then - abort_read <= '1'; - -- Reached End of Memory, No Match - if (mem_addr_base = max_endpoint_addr) then - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match - -- DONE - mem_stage_next <= IDLE; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - - end if; + abort_read <= '1'; + mem_cnt_next <= 8; -- GET Next Addr else mem_cnt_next <= mem_cnt + 1; end if; @@ -2512,17 +2582,7 @@ begin -- No Match if (mem_read_data /= mem_endpoint_latch_data.guid(0)) then abort_read <= '1'; - -- Reached End of Memory, No Match - if (mem_addr_base = max_endpoint_addr) then - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match - -- DONE - mem_stage_next <= IDLE; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; + mem_cnt_next <= 8; -- GET Next Addr else mem_cnt_next <= mem_cnt + 1; end if; @@ -2535,17 +2595,7 @@ begin -- No Match if (mem_read_data /= mem_endpoint_latch_data.guid(1)) then abort_read <= '1'; - -- Reached End of Memory, No Match - if (mem_addr_base = max_endpoint_addr) then - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match - -- DONE - mem_stage_next <= IDLE; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; + mem_cnt_next <= 8; -- GET Next Addr else mem_cnt_next <= mem_cnt + 1; end if; @@ -2558,23 +2608,12 @@ begin -- No Match if (mem_read_data /= mem_endpoint_latch_data.guid(2)) then abort_read <= '1'; - -- Reached End of Memory, No Match - if (mem_addr_base = max_endpoint_addr) then - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match - -- DONE - mem_stage_next <= IDLE; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; + mem_cnt_next <= 8; -- GET Next Addr -- Match else mem_addr_base_next <= mem_addr_base; -- Fetch Endpoint Data - mem_stage_next <= GET_ENDPOINT_DATA; - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + mem_stage_next <= GET_ENDPOINT_DATA; if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then mem_cnt_next <= 0; elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then @@ -2599,6 +2638,31 @@ begin end if; end if; end if; + -- GET Next Addr + when 8 => + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + mem_read <= '1'; + mem_valid_in <= '1'; + -- Memory Flow Control Guard + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- READ Next Addr + when 9 => + mem_ready_out <= '1'; + -- Memory Flow Control Guard + if (mem_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match + -- DONE + mem_stage_next <= IDLE; + else + -- Continue + mem_addr_base_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + mem_cnt_next <= 0; + end if; + end if; when others => null; end case; @@ -2949,6 +3013,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.guid(3) <= mem_read_data; + current_emf_next <= current_emf or EMF_ENTITYID_FLAG; if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then mem_cnt_next <= 16; @@ -2995,6 +3060,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.guid(2) <= mem_read_data; + current_emf_next <= current_emf or EMF_GUIDPREFIX_FLAG; if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then mem_cnt_next <= 19; @@ -3021,6 +3087,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.addr <= mem_read_data; + current_emf_next <= current_emf or EMF_IPV4_ADDR_FLAG; if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then mem_cnt_next <= 20; @@ -3046,6 +3113,7 @@ begin if (mem_valid_out = '1') then mem_endpoint_data_next.portn <= mem_read_data(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH); mem_endpoint_data_next.flags <= mem_read_data(CDR_SHORT_WIDTH-1 downto 0); + current_emf_next <= current_emf or EMF_UDP_PORT_FLAG; if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG)) then mem_cnt_next <= 21; @@ -3082,6 +3150,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.lease_deadline(1) <= unsigned(mem_read_data); + current_emf_next <= current_emf or EMF_LEASE_DEADLINE_FLAG; if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then mem_cnt_next <= 23; @@ -3117,6 +3186,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.res_time(1) <= unsigned(mem_read_data); + current_emf_next <= current_emf or EMF_RES_TIME_FLAG; if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_ACK_SEQ_NR_BASE_FLAG)) then mem_cnt_next <= 25; @@ -3150,6 +3220,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.ack_seq_nr_base(1) <= unsigned(mem_read_data); + current_emf_next <= current_emf or EMF_ACK_SEQ_NR_BASE_FLAG; if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_REQ_SEQ_NR_BASE_FLAG)) then mem_cnt_next <= 27; @@ -3181,6 +3252,7 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.req_seq_nr_base(1) <= unsigned(mem_read_data); + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BASE_FLAG; if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then mem_cnt_next <= 29; @@ -3198,7 +3270,8 @@ begin -- Memory Flow Control Guard if (mem_valid_out = '1') then mem_endpoint_data_next.req_seq_nr_bitmap <= mem_read_data; - + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BITMAP_FLAG; + -- DONE mem_stage_next <= IDLE; end if; @@ -3208,61 +3281,80 @@ begin end case; when INSERT_ENDPOINT => case (mem_cnt) is - -- Entity ID + -- GET Next Addr when 0 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + mem_read <= '1'; + -- Memory Flow Control Guard + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- SET Entity ID + when 1 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; mem_write_data <= mem_endpoint_latch_data.guid(3); + mem_endpoint_data_next.guid(3) <= mem_endpoint_latch_data.guid(3); + current_emf_next <= current_emf or EMF_ENTITYID_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; - -- GUID Prefix 1/3 - when 1 => + -- SET GUID Prefix 1/3 + when 2 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET; mem_write_data <= mem_endpoint_latch_data.guid(0); + mem_endpoint_data_next.guid(0) <= mem_endpoint_latch_data.guid(0); if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; - -- GUID Prefix 2/3 - when 2 => + -- SET GUID Prefix 2/3 + when 3 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 1; mem_write_data <= mem_endpoint_latch_data.guid(1); + mem_endpoint_data_next.guid(1) <= mem_endpoint_latch_data.guid(1); if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; - -- GUID Prefix 3/3 - when 3 => + -- SET GUID Prefix 3/3 + when 4 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2; mem_write_data <= mem_endpoint_latch_data.guid(2); + mem_endpoint_data_next.guid(2) <= mem_endpoint_latch_data.guid(2); + current_emf_next <= current_emf or EMF_GUIDPREFIX_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; - -- IPv4 Address - when 4 => + -- SET IPv4 Address + when 5 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET; mem_write_data <= mem_endpoint_latch_data.addr; + mem_endpoint_data_next.addr <= mem_endpoint_latch_data.addr; + current_emf_next <= current_emf or EMF_IPV4_ADDR_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; - -- UDPv4 Ports and Reader Flags - when 5 => + -- SET UDPv4 Ports and Reader Flags + when 6 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET; mem_write_data <= mem_endpoint_latch_data.portn & mem_endpoint_latch_data.flags; + mem_endpoint_data_next.portn <= mem_endpoint_latch_data.portn; + mem_endpoint_data_next.flags <= mem_endpoint_latch_data.flags; + current_emf_next <= current_emf or EMF_UDP_PORT_FLAG; if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_cnt_next <= mem_cnt + 1; else - -- DONE - mem_stage_next <= IDLE; + mem_cnt_next <= 16; -- SET Next Addr end if; end if; - -- Lease Deadline 1/2 - when 6 => + -- SET Lease Deadline 1/2 + when 7 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; @@ -3272,19 +3364,21 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Lease Deadline 2/2 - when 7 => + -- SET Lease Deadline 2/2 + when 8 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(1)); + mem_endpoint_data_next.lease_deadline <= mem_endpoint_latch_data.lease_deadline; + current_emf_next <= current_emf or EMF_LEASE_DEADLINE_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Response Time 1/2 - when 8 => + -- SET Response Time 1/2 + when 9 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; @@ -3294,18 +3388,20 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Response Time 2/2 - when 9 => + -- SET Response Time 2/2 + when 10 => if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1; mem_write_data <= std_logic_vector(TIME_INVALID(1)); + mem_endpoint_data_next.res_time <= TIME_INVALID; + current_emf_next <= current_emf or EMF_RES_TIME_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; end if; - -- ACK Sequence Number 1/2 - when 10 => + -- SET ACK Sequence Number 1/2 + when 11 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; @@ -3315,19 +3411,21 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- ACK Sequence Number 2/2 - when 11 => + -- SET ACK Sequence Number 2/2 + when 12 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_ACK_SEQ_NR_BASE_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.ack_seq_nr_base(1)); + mem_endpoint_data_next.ack_seq_nr_base <= mem_endpoint_latch_data.ack_seq_nr_base; + current_emf_next <= current_emf or EMF_ACK_SEQ_NR_BASE_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Request Sequence Number Base 1/2 - when 12 => + -- SET Request Sequence Number Base 1/2 + when 13 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; @@ -3337,41 +3435,89 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Request Sequence Number Base 2/2 - when 13 => + -- SET Request Sequence Number Base 2/2 + when 14 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_write_data <= (others => '0'); mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_REQ_SEQ_NR_BASE_OFFSET + 1; mem_write_data <= std_logic_vector(SEQUENCENUMBER_UNKNOWN(1)); + mem_endpoint_data_next.req_seq_nr_base <= SEQUENCENUMBER_UNKNOWN; + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BASE_FLAG; if (mem_ready_in = '1') then mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Request Bitmap - when 14 => + -- SET Request Bitmap + when 15 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_REQ_SEQ_NR_BITMAP_OFFSET; mem_write_data <= (others => '0'); + mem_endpoint_data_next.req_seq_nr_bitmap <= (others => '0'); + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BITMAP_FLAG; if (mem_ready_in = '1') then - -- DONE - mem_stage_next <= IDLE; + mem_cnt_next <= mem_cnt + 1; end if; end if; + -- SET Next Addr + when 16 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_occupied_head,WORD_WIDTH)); + + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- SET Prev Addr + when 17 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_PREV_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(ENDPOINT_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + + if (mem_ready_in = '1') then + if (mem_occupied_head = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_cnt_next <= mem_cnt + 2; -- Skip Next Step + else + mem_cnt_next <= mem_cnt + 1; + end if; + end if; + -- SET Prev Addr (Occupied Head) + when 18 => + mem_valid_in <= '1'; + mem_addr <= mem_occupied_head + EMF_PREV_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_addr_base,WORD_WIDTH)); + + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- READ Next Addr + when 19 => + mem_ready_out <= '1'; + -- Memory Flow Control Guard + if (mem_valid_out = '1') then + + -- Update List Heads + mem_empty_head_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + mem_occupied_head_next <= mem_addr_base; + + -- DONE + mem_stage_next <= IDLE; + end if; when others => null; - end case; + end case; when UPDATE_ENDPOINT => case (mem_cnt) is - -- IPv4 Address + -- SET IPv4 Address when 0 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET; mem_write_data <= mem_endpoint_latch_data.addr; - mem_endpoint_data_next.addr <= mem_endpoint_latch_data.addr; + mem_endpoint_data_next.addr <= mem_endpoint_latch_data.addr; + current_emf_next <= current_emf or EMF_IPV4_ADDR_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then @@ -3391,13 +3537,14 @@ begin mem_stage_next <= IDLE; end if; end if; - -- UDPv4 Ports & Reader Flags + -- SET UDPv4 Ports & Reader Flags when 1 => mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET; mem_write_data <= mem_endpoint_latch_data.portn & mem_endpoint_latch_data.flags; - mem_endpoint_data_next.portn <= mem_endpoint_latch_data.portn; - mem_endpoint_data_next.flags <= mem_endpoint_latch_data.flags; + mem_endpoint_data_next.portn <= mem_endpoint_latch_data.portn; + mem_endpoint_data_next.flags <= mem_endpoint_latch_data.flags; + current_emf_next <= current_emf or EMF_UDP_PORT_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG)) then @@ -3415,7 +3562,7 @@ begin mem_stage_next <= IDLE; end if; end if; - -- Lease Deadline 1/2 + -- SET Lease Deadline 1/2 when 2 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then @@ -3427,14 +3574,15 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Lease Deadline 2/2 + -- SET Lease Deadline 2/2 when 3 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.lease_deadline(1)); - mem_endpoint_data_next.lease_deadline <= mem_endpoint_latch_data.lease_deadline; + mem_endpoint_data_next.lease_deadline <= mem_endpoint_latch_data.lease_deadline; + current_emf_next <= current_emf or EMF_LEASE_DEADLINE_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then @@ -3451,7 +3599,7 @@ begin end if; end if; end if; - -- Response Time 1/2 + -- SET Response Time 1/2 when 4 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then @@ -3463,14 +3611,15 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Response Time 2/2 + -- SET Response Time 2/2 when 5 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.res_time(1)); - mem_endpoint_data_next.res_time <= mem_endpoint_latch_data.res_time; + mem_endpoint_data_next.res_time <= mem_endpoint_latch_data.res_time; + current_emf_next <= current_emf or EMF_RES_TIME_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_ACK_SEQ_NR_BASE_FLAG)) then @@ -3485,7 +3634,7 @@ begin end if; end if; end if; - -- ACK Sequence Number 1/2 + -- SET ACK Sequence Number 1/2 when 6 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then @@ -3497,14 +3646,15 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- ACK Sequence Number 2/2 + -- SET ACK Sequence Number 2/2 when 7 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_ACK_SEQ_NR_BASE_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.ack_seq_nr_base(1)); - mem_endpoint_data_next.ack_seq_nr_base <= mem_endpoint_latch_data.ack_seq_nr_base; + mem_endpoint_data_next.ack_seq_nr_base <= mem_endpoint_latch_data.ack_seq_nr_base; + current_emf_next <= current_emf or EMF_ACK_SEQ_NR_BASE_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_REQ_SEQ_NR_BASE_FLAG)) then @@ -3517,7 +3667,7 @@ begin end if; end if; end if; - -- Request Sequence Number Base 1/2 + -- SET Request Sequence Number Base 1/2 when 8 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then @@ -3529,14 +3679,15 @@ begin mem_cnt_next <= mem_cnt + 1; end if; end if; - -- Request Sequence Number Base 2/2 + -- SET Request Sequence Number Base 2/2 when 9 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_REQ_SEQ_NR_BASE_OFFSET + 1; mem_write_data <= std_logic_vector(mem_endpoint_latch_data.req_seq_nr_base(1)); - mem_endpoint_data_next.req_seq_nr_base <= mem_endpoint_latch_data.req_seq_nr_base; + mem_endpoint_data_next.req_seq_nr_base <= mem_endpoint_latch_data.req_seq_nr_base; + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BASE_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_REQ_SEQ_NR_BITMAP_FLAG)) then @@ -3547,14 +3698,15 @@ begin end if; end if; end if; - -- Request Bitmap + -- SET Request Bitmap when 10 => -- Synthesis Guard if (RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then mem_valid_in <= '1'; mem_addr <= mem_addr_base + EMF_REQ_SEQ_NR_BITMAP_OFFSET; mem_write_data <= mem_endpoint_latch_data.req_seq_nr_bitmap; - mem_endpoint_data_next.req_seq_nr_bitmap <= mem_endpoint_latch_data.req_seq_nr_bitmap; + mem_endpoint_data_next.req_seq_nr_bitmap <= mem_endpoint_latch_data.req_seq_nr_bitmap; + current_emf_next <= current_emf or EMF_REQ_SEQ_NR_BITMAP_FLAG; -- Memory Flow Control Guard if (mem_ready_in = '1') then -- DONE @@ -3565,152 +3717,127 @@ begin null; end case; when REMOVE_ENDPOINT => - -- Mark with ENTITYID_UNKNOWN to mark slot empty_user - mem_valid_in <= '1'; - mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; - mem_write_data <= ENTITYID_UNKNOWN; - - -- Memory Flow Control Guard - if (mem_ready_in = '1') then - -- Reset MAX Endpoint Pointer - mem_addr_base_next <= FIRST_ENDPOINT_ADDRESS; - mem_pos_next <= 0; - last_addr_next <= (others => '0'); - mem_stage_next <= RESET_MAX_POINTER; - mem_cnt_next <= 0; - -- Save Current Memory Position - mem_addr_latch_next <= mem_addr_base; - end if; - when FIND_EMPTY_SLOT => case (mem_cnt) is - -- GET Entity ID + -- GET Next Addr when 0 => - mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; - mem_read <= '1'; mem_valid_in <= '1'; - - -- Memory Control Flow Guard - if (mem_ready_in = '1') then - mem_cnt_next <= 1; - end if; - -- READ Entity ID - when 1 => - mem_ready_out <= '1'; - - -- Memory Control Flow Guard - if (mem_valid_out = '1') then - -- Slot Occupied - if (mem_read_data /= ENTITYID_UNKNOWN) then - -- Reached end of Endpoint Memory Area - if (mem_addr_base = max_endpoint_addr) then - -- MEMORY FULL - if (max_endpoint_addr = MAX_ENDPOINT_ADDRESS) then - report "Memory Full, Ignoring Endpoint Data" severity NOTE; - -- Ignore Insertion - mem_stage_next <= IDLE; - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; - else - -- Extend Endpoint Memory Area - -- NOTE: "max_endpoint_addr" points to the first address of last Endpoint Frame - max_endpoint_addr_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - -- Populate Endpoint Slot - mem_stage_next <= INSERT_ENDPOINT; - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; - -- Slot Empty - else - -- Populate Endpoint Slot - mem_stage_next <= INSERT_ENDPOINT; - mem_cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - when RESET_MAX_POINTER => - case (mem_cnt) is - -- GET Entity ID - when 0 => - mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; mem_read <= '1'; - mem_valid_in <= '1'; - - -- Memory Control Flow Guard + -- Memory Flow Control Guard if (mem_ready_in = '1') then - mem_cnt_next <= 1; + mem_cnt_next <= mem_cnt + 1; end if; - -- READ Entity ID + -- GET Prev Addr when 1 => - mem_ready_out <= '1'; + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_PREV_ADDR_OFFSET; + mem_read <= '1'; + -- Memory Flow Control Guard + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- SET Next Addr + when 2 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_empty_head,WORD_WIDTH)); - -- Memory Control Flow Guard + if (mem_ready_in = '1') then + -- Set New Empty Head + mem_empty_head_next <= mem_addr_base; + + mem_cnt_next <= mem_cnt + 1; + end if; + -- READ Next Addr + when 3 => + mem_ready_out <= '1'; + -- Memory Flow Control Guard if (mem_valid_out = '1') then - -- Slot Occupied - if (mem_read_data /= ENTITYID_UNKNOWN) then - -- Reached end of Endpoint Memory Area - if (mem_addr_base = max_endpoint_addr) then - -- No Change - mem_stage_next <= IDLE; - -- Restore Memory Position - mem_addr_base_next <= mem_addr_latch; - else - -- Latch last occupied Endpoint Slot - last_addr_next <= mem_addr_base; - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_cnt_next <= 0; - end if; - -- Slot Empty - else - -- Make sure to iterate through complete Endpoint Area - if (mem_addr_base = max_endpoint_addr) then - -- Reset Pointer to last occupied Endpoint Slot - max_endpoint_addr_next <= last_addr; + mem_addr_latch_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + mem_cnt_next <= mem_cnt + 1; + end if; + -- READ Prev Addr + when 4 => + mem_ready_out <= '1'; + -- Memory Flow Control Guard + if (mem_valid_out = '1') then + if (mem_addr_latch = ENDPOINT_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then + -- RESET Occupied List Head + mem_occupied_head_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; -- DONE - mem_stage_next <= IDLE; - -- Restore Memory Position - mem_addr_base_next <= mem_addr_latch; + mem_stage_next <= IDLE; else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_cnt_next <= 0; - end if; + mem_addr_base_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + mem_cnt_next <= mem_cnt + 2; -- Skip Next Step + end if; + else + mem_addr_base_next <= mem_addr_latch; + mem_addr_latch_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + mem_cnt_next <= mem_cnt + 1; end if; end if; - when others => + -- SET Prev Addr (Next Slot) + when 5 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_PREV_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH)); + + if (mem_ready_in = '1') then + if (mem_addr_latch = ENDPOINT_MEMORY_MAX_ADDRESS) then + -- Set New Occupied List Head + mem_occupied_head_next <= mem_addr_base; + -- DONE + mem_stage_next <= IDLE; + else + mem_addr_base_next <= mem_addr_latch; + mem_addr_latch_next <= mem_addr_base; + mem_cnt_next <= mem_cnt + 1; + end if; + end if; + -- SET Next Addr (Previous Slot) + when 6 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH)); + + if (mem_ready_in = '1') then + mem_addr_base_next <= mem_addr_latch; + -- DONE + mem_stage_next <= IDLE; + end if; + when others => null; end case; when GET_NEXT_ENDPOINT => case (mem_cnt) is - -- GET Entity ID + -- GET Next Addr when 0 => mem_valid_in <= '1'; mem_read <= '1'; - mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; -- Memory Flow Control Guard if (mem_ready_in = '1') then - mem_cnt_next <= 1; + mem_cnt_next <= mem_cnt + 1; end if; - -- READ Entity ID + -- READ Next Addr when 1 => mem_ready_out <= '1'; -- Memory Flow Control Guard if (mem_valid_out = '1') then - -- Slot Occupied - if (mem_read_data /= ENTITYID_UNKNOWN) then + if (resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH) = ENDPOINT_MEMORY_MAX_ADDRESS) then + mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + -- DONE + mem_stage_next <= IDLE; + else -- Fetch Endpoint Data - mem_stage_next <= GET_ENDPOINT_DATA; - mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + mem_addr_base_next <= resize(unsigned(mem_read_data),ENDPOINT_MEMORY_ADDR_WIDTH); + + mem_stage_next <= GET_ENDPOINT_DATA; if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then mem_cnt_next <= 0; elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then @@ -3733,19 +3860,6 @@ begin -- DONE mem_stage_next <= IDLE; end if; - -- Slot Empty - else - -- Reached End of Memory, No Match - if (mem_addr_base = max_endpoint_addr) then - mem_addr_base_next <= ENDPOINT_MEMORY_MAX_ADDRESS; --No match - -- DONE - mem_stage_next <= IDLE; - else - -- Continue Search - mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; - mem_pos_next <= mem_pos + 1; - mem_cnt_next <= 0; - end if; end if; end if; when others => @@ -3753,32 +3867,44 @@ begin end case; when RESET_MEMORY => case (mem_cnt) is - -- Initiate Reset + -- SET Next Pointer when 0 => - mem_addr_base_next <= FIRST_ENDPOINT_ADDRESS; - mem_cnt_next <= mem_cnt + 1; - -- Reset Memory - when 1 => mem_valid_in <= '1'; - mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; - mem_write_data <= ENTITYID_UNKNOWN; + mem_addr <= mem_addr_base + EMF_NEXT_ADDR_OFFSET; + if (mem_addr_base = MAX_ENDPOINT_ADDRESS) then + mem_write_data <= std_logic_vector(resize(ENDPOINT_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + else + mem_write_data <= std_logic_vector(resize(mem_addr_base + ENDPOINT_FRAME_SIZE,WORD_WIDTH)); + end if; + + -- Memory Flow Control Guard + if (mem_ready_in = '1') then + mem_cnt_next <= mem_cnt + 1; + end if; + -- SET Previous Pointer + when 1 => + mem_valid_in <= '1'; + mem_addr <= mem_addr_base + EMF_PREV_ADDR_OFFSET; + mem_write_data <= std_logic_vector(resize(mem_addr_latch,WORD_WIDTH)); -- Memory Flow Control Guard if (mem_ready_in = '1') then - -- End of Memory if (mem_addr_base = MAX_ENDPOINT_ADDRESS) then + -- Initialize Empty and Occupied Heads + mem_empty_head_next <= FIRST_ENDPOINT_ADDRESS; + mem_occupied_head_next <= ENDPOINT_MEMORY_MAX_ADDRESS; + -- DONE mem_stage_next <= IDLE; else - -- Next Endpoint Frame + mem_addr_latch_next <= mem_addr_base; mem_addr_base_next <= mem_addr_base + ENDPOINT_FRAME_SIZE; + mem_cnt_next <= 0; end if; end if; when others => null; end case; - when others => - null; end case; end process; @@ -3805,7 +3931,6 @@ begin nack_bitmap_pos <= 0; req_bitmap_pos <= 0; mem_cnt <= 0; - mem_pos <= 0; return_cnt <= 0; gap_is_last <= '0'; is_meta <= '0'; @@ -3823,10 +3948,10 @@ begin count <= (others => '0'); long_latch <= (others => '0'); req_seq_nr_bitmap <= (others => '0'); - mem_addr_base <= (others => '0'); - last_addr <= (others => '0'); - mem_addr_latch <= (others => '0'); - max_endpoint_addr <= (others => '0'); + mem_addr_base <= FIRST_ENDPOINT_ADDRESS; + mem_occupied_head <= ENDPOINT_MEMORY_MAX_ADDRESS; + mem_empty_head <= ENDPOINT_MEMORY_MAX_ADDRESS; + mem_addr_latch <= ENDPOINT_MEMORY_MAX_ADDRESS; current_emf <= (others => '0'); global_ack_seq_nr_base <= SEQUENCENUMBER_UNKNOWN; last_seq_nr <= ZERO_SEQUENCENUMBER; @@ -3851,7 +3976,6 @@ begin nack_bitmap_pos <= nack_bitmap_pos_next; req_bitmap_pos <= req_bitmap_pos_next; mem_cnt <= mem_cnt_next; - mem_pos <= mem_pos_next; return_cnt <= return_cnt_next; gap_is_last <= gap_is_last_next; is_meta <= is_meta_next; @@ -3870,9 +3994,9 @@ begin long_latch <= long_latch_next; req_seq_nr_bitmap <= req_seq_nr_bitmap_next; mem_addr_base <= mem_addr_base_next; - last_addr <= last_addr_next; + mem_occupied_head <= mem_occupied_head_next; + mem_empty_head <= mem_empty_head_next; mem_addr_latch <= mem_addr_latch_next; - max_endpoint_addr <= max_endpoint_addr_next; current_emf <= current_emf_next; global_ack_seq_nr_base <= global_ack_seq_nr_base_next; last_seq_nr <= last_seq_nr_next;