greek64/rtps-fpga
2
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

CYCLONE DDS COMPATIBILITY: Add start delay in ROS action Server

Browse Source 
Even with the previous commits, there still exist race conditions in
which if the Cyclone DDS implementation receives the initial HEARTBEAT
after the message has been sent, it is silently dropped (Volatile behaviour).
And since the Cyclone DDS implementation is ignoring HEARTBEATs of
yet unmatched endpoints (which is what happens to our init HEARTBEAT),
the best way to counter this is to just wait after the reception of the
first Cyclone DDS message (which signifies that it has matched all our
endpoints) until the HEARTBEAT timeout has also sent the respective
initial HEARTBEATs.
This commit is contained in:
John Ring 2022-04-16 20:01:37 +02:00
parent 6bfcc241c2
commit 1efeeef279
1 changed files with 30 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
src/ros2/Tests/Fibonacci.vhd
View File

@ -71,7 +71,7 @@ end entity;
architecture arch of Fibonacci is
--*****TYPE DECLARATION*****
type STAGE_TYPE is (IDLE,START_EXECUTION,INITIALIZE_EXECUTION,EXECUTE,FEEDBACK,TIMER,FINALIZE,CANCEL);
type STAGE_TYPE is (IDLE,DELAY_START,START_EXECUTION,INITIALIZE_EXECUTION,EXECUTE,FEEDBACK,TIMER,FINALIZE,CANCEL);
--*****SIGNAL DECLARATION*****
signal stage, stage_next : STAGE_TYPE;
@ -123,19 +123,35 @@ begin
case (stage) is
when IDLE =>
if (new_goal_request = '1') then
new_goal_accepted <= '1';
new_goal_response <= '1';
-- Latch DATA
order_next <= unsigned(new_goal_order);
handle_next <= new_goal_handle;
ind_next <= new_goal_result_index;
stage_next <= START_EXECUTION;
cnt_next <= 0;
elsif (cancel_request = '1') then
cancel_response <= '1';
-- NOTE: Because of race conditions that can occur with the Cyclone DDS implementation, we wait
-- 2 seconds to make sure that all remote readers have received an initial HEARTBEAT.
if (new_goal_request = '1' or cancel_request = '1') then
-- NOTE: During simulation we essentially skip the timer
if (ros_config.SIMULATION_TIMING) then
deadline_next <= time;
else
deadline_next.sec <= std_logic_vector(unsigned(time.sec) + 2);
deadline_next.nanosec <= time.nanosec;
end if;
stage_next <= DELAY_START;
end if;
when DELAY_START =>
if (deadline <= time) then
if (new_goal_request = '1') then
new_goal_accepted <= '1';
new_goal_response <= '1';
-- Latch DATA
order_next <= unsigned(new_goal_order);
handle_next <= new_goal_handle;
ind_next <= new_goal_result_index;
stage_next <= START_EXECUTION;
cnt_next <= 0;
elsif (cancel_request = '1') then
cancel_response <= '1';
stage_next <= IDLE;
end if;
end if;
when START_EXECUTION =>
case (cnt) is