diff --git a/sim/modelsim.ini b/sim/modelsim.ini index ea112b1..020467f 100644 --- a/sim/modelsim.ini +++ b/sim/modelsim.ini @@ -19,7 +19,11 @@ others = $MODEL_TECH/../modelsim.ini default = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/default.lib osvvm = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/osvvm.lib -Testbench-Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench-Lib1.lib +Testbench_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib2.lib +Testbench_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib3.lib +Testbench_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib1.lib +Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/QuestaSim-2021.04/Lib1.lib +Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/QuestaSim-2021.04/Lib3.lib [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. @@ -131,6 +135,11 @@ NoRangeCheck = 0 ; Show_Lint = 1 [vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ns diff --git a/src/TEMPLATE_key_holder.vhd b/src/TEMPLATE_key_holder.vhd index 426f28c..a948907 100644 --- a/src/TEMPLATE_key_holder.vhd +++ b/src/TEMPLATE_key_holder.vhd @@ -440,9 +440,16 @@ begin null; end case; + -- ABORT + if (abort = '1' and stage /= IDLE) then + stage_next <= IDLE; + -- Reset + last_word_in_latch_next <= '0'; + align_op_next <= '0'; + finalize_payload_next <= '0'; -- OVERREAD GUARD -- Attempted read on empty input - if (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then + elsif (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then stage_next <= SKIP_PAYLOAD; decode_error_latch_next <= '1'; end if; diff --git a/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd b/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd index efbd542..7163b1b 100644 --- a/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd +++ b/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd @@ -81,6 +81,7 @@ begin opcode => opcode_kh, ack => ack_kh, decode_error => decode_error, + abort => '0', data_in => data_kh_in, valid_in => valid_kh_in, ready_in => ready_kh_in, diff --git a/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd b/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd index 4611911..ada7bd0 100644 --- a/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd +++ b/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd @@ -84,6 +84,7 @@ begin opcode => opcode_kh, ack => ack_kh, decode_error => decode_error, + abort => '0', data_in => data_kh_in, valid_in => valid_kh_in, ready_in => ready_kh_in, diff --git a/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd b/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd index 7d17a7b..9fabe94 100644 --- a/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd +++ b/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd @@ -153,6 +153,7 @@ begin opcode => opcode_kh, ack => ack_kh, decode_error => decode_error, + abort => '0', data_in => data_kh_in, valid_in => valid_kh_in, ready_in => ready_kh_in, diff --git a/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd b/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd index aa1ce8f..f525fa6 100644 --- a/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd +++ b/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd @@ -156,6 +156,7 @@ begin opcode => opcode_kh, ack => ack_kh, decode_error => decode_error, + abort => '0', data_in => data_kh_in, valid_in => valid_kh_in, ready_in => ready_kh_in, diff --git a/src/Tests/Type1_key_holder.vhd b/src/Tests/Type1_key_holder.vhd index 74afab7..9122763 100644 --- a/src/Tests/Type1_key_holder.vhd +++ b/src/Tests/Type1_key_holder.vhd @@ -455,9 +455,17 @@ begin null; end case; + + -- ABORT + if (abort = '1' and stage /= IDLE) then + stage_next <= IDLE; + -- Reset + last_word_in_latch_next <= '0'; + align_op_next <= '0'; + finalize_payload_next <= '0'; -- OVERREAD GUARD -- Attempted read on empty input - if (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then + elsif (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then stage_next <= SKIP_PAYLOAD; decode_error_latch_next <= '1'; end if; diff --git a/src/Tests/Type2_key_holder.vhd b/src/Tests/Type2_key_holder.vhd index 8273556..b0a781d 100644 --- a/src/Tests/Type2_key_holder.vhd +++ b/src/Tests/Type2_key_holder.vhd @@ -731,9 +731,16 @@ begin null; end case; + -- ABORT + if (abort = '1' and stage /= IDLE) then + stage_next <= IDLE; + -- Reset + last_word_in_latch_next <= '0'; + align_op_next <= '0'; + finalize_payload_next <= '0'; -- OVERREAD GUARD -- Attempted read on empty input - if (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then + elsif (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then stage_next <= SKIP_PAYLOAD; decode_error_latch_next <= '1'; end if; diff --git a/src/key_holder.vhd b/src/key_holder.vhd index 1fd2e9d..32d7bcb 100644 --- a/src/key_holder.vhd +++ b/src/key_holder.vhd @@ -14,6 +14,7 @@ entity key_holder is opcode : in KEY_HOLDER_OPCODE_TYPE; ack : out std_logic; decode_error : out std_logic; + abort : in std_logic; data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); valid_in : in std_logic;