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Bug Fix: DDS Reader and Writer Interfaces had no signal passthrough for non-Type dependent Operations

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The ready/valid Signals were missing from the DDS Reader and Writer Interfaces,
preventing the user from effectively using non-Type dependent operations
(like GET_OFFERED_DEADLINE_MISSED_STATUS).
The L1_Type1_test1 was extended to test for this non-type dependent operation.
This commit is contained in:
John Ring 2023-06-17 13:32:58 +02:00
parent d2d40c1326
commit 35baf341c7
20 changed files with 300 additions and 96 deletions
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22
src/TEMPLATE_reader_interface.vhd
View File

@ -48,6 +48,10 @@ entity TYPENAME_reader_interface is
get_data_user : in std_logic; get_data_user : in std_logic;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Sample Info -- Sample Info
sample_info_user : out SAMPLE_INFO_TYPE; sample_info_user : out SAMPLE_INFO_TYPE;
sample_info_valid_user : out std_logic; sample_info_valid_user : out std_logic;
@ -87,7 +91,7 @@ architecture arch of TYPENAME_reader_interface is
signal optional, optional_next : std_logic; signal optional, optional_next : std_logic;
signal abort_mem : std_logic; signal abort_mem : std_logic;
signal ready_in_dds_sig : std_logic; signal ready_in_dds_sig : std_logic;
signal valid_sig, valid_sig_next : std_logic; signal valid_latch, valid_latch_next : std_logic;
signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE;
signal return_stage, return_stage_next : DECODE_STAGE_TYPE; signal return_stage, return_stage_next : DECODE_STAGE_TYPE;
-- ###GENERATED START### -- ###GENERATED START###
@ -125,7 +129,7 @@ begin
eoc_user <= eoc_dds; eoc_user <= eoc_dds;
status_user <= status_dds; status_user <= status_dds;
valid <= valid_sig; valid <= valid_latch;
decode_error <= decode_error_latch; decode_error <= decode_error_latch;
ready_in_dds <= ready_in_dds_sig; ready_in_dds <= ready_in_dds_sig;
@ -147,7 +151,7 @@ begin
align_offset_next <= align_offset; align_offset_next <= align_offset;
target_align_next <= target_align; target_align_next <= target_align;
optional_next <= optional; optional_next <= optional;
valid_sig_next <= valid_sig; valid_latch_next <= valid_latch;
data_in_latch_next <= data_in_latch; data_in_latch_next <= data_in_latch;
align_op_next <= align_op; align_op_next <= align_op;
abort_mem <= '0'; abort_mem <= '0';
@ -168,9 +172,13 @@ begin
stage_next <= GET_PAYLOAD_HEADER; stage_next <= GET_PAYLOAD_HEADER;
-- RESET -- RESET
decode_error_latch_next <= '0'; decode_error_latch_next <= '0';
valid_sig_next <= '0'; valid_latch_next <= '0';
abort_mem <= '1'; abort_mem <= '1';
else else
valid_out_user <= valid_in_dds;
ready_in_dds_sig <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
-- ###GENERATED START### -- ###GENERATED START###
-- MEMORY SIGNAL CONNECTIONS -- MEMORY SIGNAL CONNECTIONS
-- ###GENERATED END### -- ###GENERATED END###
@ -241,7 +249,7 @@ begin
-- If no Decode Error, mark output as valid -- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then if (decode_error_latch = '0') then
valid_sig_next <= '1'; valid_latch_next <= '1';
end if; end if;
-- Reset -- Reset
@ -331,7 +339,7 @@ begin
last_word_in_latch <= '0'; last_word_in_latch <= '0';
decode_error_latch <= '0'; decode_error_latch <= '0';
optional <= '0'; optional <= '0';
valid_sig <= '0'; valid_latch <= '0';
align_op <= '0'; align_op <= '0';
align_offset <= (others => '0'); align_offset <= (others => '0');
data_in_latch <= (others => '0'); data_in_latch <= (others => '0');
@ -348,7 +356,7 @@ begin
last_word_in_latch <= last_word_in_latch_next; last_word_in_latch <= last_word_in_latch_next;
decode_error_latch <= decode_error_latch_next; decode_error_latch <= decode_error_latch_next;
optional <= optional_next; optional <= optional_next;
valid_sig <= valid_sig_next; valid_latch <= valid_latch_next;
align_op <= align_op_next; align_op <= align_op_next;
align_offset <= align_offset_next; align_offset <= align_offset_next;
data_in_latch <= data_in_latch_next; data_in_latch <= data_in_latch_next;

9
src/TEMPLATE_writer_interface.vhd
View File

@ -47,6 +47,10 @@ entity TYPENAME_writer_interface is
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_user : out INSTANCE_HANDLE_TYPE; instance_handle_out_user : out INSTANCE_HANDLE_TYPE;
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Communication Status -- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
@ -100,6 +104,10 @@ begin
return_code_user <= return_code_dds; return_code_user <= return_code_dds;
instance_handle_out_user <= instance_handle_out_dds; instance_handle_out_user <= instance_handle_out_dds;
status_user <= status_dds; status_user <= status_dds;
valid_out_user <= valid_in_dds;
ready_in_dds <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
-- ###GENERATED START### -- ###GENERATED START###
-- PORT SIGNAL CONNECTIONS -- PORT SIGNAL CONNECTIONS
@ -118,7 +126,6 @@ begin
finalize_payload_next <= finalize_payload; finalize_payload_next <= finalize_payload;
abort_mem <= '0'; abort_mem <= '0';
encode_done <= '0'; encode_done <= '0';
ready_in_dds <= '0';
valid_out_dds <= '0'; valid_out_dds <= '0';
last_word_out_dds <= '0'; last_word_out_dds <= '0';
data_out_dds <= (others => '0'); data_out_dds <= (others => '0');

8
src/Tests/Level_1/L1_Type1_interface_test1.vhd
View File

@ -75,6 +75,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
id => id_in, id => id_in,
a => a_in, a => a_in,
@ -116,6 +120,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
sample_info_user => open, sample_info_user => open,
sample_info_valid_user => open, sample_info_valid_user => open,
sample_info_ack_user => '1', sample_info_ack_user => '1',

8
src/Tests/Level_1/L1_Type1_interface_test2.vhd
View File

@ -78,6 +78,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
id => id_in, id => id_in,
a => a_in, a => a_in,
@ -119,6 +123,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
sample_info_user => open, sample_info_user => open,
sample_info_valid_user => open, sample_info_valid_user => open,
sample_info_ack_user => '1', sample_info_ack_user => '1',

4
src/Tests/Level_1/L1_Type1_key_holder_test1.vhd
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@ -67,6 +67,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
encode_done => encode_done, encode_done => encode_done,
id => id_in, id => id_in,

4
src/Tests/Level_1/L1_Type1_key_holder_test2.vhd
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@ -70,6 +70,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
encode_done => encode_done, encode_done => encode_done,
id => id_in, id => id_in,

8
src/Tests/Level_1/L1_Type2_interface_test1.vhd
View File

@ -97,6 +97,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
id => id_in, id => id_in,
TestSequence_len => TestSequence_len_in, TestSequence_len => TestSequence_len_in,
@ -188,6 +192,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
sample_info_user => open, sample_info_user => open,
sample_info_valid_user => open, sample_info_valid_user => open,
sample_info_ack_user => '1', sample_info_ack_user => '1',

8
src/Tests/Level_1/L1_Type2_interface_test2.vhd
View File

@ -100,6 +100,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
id => id_in, id => id_in,
TestSequence_len => TestSequence_len_in, TestSequence_len => TestSequence_len_in,
@ -191,6 +195,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
sample_info_user => open, sample_info_user => open,
sample_info_valid_user => open, sample_info_valid_user => open,
sample_info_ack_user => '1', sample_info_ack_user => '1',

4
src/Tests/Level_1/L1_Type2_key_holder_test1.vhd
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@ -89,6 +89,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
encode_done => encode_done, encode_done => encode_done,
id => id_in, id => id_in,

4
src/Tests/Level_1/L1_Type2_key_holder_test2.vhd
View File

@ -92,6 +92,10 @@ begin
done_user => open, done_user => open,
return_code_user => open, return_code_user => open,
instance_handle_out_user => open, instance_handle_out_user => open,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
status_user => open, status_user => open,
encode_done => encode_done, encode_done => encode_done,
id => id_in, id => id_in,

8
src/Tests/Level_2/L2_Testbench_Lib2.vhd
View File

@ -34,6 +34,10 @@ entity L2_Testbench_Lib2 is
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_user : out INSTANCE_HANDLE_TYPE; instance_handle_out_user : out INSTANCE_HANDLE_TYPE;
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Communication Status -- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- ###GENERATED START### -- ###GENERATED START###
@ -574,6 +578,10 @@ begin
done_user => done_user, done_user => done_user,
return_code_user => return_code_user, return_code_user => return_code_user,
instance_handle_out_user => instance_handle_out_user, instance_handle_out_user => instance_handle_out_user,
valid_out_user => valid_out_user,
ready_out_user => ready_out_user,
data_out_user => data_out_user,
last_word_out_user => last_word_out_user,
-- Communication Status -- Communication Status
status_user => status_user, status_user => status_user,
-- ###GENERATED START### -- ###GENERATED START###

8
src/Tests/Level_2/L2_Testbench_Lib3.vhd
View File

@ -36,6 +36,10 @@ entity L2_Testbench_Lib3 is
get_data_user : in std_logic; get_data_user : in std_logic;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
sample_info_user : out SAMPLE_INFO_TYPE; sample_info_user : out SAMPLE_INFO_TYPE;
sample_info_valid_user : out std_logic; sample_info_valid_user : out std_logic;
sample_info_ack_user : in std_logic; sample_info_ack_user : in std_logic;
@ -585,6 +589,10 @@ begin
get_data_user => get_data_user, get_data_user => get_data_user,
done_user => done_user, done_user => done_user,
return_code_user => return_code_user, return_code_user => return_code_user,
valid_out_user => valid_out_user,
ready_out_user => ready_out_user,
data_out_user => data_out_user,
last_word_out_user => last_word_out_user,
sample_info_user => sample_info_user, sample_info_user => sample_info_user,
sample_info_valid_user => sample_info_valid_user, sample_info_valid_user => sample_info_valid_user,
sample_info_ack_user => sample_info_ack_user, sample_info_ack_user => sample_info_ack_user,

8
src/Tests/Level_2/L2_Testbench_Lib4.vhd
View File

@ -581,6 +581,10 @@ begin
get_data_user => get_data_user_ri, get_data_user => get_data_user_ri,
done_user => done_ri_user, done_user => done_ri_user,
return_code_user => return_code_ri_user, return_code_user => return_code_ri_user,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
sample_info_user => sample_info_ri_user, sample_info_user => sample_info_ri_user,
sample_info_valid_user => sample_info_valid_ri_user, sample_info_valid_user => sample_info_valid_ri_user,
sample_info_ack_user => sample_info_ack_user_ri, sample_info_ack_user => sample_info_ack_user_ri,
@ -631,6 +635,10 @@ begin
done_user => done_wi_user, done_user => done_wi_user,
return_code_user => return_code_wi_user, return_code_user => return_code_wi_user,
instance_handle_out_user => instance_handle_wi_user, instance_handle_out_user => instance_handle_wi_user,
valid_out_user => open,
ready_out_user => '1',
data_out_user => open,
last_word_out_user => open,
-- Communication Status -- Communication Status
status_user => status_wi_user, status_user => status_wi_user,
-- ###GENERATED START### -- ###GENERATED START###

16
src/Tests/Level_2/L2_Testbench_Lib5.vhd
View File

@ -36,6 +36,10 @@ entity L2_Testbench_Lib5 is
get_data_r : in std_logic; get_data_r : in std_logic;
done_r : out std_logic; done_r : out std_logic;
return_code_r : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_r : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
valid_out_r : out std_logic;
ready_out_r : in std_logic;
data_out_r : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_r : out std_logic;
sample_info_r : out SAMPLE_INFO_TYPE; sample_info_r : out SAMPLE_INFO_TYPE;
sample_info_valid_r : out std_logic; sample_info_valid_r : out std_logic;
sample_info_ack_r : in std_logic; sample_info_ack_r : in std_logic;
@ -55,6 +59,10 @@ entity L2_Testbench_Lib5 is
done_w : out std_logic; done_w : out std_logic;
return_code_w : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_w : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_w : out INSTANCE_HANDLE_TYPE; instance_handle_out_w : out INSTANCE_HANDLE_TYPE;
valid_out_w : out std_logic;
ready_out_w : in std_logic;
data_out_w : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_w : out std_logic;
status_w : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_w : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
id_w : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0); id_w : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
a_w : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0); a_w : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
@ -596,6 +604,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => done_r, done_user => done_r,
return_code_user => return_code_r, return_code_user => return_code_r,
valid_out_user => valid_out_r,
ready_out_user => ready_out_r,
data_out_user => data_out_r,
last_word_out_user => last_word_out_r,
sample_info_user => sample_info_r, sample_info_user => sample_info_r,
sample_info_valid_user => sample_info_valid_r, sample_info_valid_user => sample_info_valid_r,
sample_info_ack_user => sample_info_ack_r, sample_info_ack_user => sample_info_ack_r,
@ -646,6 +658,10 @@ begin
done_user => done_w, done_user => done_w,
return_code_user => return_code_w, return_code_user => return_code_w,
instance_handle_out_user => instance_handle_out_w, instance_handle_out_user => instance_handle_out_w,
valid_out_user => valid_out_w,
ready_out_user => ready_out_w,
data_out_user => data_out_w,
last_word_out_user => last_word_out_w,
-- Communication Status -- Communication Status
status_user => status_w, status_user => status_w,
-- ###GENERATED START### -- ###GENERATED START###

100
src/Tests/Level_2/L2_Type1_test1.vhd
View File

@ -47,7 +47,7 @@ architecture testbench of L2_Type1_test1 is
signal clk, reset : std_logic := '0'; signal clk, reset : std_logic := '0';
signal time : TIME_TYPE := TIME_ZERO; signal time : TIME_TYPE := TIME_ZERO;
-- INPUT -- INPUT
signal start_w, ack_w, done_w, ready_out_w, valid_out_w, last_word_out_w, encode_done_w, empty_rtps_w, full_rtps_w, rd_rtps_w, wr_rtps_w : std_logic := '0'; signal start_w, ack_w, done_w, ready_out_w, ready_out_r, valid_out_w, valid_out_r, last_word_out_w, last_word_out_r, encode_done_w, empty_rtps_w, full_rtps_w, rd_rtps_w, wr_rtps_w : std_logic := '0';
--signal opcode_w : Testbench_Lib2.rtps_config_package.DDS_WRITER_OPCODE_TYPE := Testbench_Lib2.rtps_config_package.DDS_WRITER_OPCODE_TYPE'(NOP); --signal opcode_w : Testbench_Lib2.rtps_config_package.DDS_WRITER_OPCODE_TYPE := Testbench_Lib2.rtps_config_package.DDS_WRITER_OPCODE_TYPE'(NOP);
signal opcode_w : DDS_WRITER_OPCODE_TYPE; signal opcode_w : DDS_WRITER_OPCODE_TYPE;
signal instance_handle_in_w : INSTANCE_HANDLE_TYPE := HANDLE_NIL; signal instance_handle_in_w : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -55,7 +55,7 @@ architecture testbench of L2_Type1_test1 is
signal source_ts_w : TIME_TYPE := TIME_INVALID; signal source_ts_w : TIME_TYPE := TIME_INVALID;
signal max_wait_w : DURATION_TYPE := DURATION_ZERO; signal max_wait_w : DURATION_TYPE := DURATION_ZERO;
signal return_code_w : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_OK; signal return_code_w : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_OK;
signal data_out_w, data_in_rtps_w, data_out_rtps_w : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_out_w, data_out_r, data_in_rtps_w, data_out_rtps_w : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal status_w : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal status_w : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal id_w, a_w : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal id_w, a_w : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
@ -75,6 +75,8 @@ architecture testbench of L2_Type1_test1 is
signal id1, id2, id3, a1, a2, a3 : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal id1, id2, id3, a1, a2, a3 : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal inst1, inst2, inst3 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; signal inst1, inst2, inst3 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
signal sample, data_out : AlertLogIDType;
-- HACK: For some reason (possibly Modelsim/Questasim Bug) I cannot declare the opcode signals from their respective Library sources, -- HACK: For some reason (possibly Modelsim/Questasim Bug) I cannot declare the opcode signals from their respective Library sources,
-- because I cannot use a qualified expression to define an enumeration literal (and direct type casting cannot be done because -- because I cannot use a qualified expression to define an enumeration literal (and direct type casting cannot be done because
-- the types are not closely related). So I have to do define explicit type conversions between the types... -- the types are not closely related). So I have to do define explicit type conversions between the types...
@ -115,6 +117,10 @@ begin
done_user => done_w, done_user => done_w,
return_code_user => return_code_w, return_code_user => return_code_w,
instance_handle_out_user => instance_handle_out_w, instance_handle_out_user => instance_handle_out_w,
valid_out_user => valid_out_w,
ready_out_user => ready_out_w,
data_out_user => data_out_w,
last_word_out_user => last_word_out_w,
-- Communication Status -- Communication Status
status_user => status_w, status_user => status_w,
-- ###GENERATED START### -- ###GENERATED START###
@ -186,6 +192,10 @@ begin
get_data_user => get_data_r, get_data_user => get_data_r,
done_user => done_r, done_user => done_r,
return_code_user => return_code_r, return_code_user => return_code_r,
valid_out_user => valid_out_r,
ready_out_user => ready_out_r,
data_out_user => data_out_r,
last_word_out_user => last_word_out_r,
sample_info_user => sample_info_r, sample_info_user => sample_info_r,
sample_info_valid_user => sample_info_valid_r, sample_info_valid_user => sample_info_valid_r,
sample_info_ack_user => sample_info_ack_r, sample_info_ack_user => sample_info_ack_r,
@ -262,6 +272,8 @@ begin
SetLogEnable(PASSED, FALSE); SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE); SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name); RV.InitSeed(RV'instance_name);
sample <= GetAlertLogID("DDS Sample", ALERTLOG_BASE_ID);
data_out <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
id1 <= RV.RandSlv(CDR_LONG_WIDTH); id1 <= RV.RandSlv(CDR_LONG_WIDTH);
id2 <= RV.RandSlv(CDR_LONG_WIDTH); id2 <= RV.RandSlv(CDR_LONG_WIDTH);
@ -372,7 +384,7 @@ begin
wait_on_sig(sample_info_valid_r); wait_on_sig(sample_info_valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR); AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR);
AffirmIfEqual(to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst1)); AffirmIfEqual(sample, to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst1));
sample_info_ack_r <= '1'; sample_info_ack_r <= '1';
get_data_r <= '1'; get_data_r <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -380,8 +392,8 @@ begin
get_data_r <= '0'; get_data_r <= '0';
wait_on_sig(valid_r); wait_on_sig(valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AffirmIfEqual(id_r, id1); AffirmIfEqual(sample, id_r, id1);
AffirmIfEqual(a_r, a1); AffirmIfEqual(sample, a_r, a1);
wait_on_sig(eoc_r); wait_on_sig(eoc_r);
wait until rising_edge(clk); wait until rising_edge(clk);
@ -390,7 +402,7 @@ begin
wait_on_sig(sample_info_valid_r); wait_on_sig(sample_info_valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR); AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR);
AffirmIfEqual(to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst2)); AffirmIfEqual(sample, to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst2));
sample_info_ack_r <= '1'; sample_info_ack_r <= '1';
get_data_r <= '1'; get_data_r <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -398,8 +410,8 @@ begin
get_data_r <= '0'; get_data_r <= '0';
wait_on_sig(valid_r); wait_on_sig(valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AffirmIfEqual(id_r, id2); AffirmIfEqual(sample, id_r, id2);
AffirmIfEqual(a_r, a1); AffirmIfEqual(sample, a_r, a1);
wait_on_sig(eoc_r); wait_on_sig(eoc_r);
wait until rising_edge(clk); wait until rising_edge(clk);
@ -408,7 +420,7 @@ begin
wait_on_sig(sample_info_valid_r); wait_on_sig(sample_info_valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR); AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR);
AffirmIfEqual(to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst1)); AffirmIfEqual(sample, to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst1));
sample_info_ack_r <= '1'; sample_info_ack_r <= '1';
get_data_r <= '1'; get_data_r <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -416,8 +428,8 @@ begin
get_data_r <= '0'; get_data_r <= '0';
wait_on_sig(valid_r); wait_on_sig(valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AffirmIfEqual(id_r, id1); AffirmIfEqual(sample, id_r, id1);
AffirmIfEqual(a_r, a2); AffirmIfEqual(sample, a_r, a2);
wait_on_sig(eoc_r); wait_on_sig(eoc_r);
wait until rising_edge(clk); wait until rising_edge(clk);
@ -426,7 +438,7 @@ begin
wait_on_sig(sample_info_valid_r); wait_on_sig(sample_info_valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR); AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR);
AffirmIfEqual(to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst2)); AffirmIfEqual(sample, to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst2));
sample_info_ack_r <= '1'; sample_info_ack_r <= '1';
get_data_r <= '1'; get_data_r <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -434,8 +446,8 @@ begin
get_data_r <= '0'; get_data_r <= '0';
wait_on_sig(valid_r); wait_on_sig(valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AffirmIfEqual(id_r, id2); AffirmIfEqual(sample, id_r, id2);
AffirmIfEqual(a_r, a2); AffirmIfEqual(sample, a_r, a2);
wait_on_sig(eoc_r); wait_on_sig(eoc_r);
wait until rising_edge(clk); wait until rising_edge(clk);
@ -475,7 +487,7 @@ begin
wait_on_sig(sample_info_valid_r); wait_on_sig(sample_info_valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR); AlertIf(sample_info_r.valid_data /= '1', "Reader returned no Data", ERROR);
AffirmIfEqual(to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst3)); AffirmIfEqual(sample, to_unsigned(INSTANCE_HANDLE_TYPE(sample_info_r.instance_handle)), to_unsigned(inst3));
sample_info_ack_r <= '1'; sample_info_ack_r <= '1';
get_data_r <= '1'; get_data_r <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -483,11 +495,29 @@ begin
get_data_r <= '0'; get_data_r <= '0';
wait_on_sig(valid_r); wait_on_sig(valid_r);
wait for 1 ps; -- Make sure all signals stable wait for 1 ps; -- Make sure all signals stable
AffirmIfEqual(id_r, id3); AffirmIfEqual(sample, id_r, id3);
AffirmIfEqual(a_r, a3); AffirmIfEqual(sample, a_r, a3);
wait_on_sig(eoc_r); wait_on_sig(eoc_r);
wait until rising_edge(clk); wait until rising_edge(clk);
Log("Test non Type Related Writer Operation (GET_OFFERED_DEADLINE_MISSED_STATUS)", INFO);
start_w <= '1';
opcode_w <= GET_OFFERED_DEADLINE_MISSED_STATUS;
wait_on_sig(ack_w);
wait until rising_edge(clk);
start_w <= '0';
wait_on_sig(done_w);
wait_on_sig(last_word_out_w);
Log("Test non Type Related Reader Operation (GET_REQUESTED_DEADLINE_MISSED_STATUS)", INFO);
start_r <= '1';
opcode_r <= GET_REQUESTED_DEADLINE_MISSED_STATUS;
wait_on_sig(ack_r);
wait until rising_edge(clk);
start_r <= '0';
wait_on_sig(done_r);
wait_on_sig(last_word_out_r);
TranscriptOpen(RESULTS_FILE, APPEND_MODE); TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror; SetTranscriptMirror;
ReportAlerts; ReportAlerts;
@ -496,6 +526,42 @@ begin
wait; wait;
end process; end process;
check_out_w : process(all)
variable cnt : natural := 0;
begin
if rising_edge(clk) then
ready_out_w <= '1';
if (valid_out_w = '1') then
AffirmIfEqual(data_out, data_out_w, (data_out_w'range => '0'));
if (cnt = 5) then
AffirmIfEqual(data_out, last_word_out_w, '1');
cnt := 0;
else
AffirmIfEqual(data_out, last_word_out_w, '0');
cnt := cnt + 1;
end if;
end if;
end if;
end process;
check_out_r : process(all)
variable cnt : natural := 0;
begin
if rising_edge(clk) then
ready_out_r <= '1';
if (valid_out_r = '1') then
AffirmIfEqual(data_out, data_out_r, (data_out_r'range => '0'));
if (cnt = 5) then
AffirmIfEqual(data_out, last_word_out_r, '1');
cnt := 0;
else
AffirmIfEqual(data_out, last_word_out_r, '0');
cnt := cnt + 1;
end if;
end if;
end if;
end process;
clock_prc : process clock_prc : process
begin begin
clk <= '0'; clk <= '0';

8
src/Tests/Level_2/L2_Type1_test2.vhd
View File

@ -169,6 +169,10 @@ begin
get_data_r => get_data_r, get_data_r => get_data_r,
done_r => done_r, done_r => done_r,
return_code_r => return_code_r, return_code_r => return_code_r,
valid_out_r => open,
ready_out_r => '1',
data_out_r => open,
last_word_out_r => open,
sample_info_r => sample_info_r, sample_info_r => sample_info_r,
sample_info_valid_r => sample_info_valid_r, sample_info_valid_r => sample_info_valid_r,
sample_info_ack_r => sample_info_ack_r, sample_info_ack_r => sample_info_ack_r,
@ -188,6 +192,10 @@ begin
done_w => done_w, done_w => done_w,
return_code_w => return_code_w, return_code_w => return_code_w,
instance_handle_out_w => instance_handle_out_w, instance_handle_out_w => instance_handle_out_w,
valid_out_w => open,
ready_out_w => '1',
data_out_w => open,
last_word_out_w => open,
status_w => status_w, status_w => status_w,
id_w => id_w, id_w => id_w,
a_w => a_w, a_w => a_w,

16
src/Tests/Type1_reader_interface.vhd
View File

@ -26,11 +26,10 @@ entity Type1_reader_interface is
get_data_dds : out std_logic; get_data_dds : out std_logic;
done_dds : in std_logic; done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_in_dds : out std_logic;
valid_in_dds : in std_logic; valid_in_dds : in std_logic;
ready_in_dds : out std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic; last_word_in_dds : in std_logic;
-- Sample Info
sample_info_dds : in SAMPLE_INFO_TYPE; sample_info_dds : in SAMPLE_INFO_TYPE;
sample_info_valid_dds : in std_logic; sample_info_valid_dds : in std_logic;
sample_info_ack_dds : out std_logic; sample_info_ack_dds : out std_logic;
@ -50,6 +49,10 @@ entity Type1_reader_interface is
get_data_user : in std_logic; get_data_user : in std_logic;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Sample Info -- Sample Info
sample_info_user : out SAMPLE_INFO_TYPE; sample_info_user : out SAMPLE_INFO_TYPE;
sample_info_valid_user : out std_logic; sample_info_valid_user : out std_logic;
@ -138,7 +141,7 @@ begin
begin begin
-- DEFAULT -- DEFAULT
stage_next <= stage; stage_next <= stage;
decode_stage_next <= decode_stage; decode_stage_next <= decode_stage;
return_stage_next <= return_stage; return_stage_next <= return_stage;
cnt_next <= cnt; cnt_next <= cnt;
endian_flag_next <= endian_flag; endian_flag_next <= endian_flag;
@ -172,7 +175,10 @@ begin
valid_latch_next <= '0'; valid_latch_next <= '0';
abort_mem <= '1'; abort_mem <= '1';
else else
null; valid_out_user <= valid_in_dds;
ready_in_dds_sig <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
end if; end if;
when GET_PAYLOAD_HEADER => when GET_PAYLOAD_HEADER =>
-- TODO: Latch Offset from Options Field? -- TODO: Latch Offset from Options Field?
@ -309,7 +315,7 @@ begin
-- Llength -- Llength
when 2 => when 2 =>
stage_next <= FETCH; stage_next <= FETCH;
decode_stage_next <= return_stage; decode_stage_next <= return_stage;
cnt_next <= 0; cnt_next <= 0;
-- Alignment Reset -- Alignment Reset
align_offset_next <= (others => '0'); align_offset_next <= (others => '0');

71
src/Tests/Type1_writer_interface.vhd
View File

@ -15,48 +15,52 @@ entity Type1_writer_interface is
); );
port ( port (
-- SYSTEM -- SYSTEM
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
-- FROM DDS WRITER -- FROM DDS WRITER
start_dds : out std_logic; start_dds : out std_logic;
ack_dds : in std_logic; ack_dds : in std_logic;
opcode_dds : out DDS_WRITER_OPCODE_TYPE; opcode_dds : out DDS_WRITER_OPCODE_TYPE;
instance_handle_in_dds : out INSTANCE_HANDLE_TYPE; instance_handle_in_dds : out INSTANCE_HANDLE_TYPE;
source_ts_dds : out TIME_TYPE; source_ts_dds : out TIME_TYPE;
max_wait_dds : out DURATION_TYPE; max_wait_dds : out DURATION_TYPE;
done_dds : in std_logic; done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_dds : in INSTANCE_HANDLE_TYPE; instance_handle_out_dds : in INSTANCE_HANDLE_TYPE;
ready_out_dds : in std_logic; valid_out_dds : out std_logic;
valid_out_dds : out std_logic; ready_out_dds : in std_logic;
data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_dds : out std_logic; last_word_out_dds : out std_logic;
ready_in_dds : out std_logic; valid_in_dds : in std_logic;
valid_in_dds : in std_logic; ready_in_dds : out std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic; last_word_in_dds : in std_logic;
-- Communication Status -- Communication Status
status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- TO USER ENTITY -- TO USER ENTITY
start_user : in std_logic; start_user : in std_logic;
ack_user : out std_logic; ack_user : out std_logic;
opcode_user : in DDS_WRITER_OPCODE_TYPE; opcode_user : in DDS_WRITER_OPCODE_TYPE;
instance_handle_in_user : in INSTANCE_HANDLE_TYPE; instance_handle_in_user : in INSTANCE_HANDLE_TYPE;
source_ts_user : in TIME_TYPE; source_ts_user : in TIME_TYPE;
max_wait_user : in DURATION_TYPE; max_wait_user : in DURATION_TYPE;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_user : out INSTANCE_HANDLE_TYPE; instance_handle_out_user : out INSTANCE_HANDLE_TYPE;
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Communication Status -- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- ###GENERATED START### -- ###GENERATED START###
id : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0); id : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
a : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0); a : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
-- ###GENERATED END### -- ###GENERATED END###
encode_done : out std_logic encode_done : out std_logic
); );
end entity; end entity;
@ -95,6 +99,10 @@ begin
return_code_user <= return_code_dds; return_code_user <= return_code_dds;
instance_handle_out_user <= instance_handle_out_dds; instance_handle_out_user <= instance_handle_out_dds;
status_user <= status_dds; status_user <= status_dds;
valid_out_user <= valid_in_dds;
ready_in_dds <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
main_prc : process (all) main_prc : process (all)
begin begin
@ -109,7 +117,6 @@ begin
finalize_payload_next <= finalize_payload; finalize_payload_next <= finalize_payload;
abort_mem <= '0'; abort_mem <= '0';
encode_done <= '0'; encode_done <= '0';
ready_in_dds <= '0';
valid_out_dds <= '0'; valid_out_dds <= '0';
last_word_out_dds <= '0'; last_word_out_dds <= '0';
data_out_dds <= (others => '0'); data_out_dds <= (others => '0');

11
src/Tests/Type2_reader_interface.vhd
View File

@ -26,11 +26,10 @@ entity Type2_reader_interface is
get_data_dds : out std_logic; get_data_dds : out std_logic;
done_dds : in std_logic; done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_in_dds : out std_logic;
valid_in_dds : in std_logic; valid_in_dds : in std_logic;
ready_in_dds : out std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic; last_word_in_dds : in std_logic;
-- Sample Info
sample_info_dds : in SAMPLE_INFO_TYPE; sample_info_dds : in SAMPLE_INFO_TYPE;
sample_info_valid_dds : in std_logic; sample_info_valid_dds : in std_logic;
sample_info_ack_dds : out std_logic; sample_info_ack_dds : out std_logic;
@ -50,6 +49,10 @@ entity Type2_reader_interface is
get_data_user : in std_logic; get_data_user : in std_logic;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Sample Info -- Sample Info
sample_info_user : out SAMPLE_INFO_TYPE; sample_info_user : out SAMPLE_INFO_TYPE;
sample_info_valid_user : out std_logic; sample_info_valid_user : out std_logic;
@ -501,6 +504,10 @@ begin
valid_latch_next <= '0'; valid_latch_next <= '0';
abort_mem <= '1'; abort_mem <= '1';
else else
valid_out_user <= valid_in_dds;
ready_in_dds_sig <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
-- ###GENERATED START### -- ###GENERATED START###
TestSequence_ready <= TestSequence_TestChar_mem_ready_in and TestSequence_TestWChar_mem_ready_in and TestSequence_TestLongLong_mem_ready_in and TestSequence_TestLongDouble_mem_ready_in; TestSequence_ready <= TestSequence_TestChar_mem_ready_in and TestSequence_TestWChar_mem_ready_in and TestSequence_TestLongLong_mem_ready_in and TestSequence_TestLongDouble_mem_ready_in;
TestSequence_TestChar_mem_addr <= TestSequence_addr; TestSequence_TestChar_mem_addr <= TestSequence_addr;

71
src/Tests/Type2_writer_interface.vhd
View File

@ -15,41 +15,45 @@ entity Type2_writer_interface is
); );
port ( port (
-- SYSTEM -- SYSTEM
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
-- FROM DDS WRITER -- FROM DDS WRITER
start_dds : out std_logic; start_dds : out std_logic;
ack_dds : in std_logic; ack_dds : in std_logic;
opcode_dds : out DDS_WRITER_OPCODE_TYPE; opcode_dds : out DDS_WRITER_OPCODE_TYPE;
instance_handle_in_dds : out INSTANCE_HANDLE_TYPE; instance_handle_in_dds : out INSTANCE_HANDLE_TYPE;
source_ts_dds : out TIME_TYPE; source_ts_dds : out TIME_TYPE;
max_wait_dds : out DURATION_TYPE; max_wait_dds : out DURATION_TYPE;
done_dds : in std_logic; done_dds : in std_logic;
return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_dds : in INSTANCE_HANDLE_TYPE; instance_handle_out_dds : in INSTANCE_HANDLE_TYPE;
ready_out_dds : in std_logic; valid_out_dds : out std_logic;
valid_out_dds : out std_logic; ready_out_dds : in std_logic;
data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_dds : out std_logic; last_word_out_dds : out std_logic;
ready_in_dds : out std_logic; valid_in_dds : in std_logic;
valid_in_dds : in std_logic; ready_in_dds : out std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in_dds : in std_logic; last_word_in_dds : in std_logic;
-- Communication Status -- Communication Status
status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- TO USER ENTITY -- TO USER ENTITY
start_user : in std_logic; start_user : in std_logic;
ack_user : out std_logic; ack_user : out std_logic;
opcode_user : in DDS_WRITER_OPCODE_TYPE; opcode_user : in DDS_WRITER_OPCODE_TYPE;
instance_handle_in_user : in INSTANCE_HANDLE_TYPE; instance_handle_in_user : in INSTANCE_HANDLE_TYPE;
source_ts_user : in TIME_TYPE; source_ts_user : in TIME_TYPE;
max_wait_user : in DURATION_TYPE; max_wait_user : in DURATION_TYPE;
done_user : out std_logic; done_user : out std_logic;
return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_user : out INSTANCE_HANDLE_TYPE; instance_handle_out_user : out INSTANCE_HANDLE_TYPE;
valid_out_user : out std_logic;
ready_out_user : in std_logic;
data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_user : out std_logic;
-- Communication Status -- Communication Status
status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
-- ###GENERATED START### -- ###GENERATED START###
id : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0); id : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
@ -106,7 +110,7 @@ entity Type2_writer_interface is
TestString_w : in std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); TestString_w : in std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
-- ###GENERATED END### -- ###GENERATED END###
encode_done : out std_logic encode_done : out std_logic
); );
end entity; end entity;
@ -350,6 +354,10 @@ begin
return_code_user <= return_code_dds; return_code_user <= return_code_dds;
instance_handle_out_user <= instance_handle_out_dds; instance_handle_out_user <= instance_handle_out_dds;
status_user <= status_dds; status_user <= status_dds;
valid_out_user <= valid_in_dds;
ready_in_dds <= ready_out_user;
data_out_user <= data_in_dds;
last_word_out_user <= last_word_in_dds;
-- ###GENERATED START### -- ###GENERATED START###
TestSequence_valid <= TestSequence_TestChar_mem_valid_out and TestSequence_TestWChar_mem_valid_out and TestSequence_TestLongLong_mem_valid_out and TestSequence_TestLongDouble_mem_valid_out; TestSequence_valid <= TestSequence_TestChar_mem_valid_out and TestSequence_TestWChar_mem_valid_out and TestSequence_TestLongLong_mem_valid_out and TestSequence_TestLongDouble_mem_valid_out;
@ -388,7 +396,6 @@ begin
finalize_payload_next <= finalize_payload; finalize_payload_next <= finalize_payload;
abort_mem <= '0'; abort_mem <= '0';
encode_done <= '0'; encode_done <= '0';
ready_in_dds <= '0';
valid_out_dds <= '0'; valid_out_dds <= '0';
last_word_out_dds <= '0'; last_word_out_dds <= '0';
data_out_dds <= (others => '0'); data_out_dds <= (others => '0');