From 399bd2bbda1418c6be5bf760ea0e32e854bfaabc Mon Sep 17 00:00:00 2001 From: Greek Date: Thu, 18 Nov 2021 12:20:20 +0100 Subject: [PATCH] Modify ports of rtps_handler according to port naming convention --- src/Tests/Level_0/L0_rtps_handler_test1.vhd | 61 ++-- src/Tests/Level_0/L0_rtps_handler_test2.vhd | 42 +-- src/Tests/Level_2/L2_Testbench_Lib2.vhd | 32 +- src/Tests/Level_2/L2_Testbench_Lib3.vhd | 32 +- src/rtps_handler.vhd | 323 ++++++++++---------- 5 files changed, 259 insertions(+), 231 deletions(-) diff --git a/src/Tests/Level_0/L0_rtps_handler_test1.vhd b/src/Tests/Level_0/L0_rtps_handler_test1.vhd index 5664ab7..0ad87f0 100644 --- a/src/Tests/Level_0/L0_rtps_handler_test1.vhd +++ b/src/Tests/Level_0/L0_rtps_handler_test1.vhd @@ -88,9 +88,9 @@ architecture testbench of L0_rtps_handler_test1 is type TEST_STAGE_TYPE is (IDLE, BUSY); -- *SIGNAL DECLARATION* - signal clk, reset, in_empty, rd_sig, builtin_full, builtin_wr, last_word_out : std_logic := '0'; - signal user_full, user_wr : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); - signal data_in, data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal clk, reset, in_empty, rd_sig, full_be, wr_be, last_word_out_be, last_word_out_ue : std_logic := '0'; + signal full_ue, wr_ue : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); + signal data_in, data_out_be, data_out_ue : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE; shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; signal packet_sent, packet_checked : std_logic := '0'; @@ -111,17 +111,23 @@ begin -- Unit Under Test uut : entity work.rtps_handler(arch) port map ( - clk => clk, - reset => reset, - empty => in_empty or packet_sent, - rd => rd_sig, - data_in => data_in, - data_out => data_out, - builtin_full => builtin_full, - builtin_wr => builtin_wr, - user_full => user_full, - user_wr => user_wr, - last_word_out => last_word_out + -- SYSTEM + clk => clk, + reset => reset, + -- INPUT + empty => in_empty or packet_sent, + rd => rd_sig, + data_in => data_in, + -- TO BUILTIN ENDPOINT + full_be => full_be, + wr_be => wr_be, + data_out_be => data_out_be, + last_word_out_be => last_word_out_be, + -- TO USER ENDPOINT + full_ue => full_ue, + wr_ue => wr_ue, + data_out_ue => data_out_ue, + last_word_out_ue => last_word_out_ue ); stimulus_prc : process @@ -1303,20 +1309,20 @@ begin fifo_ctl_prc : process begin in_empty <= '0'; - builtin_full <= '0'; - user_full <= (others => '0'); + full_be <= '0'; + full_ue <= (others => '0'); wait until rising_edge(clk); in_empty <= '1'; - builtin_full <= '0'; - user_full <= (others => '0'); + full_be <= '0'; + full_ue <= (others => '0'); wait until rising_edge(clk); in_empty <= '0'; - builtin_full <= '1'; - user_full <= (others => '0'); + full_be <= '1'; + full_ue <= (others => '0'); wait until rising_edge(clk); in_empty <= '0'; - builtin_full <= '0'; - user_full <= (others => '1'); + full_be <= '0'; + full_ue <= (others => '1'); wait until rising_edge(clk); end process; @@ -1324,8 +1330,8 @@ begin begin if rising_edge(clk) then alertif(in_empty = '1' and rd_sig = '1', "Input FIFO read signal high while empty signal high", ERROR); - alertif(builtin_full = '1' and builtin_wr = '1', "Builtin FIFO write signal high while full signal high", ERROR); - alertif(user_full /= (0 to NUM_ENDPOINTS-1 => '0') and (user_wr /= (0 to NUM_ENDPOINTS-1 => '0')), "User FIFO write signal high while full signal high", ERROR); + alertif(full_be = '1' and wr_be = '1', "Builtin FIFO write signal high while full signal high", ERROR); + alertif(full_ue /= (0 to NUM_ENDPOINTS-1 => '0') and (wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')), "User FIFO write signal high while full signal high", ERROR); end if; end process; @@ -1383,8 +1389,11 @@ begin when BUSY => if (cnt_ref = reference.length) then ref_stage <= IDLE; - elsif (builtin_wr = '1' or user_wr /= (0 to NUM_ENDPOINTS-1 => '0')) then - AffirmIfEqual(last_word_out & data_out, reference.last(cnt_ref) & reference.data(cnt_ref)); + elsif (wr_be = '1') then + AffirmIfEqual(last_word_out_be & data_out_be, reference.last(cnt_ref) & reference.data(cnt_ref)); + cnt_ref <= cnt_ref + 1; + elsif (wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')) then + AffirmIfEqual(last_word_out_ue & data_out_ue, reference.last(cnt_ref) & reference.data(cnt_ref)); cnt_ref <= cnt_ref + 1; end if; end case; diff --git a/src/Tests/Level_0/L0_rtps_handler_test2.vhd b/src/Tests/Level_0/L0_rtps_handler_test2.vhd index 0042eeb..4e5075e 100644 --- a/src/Tests/Level_0/L0_rtps_handler_test2.vhd +++ b/src/Tests/Level_0/L0_rtps_handler_test2.vhd @@ -26,9 +26,9 @@ architecture testbench of L0_rtps_handler_test2 is type TEST_STAGE_TYPE is (IDLE, BUSY); -- *SIGNAL DECLARATION* - signal clk, reset, in_empty, rd_sig, builtin_full, builtin_wr, last_word_out : std_logic := '0'; - signal user_full, user_wr : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); - signal data_in, data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal clk, reset, in_empty, rd_sig, full_be, wr_be, last_word_out_be, last_word_out_ue : std_logic := '0'; + signal full_ue, wr_ue : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); + signal data_in, data_out_be, data_out_ue : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE; shared variable stimulus, dummy : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; signal packet_sent, packet_checked : std_logic := '0'; @@ -50,17 +50,23 @@ begin -- Unit Under Test uut : entity work.rtps_handler(arch) port map ( - clk => clk, - reset => reset, - empty => in_empty or packet_sent, - rd => rd_sig, - data_in => data_in, - data_out => data_out, - builtin_full => builtin_full, - builtin_wr => builtin_wr, - user_full => user_full, - user_wr => user_wr, - last_word_out => last_word_out + -- SYSTEM + clk => clk, + reset => reset, + -- INPUT + empty => in_empty or packet_sent, + rd => rd_sig, + data_in => data_in, + -- TO BUILTIN ENDPOINT + full_be => full_be, + wr_be => wr_be, + data_out_be => data_out_be, + last_word_out_be => last_word_out_be, + -- TO USER ENDPOINT + full_ue => full_ue, + wr_ue => wr_ue, + data_out_ue => data_out_ue, + last_word_out_ue => last_word_out_ue ); stimulus_prc : process @@ -113,8 +119,8 @@ begin Log("Initiating Test", INFO); in_empty <= '0'; - builtin_full <= '0'; - user_full <= (others => '0'); + full_be <= '0'; + full_ue <= (others => '0'); start <= '0'; reset <= '1'; wait until rising_edge(clk); @@ -293,8 +299,8 @@ begin when BUSY => if (cnt_ref = dummy.length) then ref_stage <= IDLE; - elsif (builtin_wr = '1' or user_wr /= (0 to NUM_ENDPOINTS-1 => '0')) then - AffirmIfEqual((user_wr & builtin_wr), reference); + elsif (wr_be = '1' or wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')) then + AffirmIfEqual((wr_ue & wr_be), reference); cnt_ref <= cnt_ref + 1; end if; end case; diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index 93ce94f..81578bc 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -84,8 +84,8 @@ architecture arch of L2_Testbench_Lib2 is signal last_word_out_rbe : std_logic := '0'; signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal last_word_out_rh_s : std_logic := '0'; - signal data_out_rh_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0'; + signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); @@ -297,24 +297,26 @@ begin rtps_handler_w_inst : entity Testbench_Lib2.rtps_handler(arch) port map ( - clk => clk, - reset => reset, + -- SYSTEM + clk => clk, + reset => reset, -- INPUT - empty => empty, - rd => rd, - data_in => data_in, + empty => empty, + rd => rd, + data_in => data_in, -- TO RTPS BUILTIN ENDPOINT - builtin_full => full_rh(NUM_ENDPOINTS), - builtin_wr => wr_rh(NUM_ENDPOINTS), + full_be => full_rh(NUM_ENDPOINTS), + wr_be => wr_rh(NUM_ENDPOINTS), + data_out_be => data_out_rh_be_s, + last_word_out_be => last_word_out_rh_be_s, -- TO RTPS ENDPOINT - user_full => full_rh(0 to NUM_ENDPOINTS-1), - user_wr => wr_rh(0 to NUM_ENDPOINTS-1), - - last_word_out => last_word_out_rh_s, - data_out => data_out_rh_s + full_ue => full_rh(0 to NUM_ENDPOINTS-1), + wr_ue => wr_rh(0 to NUM_ENDPOINTS-1), + data_out_ue => data_out_rh_ue_s, + last_word_out_ue => last_word_out_rh_ue_s ); - data_in_rh <= (others => (last_word_out_rh_s & data_out_rh_s)); + data_in_rh <= (NUM_ENDPOINTS => (last_word_out_rh_be_s & data_out_rh_be_s), others => (last_word_out_rh_ue_s & data_out_rh_ue_s)); rtps_out_w_inst : entity Testbench_Lib2.rtps_out(arch) port map ( diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index affb48c..6cbff3e 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -108,8 +108,8 @@ architecture arch of L2_Testbench_Lib3 is signal last_word_out_rbe : std_logic := '0'; signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal last_word_out_rh_s : std_logic := '0'; - signal data_out_rh_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0'; + signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); @@ -350,24 +350,26 @@ begin rtps_handler_r_inst : entity Testbench_Lib3.rtps_handler(arch) port map ( - clk => clk, - reset => reset, + -- SYSTEM + clk => clk, + reset => reset, -- INPUT - empty => empty, - rd => rd, - data_in => data_in, + empty => empty, + rd => rd, + data_in => data_in, -- TO RTPS BUILTIN ENDPOINT - builtin_full => full_rh(NUM_ENDPOINTS), - builtin_wr => wr_rh(NUM_ENDPOINTS), + full_be => full_rh(NUM_ENDPOINTS), + wr_be => wr_rh(NUM_ENDPOINTS), + data_out_be => data_out_rh_be_s, + last_word_out_be => last_word_out_rh_be_s, -- TO RTPS ENDPOINT - user_full => full_rh(0 to NUM_ENDPOINTS-1), - user_wr => wr_rh(0 to NUM_ENDPOINTS-1), - - last_word_out => last_word_out_rh_s, - data_out => data_out_rh_s + full_ue => full_rh(0 to NUM_ENDPOINTS-1), + wr_ue => wr_rh(0 to NUM_ENDPOINTS-1), + data_out_ue => data_out_rh_ue_s, + last_word_out_ue => last_word_out_rh_ue_s ); - data_in_rh <= (others => (last_word_out_rh_s & data_out_rh_s)); + data_in_rh <= (NUM_ENDPOINTS => (last_word_out_rh_be_s & data_out_rh_be_s), others => (last_word_out_rh_ue_s & data_out_rh_ue_s)); rtps_out_r_inst : entity Testbench_Lib3.rtps_out(arch) port map ( diff --git a/src/rtps_handler.vhd b/src/rtps_handler.vhd index e7c0a5e..047c1f7 100644 --- a/src/rtps_handler.vhd +++ b/src/rtps_handler.vhd @@ -9,26 +9,28 @@ use work.rtps_config_package.all; entity rtps_handler is port ( - clk : in std_logic; -- Input Clock - reset : in std_logic; -- Synchronous Reset - empty : in std_logic; -- Input FIFO empty flag - rd : out std_logic; -- Input FIFO read signal - data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); -- Input FIFO data signal - data_out : out std_logic_vector(WORD_WIDTH-1 downto 0); -- Output data signal - builtin_full : in std_logic; -- Output FIFO (Built-In Endpoint) full signal - builtin_wr : out std_logic; -- Output FIFO (Built-In Endpoint) write signal - user_full : in std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) full signal - user_wr : out std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) write signal - last_word_out : out std_logic -- Output FIFO Last Word signal + -- SYSTEM + clk : in std_logic; + reset : in std_logic; + -- INPUT + empty : in std_logic; + rd : out std_logic; + data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); + -- TO BUILTIN ENDPOINT + full_be : in std_logic; + wr_be : out std_logic; + data_out_be : out std_logic_vector(WORD_WIDTH-1 downto 0); + last_word_out_be : out std_logic; + -- TO USER ENDPOINTS + data_out_ue : out std_logic_vector(WORD_WIDTH-1 downto 0); -- one-to-many (Multicast) Connection + full_ue : in std_logic_vector(0 to NUM_ENDPOINTS-1); + wr_ue : out std_logic_vector(0 to NUM_ENDPOINTS-1); + last_word_out_ue : out std_logic -- one-to-many (Multicast) Connection ); end entity; architecture arch of rtps_handler is - --*****COMPONENT DECLARATION****** - - --*****CONSTANT DECLARATION***** - --*****TYPE DECLARATION***** -- FSM states. Explained below in detail type STAGE_TYPE is (SRC_ADDR_HEADER, DEST_ADDR_HEADER, UDP_PORT_HEADER, LEN_HEADER, RTPS_HEADER_1, RTPS_HEADER_2, @@ -82,7 +84,7 @@ architecture arch of rtps_handler is -- Source GUID Prefix latch signal src_guidprefix, src_guidprefix_next : GUIDPREFIX_TYPE := (others => (others => '0')); -- Vector denoting the Destination User Endpoints of the Submessage - signal user_endpoint, user_endpoint_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); + signal user_endpoints, user_endpoints_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); -- Denotes if the Message is destined for the Built-in Endpoints signal builtin_endpoint, builtin_endpoint_next : std_logic := '0'; -- LocatorList NumLocator latch @@ -122,6 +124,10 @@ architecture arch of rtps_handler is signal ip_addr_type, ip_addr_type_next : IPv4_ADDRESS_TYPE := INVALID; -- Alias "substitution" signal rtps_sub_length, rtps_sub_data_length : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0'); + -- Internal Signal for data_out + signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + -- Internal Signal for last_word_out + signal last_word_out_sig : std_logic := '0'; --*****ALIAS DEFINATION***** -- UDP HEADER @@ -139,8 +145,6 @@ architecture arch of rtps_handler is -- Apparently illegal alias expression --alias rtps_sub_data_length : unsigned(15 downto 0) is unsigned(endian_swap(flags(SUBMESSAGE_ENDIAN_FLAG_POS), data_in(15 downto 0))); - --*****FUNCTION DECLARATION***** - begin -- ALIAS SUBSTITUTION @@ -156,17 +160,22 @@ begin output_prc : process(all) begin --Write Enable Signal - builtin_wr <= '0'; - user_wr <= (others => '0'); + wr_be <= '0'; + wr_ue <= (others => '0'); if (wr_sig = '1') then if (builtin_endpoint = '1') then - builtin_wr <= '1'; + wr_be <= '1'; else - user_wr <= user_endpoint; + wr_ue <= user_endpoints; end if; end if; end process; + data_out_be <= data_out_sig; + data_out_ue <= data_out_sig; + last_word_out_be <= last_word_out_sig; + last_word_out_ue <= last_word_out_sig; + -- This process is responsible for reading the input FIFO 4-Byte Word aligned. -- Even though DDSI-RTPS 2.3 defines that Submessages begin at 4-byte boundries, meaning that the -- submessage length is always a multiple of 4, the same is not defined for the "octetstoinlineQoS". @@ -223,44 +232,44 @@ begin variable rd_guard : std_logic := '0'; begin --DEFAULT Registered - stage_next <= stage; - cnt_next <= cnt; - align_offset_next <= align_offset; - align_sig_next <= align_sig; - packet_length_next <= packet_length; - sub_end_next <= sub_end; - offset_latch_next <= offset_latch; - src_addr_next <= src_addr; - src_port_next <= src_port; - flags_next <= flags; - src_entityid_next <= src_entityid; - src_guidprefix_next <= src_guidprefix; - dest_entityid_next <= dest_entityid; - user_endpoint_next <= user_endpoint; - builtin_endpoint_next <= builtin_endpoint; - numlocators_next <= numlocators; - opcode_next <= opcode; - data_header_end_next <= data_header_end; - locator_match_next <= locator_match; - is_metatraffic_next <= is_metatraffic; - src_is_reader_next <= src_is_reader; - sn_latch_1_next <= sn_latch_1; - sn_latch_2_next <= sn_latch_2; - sn_latch_3_next <= sn_latch_3; - long_latch_next <= long_latch; - ulong_latch_next <= ulong_latch; - bitmap_latch_next <= bitmap_latch; - cnt2_next <= cnt2; - bitmap_cnt_next <= bitmap_cnt; - src_ts_next <= src_ts; - ip_addr_type_next <= ip_addr_type; + stage_next <= stage; + cnt_next <= cnt; + align_offset_next <= align_offset; + align_sig_next <= align_sig; + packet_length_next <= packet_length; + sub_end_next <= sub_end; + offset_latch_next <= offset_latch; + src_addr_next <= src_addr; + src_port_next <= src_port; + flags_next <= flags; + src_entityid_next <= src_entityid; + src_guidprefix_next <= src_guidprefix; + dest_entityid_next <= dest_entityid; + user_endpoints_next <= user_endpoints; + builtin_endpoint_next <= builtin_endpoint; + numlocators_next <= numlocators; + opcode_next <= opcode; + data_header_end_next <= data_header_end; + locator_match_next <= locator_match; + is_metatraffic_next <= is_metatraffic; + src_is_reader_next <= src_is_reader; + sn_latch_1_next <= sn_latch_1; + sn_latch_2_next <= sn_latch_2; + sn_latch_3_next <= sn_latch_3; + long_latch_next <= long_latch; + ulong_latch_next <= ulong_latch; + bitmap_latch_next <= bitmap_latch; + cnt2_next <= cnt2; + bitmap_cnt_next <= bitmap_cnt; + src_ts_next <= src_ts; + ip_addr_type_next <= ip_addr_type; -- DEFAULT Unregistered - data_out <= (others => '0'); - rd_sig <= '0'; - rd_guard := '0'; - reset_read_cnt <= '0'; - wr_sig <= '0'; - last_word_out <= '0'; + data_out_sig <= (others => '0'); + rd_sig <= '0'; + rd_guard := '0'; + reset_read_cnt <= '0'; + wr_sig <= '0'; + last_word_out_sig <= '0'; case(stage) is -- Initial/Idle State @@ -968,7 +977,7 @@ begin end if; when MATCH_DST_ENDPOINT => -- DEFAULT - user_endpoint_next <= (others => '0'); + user_endpoints_next <= (others => '0'); builtin_endpoint_next <= '0'; stage_next <= PUSH_PAYLOAD_HEADER; cnt_next <= 0; @@ -981,10 +990,10 @@ begin else -- Mark Only Writers if (src_is_reader = '1' and NUM_WRITERS /= 0) then - user_endpoint_next <= not ENDPOINT_READERS; + user_endpoints_next <= not ENDPOINT_READERS; -- Mark Only Readers elsif (NUM_READERS /= 0) then - user_endpoint_next <= ENDPOINT_READERS; + user_endpoints_next <= ENDPOINT_READERS; end if; end if; -- Target Built-In Endpoints @@ -1009,10 +1018,10 @@ begin -- SANITY CHECK: Allow only Reader-Writer Communication if (src_is_reader = '1') then -- Mark only Writers - user_endpoint_next <= tmp and (not ENDPOINT_READERS); + user_endpoints_next <= tmp and (not ENDPOINT_READERS); else -- Mark only Readers - user_endpoint_next <= tmp and ENDPOINT_READERS; + user_endpoints_next <= tmp and ENDPOINT_READERS; end if; end if; -- Destination Unreachable, skip Submessage @@ -1022,72 +1031,72 @@ begin when PUSH_PAYLOAD_HEADER => -- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs. -- Output FIFO Guard - if (builtin_endpoint = '1' and builtin_full = '0') or (builtin_endpoint = '0' and ((user_endpoint and user_full) = (user_endpoint'range => '0'))) then + if (builtin_endpoint = '1' and full_be = '0') or (builtin_endpoint = '0' and ((user_endpoints and full_ue) = (user_endpoints'range => '0'))) then case (cnt) is -- OPCODE (Submessage ID), Submessage Flags, UPDv4 Source Port when 0 => - data_out <= opcode & flags & src_port; - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= opcode & flags & src_port; + wr_sig <= '1'; + cnt_next <= cnt + 1; -- IPv4 Source Address when 1 => - data_out <= src_addr; - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= src_addr; + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GUID Prefix 1/3 when 2 => - data_out <= src_guidprefix(0); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= src_guidprefix(0); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GUID Prefix 2/3 when 3 => - data_out <= src_guidprefix(1); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= src_guidprefix(1); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GUID Prefix 3/3 when 4 => - data_out <= src_guidprefix(2); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= src_guidprefix(2); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- Source Entity ID when 5 => - data_out <= src_entityid; - wr_sig <= '1'; + data_out_sig <= src_entityid; + wr_sig <= '1'; cnt_next <= cnt + 1; -- Destination ID [only for Built-in Endpoints] when 6 => if (builtin_endpoint = '1') then - data_out <= dest_entityid; - wr_sig <= '1'; + data_out_sig <= dest_entityid; + wr_sig <= '1'; end if; cnt_next <= cnt + 1; -- Sequence Number 1/2 [only for DATA Submessages] when 7 => if (opcode = SID_DATA) then - data_out <= std_logic_vector(sn_latch_1(0)); - wr_sig <= '1'; + data_out_sig <= std_logic_vector(sn_latch_1(0)); + wr_sig <= '1'; end if; cnt_next <= cnt + 1; -- Sequence Number 2/2 [only for DATA Submessages] when 8 => if (opcode = SID_DATA) then - data_out <= std_logic_vector(sn_latch_1(1)); - wr_sig <= '1'; + data_out_sig <= std_logic_vector(sn_latch_1(1)); + wr_sig <= '1'; end if; cnt_next <= cnt + 1; -- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints] when 9 => if (opcode = SID_DATA and builtin_endpoint = '0') then - data_out <= std_logic_vector(src_ts(0)); - wr_sig <= '1'; + data_out_sig <= std_logic_vector(src_ts(0)); + wr_sig <= '1'; end if; cnt_next <= cnt + 1; -- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints] when 10 => if (opcode = SID_DATA and builtin_endpoint = '0') then - data_out <= std_logic_vector(src_ts(1)); - wr_sig <= '1'; + data_out_sig <= std_logic_vector(src_ts(1)); + wr_sig <= '1'; end if; stage_next <= PUSH_PAYLOAD; @@ -1099,36 +1108,36 @@ begin when PUSH_PAYLOAD => -- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs. -- Output FIFO Guard - if (builtin_endpoint = '1' and builtin_full = '0') or (builtin_endpoint = '0' and ((user_endpoint and user_full) = (user_endpoint'range => '0'))) then + if (builtin_endpoint = '1' and full_be = '0') or (builtin_endpoint = '0' and ((user_endpoints and full_ue) = (user_endpoints'range => '0'))) then case (opcode) is when SID_HEARTBEAT => case (cnt) is -- FirstSN 1/2 when 0 => - data_out <= std_logic_vector(sn_latch_1(0)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(0)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- FirstSN 2/2 when 1 => - data_out <= std_logic_vector(sn_latch_1(1)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(1)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- LastSN 1/2 when 2 => - data_out <= std_logic_vector(sn_latch_2(0)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_2(0)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- LastSN 2/2 when 3 => - data_out <= std_logic_vector(sn_latch_2(1)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_2(1)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- Count when 4 => - data_out <= long_latch; - wr_sig <= '1'; - last_word_out <= '1'; + data_out_sig <= long_latch; + wr_sig <= '1'; + last_word_out_sig <= '1'; -- DONE stage_next <= SKIP_SUB; @@ -1139,36 +1148,36 @@ begin case (cnt) is -- ReaderSNState.Base 1/2 when 0 => - data_out <= std_logic_vector(sn_latch_1(0)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(0)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- ReaderSNState.Base 2/2 when 1 => - data_out <= std_logic_vector(sn_latch_1(1)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(1)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- ReaderSNState.NumBits when 2 => - data_out <= std_logic_vector(ulong_latch); - wr_sig <= '1'; - cnt2_next <= 0; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(ulong_latch); + wr_sig <= '1'; + cnt2_next <= 0; + cnt_next <= cnt + 1; -- ReaderSNState.Bitmap when 3 => -- Write Bitmap if (cnt2 < bitmap_cnt) then cnt2_next <= cnt2 + 1; - data_out <= bitmap_latch_next(cnt2); - wr_sig <= '1'; + data_out_sig <= bitmap_latch_next(cnt2); + wr_sig <= '1'; else - cnt_next <= cnt + 1; + cnt_next <= cnt + 1; end if; -- Count when 4 => - data_out <= long_latch; - wr_sig <= '1'; - last_word_out <= '1'; + data_out_sig <= long_latch; + wr_sig <= '1'; + last_word_out_sig <= '1'; -- DONE stage_next <= SKIP_SUB; @@ -1179,49 +1188,49 @@ begin case (cnt) is -- GapStart 1/2 when 0 => - data_out <= std_logic_vector(sn_latch_1(0)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(0)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GapStart 2/2 when 1 => - data_out <= std_logic_vector(sn_latch_1(1)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_1(1)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GapList.Base 1/2 when 2 => - data_out <= std_logic_vector(sn_latch_2(0)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_2(0)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GapList.Base 2/2 when 3 => - data_out <= std_logic_vector(sn_latch_2(1)); - wr_sig <= '1'; - cnt_next <= cnt + 1; + data_out_sig <= std_logic_vector(sn_latch_2(1)); + wr_sig <= '1'; + cnt_next <= cnt + 1; -- GapList.NumBits when 4 => - data_out <= std_logic_vector(ulong_latch); - wr_sig <= '1'; - cnt_next <= cnt + 1; - cnt2_next <= 0; + data_out_sig <= std_logic_vector(ulong_latch); + wr_sig <= '1'; + cnt_next <= cnt + 1; + cnt2_next <= 0; -- GapList.Bitmap when 5 => -- Write Bitmap if (cnt2 < bitmap_cnt) then cnt2_next <= cnt2 + 1; - data_out <= bitmap_latch_next(cnt2); - wr_sig <= '1'; + data_out_sig <= bitmap_latch_next(cnt2); + wr_sig <= '1'; else - cnt_next <= cnt + 1; + cnt_next <= cnt + 1; end if; - -- NOTE: Because we need to pull "last_word_out" high on the last Byte, and doing so in the last Byte of Bitmap was deemed + -- NOTE: Because we need to pull "last_word_out_sig" high on the last Byte, and doing so in the last Byte of Bitmap was deemed -- to much overhead (We need a counter in addition to cnt2 to track the next-to-last Byte of the Bitmap), we just -- define the Frame with an additional dummy word in the end. -- UNUSED when 6 => - data_out <= (others => '0'); - wr_sig <= '1'; - last_word_out <= '1'; + data_out_sig <= (others => '0'); + wr_sig <= '1'; + last_word_out_sig <= '1'; -- DONE stage_next <= SKIP_SUB; @@ -1245,11 +1254,11 @@ begin align_sig_next <= data_in(23 downto 0); -- Push Payload - data_out <= data_in_aligned; + data_out_sig <= data_in_aligned; wr_sig <= '1'; if (read_cnt_plus = sub_end) then - last_word_out <= '1'; + last_word_out_sig <= '1'; -- Begin parsing of next submessage stage_next <= RTPS_SUB_HEADER; -- Reset alignement @@ -1310,7 +1319,7 @@ begin -- Force rd_sig low rd_sig <= '0'; -- Notify Endpoints of EOP - last_word_out <= '1'; + last_word_out_sig <= '1'; -- Continue parsing next Packet stage_next <= SRC_ADDR_HEADER; -- Reset Lengths @@ -1322,16 +1331,16 @@ begin -- The SKIP_SUB clause prevents a read signal from occuring in this situation, and thus prevents from entering this state. elsif (read_cnt = sub_end and rd_guard = '1') then -- Force rd_sig low - rd_sig <= '0'; + rd_sig <= '0'; -- Notify Endpoints of EOS - last_word_out <= '1'; + last_word_out_sig <= '1'; -- Invalid Submessage Length Field, Skip Packet (see DDSI-RTPS 2.3 Section 8.3.4.1) - stage_next <= SKIP_PACKET; + stage_next <= SKIP_PACKET; -- Reset Submessage End - sub_end_next <= (others => '1'); + sub_end_next <= (others => '1'); -- DEFAULT else - rd_sig <= rd_guard; + rd_sig <= rd_guard; end if; end process; @@ -1368,7 +1377,7 @@ begin flags <= (others => '0'); src_entityid <= (others => '0'); dest_entityid <= (others => '0'); - user_endpoint <= (others => '0'); + user_endpoints <= (others => '0'); numlocators <= (others => '0'); opcode <= (others => '0'); data_header_end <= (others => '0'); @@ -1400,7 +1409,7 @@ begin flags <= flags_next; src_entityid <= src_entityid_next; dest_entityid <= dest_entityid_next; - user_endpoint <= user_endpoint_next; + user_endpoints <= user_endpoints_next; numlocators <= numlocators_next; opcode <= opcode_next; data_header_end <= data_header_end_next;