Rename *_wrapper to *_interface

Since the Type Specific user facing entities did not actually wrap the
DDS entities, but connected to them through port signals, a more
semantically correct name would be "interface", since they are the user
facing interface of the DDS entities.

sim/L1_Type2_interface.do

@@ -0,0 +1,55 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider SYSTEM
+add wave -noupdate /l1_type2_interface_test1/clk
+add wave -noupdate /l1_type2_interface_test1/reset
+add wave -noupdate -divider WRITER_interface
+add wave -noupdate /l1_type2_interface_test1/uut_w/start_user
+add wave -noupdate /l1_type2_interface_test1/uut_w/opcode_user
+add wave -noupdate /l1_type2_interface_test1/uut_w/ack_dds
+add wave -noupdate /l1_type2_interface_test1/uut_w/stage
+add wave -noupdate /l1_type2_interface_test1/uut_w/stage_next
+add wave -noupdate /l1_type2_interface_test1/uut_w/encode_stage
+add wave -noupdate /l1_type2_interface_test1/uut_w/encode_stage_next
+add wave -noupdate /l1_type2_interface_test1/uut_w/cnt
+add wave -noupdate -radix hexadecimal /l1_type2_interface_test1/uut_w/data_out_latch
+add wave -noupdate /l1_type2_interface_test1/uut_w/align_offset
+add wave -noupdate /l1_type2_interface_test1/uut_w/encode_done
+add wave -noupdate -divider INTERCONNECT
+add wave -noupdate /l1_type2_interface_test1/ready
+add wave -noupdate /l1_type2_interface_test1/valid
+add wave -noupdate -radix hexadecimal /l1_type2_interface_test1/data
+add wave -noupdate /l1_type2_interface_test1/last_word
+add wave -noupdate -divider READER_interface
+add wave -noupdate /l1_type2_interface_test1/uut_r/si_valid_data_dds
+add wave -noupdate /l1_type2_interface_test1/uut_r/si_valid_dds
+add wave -noupdate /l1_type2_interface_test1/uut_r/si_ack_user
+add wave -noupdate /l1_type2_interface_test1/uut_r/get_data_user
+add wave -noupdate /l1_type2_interface_test1/uut_r/stage
+add wave -noupdate /l1_type2_interface_test1/uut_r/stage_next
+add wave -noupdate /l1_type2_interface_test1/uut_r/decode_stage
+add wave -noupdate /l1_type2_interface_test1/uut_r/decode_stage_next
+add wave -noupdate /l1_type2_interface_test1/uut_r/cnt
+add wave -noupdate /l1_type2_interface_test1/uut_r/align_offset
+add wave -noupdate /l1_type2_interface_test1/uut_r/optional
+add wave -noupdate /l1_type2_interface_test1/uut_r/decode_error
+add wave -noupdate /l1_type2_interface_test1/uut_r/valid
+add wave -noupdate -divider MISC
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {5853656 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {5683200 ps} {6707200 ps}

sim/L1_Type2_wrapper.do

@@ -1,55 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider SYSTEM
-add wave -noupdate /l1_type2_wrapper_test1/clk
-add wave -noupdate /l1_type2_wrapper_test1/reset
-add wave -noupdate -divider WRITER_WRAPPER
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/start_user
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/opcode_user
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/ack_dds
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/stage
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/stage_next
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_stage
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_stage_next
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/cnt
-add wave -noupdate -radix hexadecimal /l1_type2_wrapper_test1/uut_w/data_out_latch
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/align_offset
-add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_done
-add wave -noupdate -divider INTERCONNECT
-add wave -noupdate /l1_type2_wrapper_test1/ready
-add wave -noupdate /l1_type2_wrapper_test1/valid
-add wave -noupdate -radix hexadecimal /l1_type2_wrapper_test1/data
-add wave -noupdate /l1_type2_wrapper_test1/last_word
-add wave -noupdate -divider READER_WRAPPER
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_valid_data_dds
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_valid_dds
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_ack_user
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/get_data_user
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/stage
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/stage_next
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_stage
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_stage_next
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/cnt
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/align_offset
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/optional
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_error
-add wave -noupdate /l1_type2_wrapper_test1/uut_r/valid
-add wave -noupdate -divider MISC
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {5853656 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {5683200 ps} {6707200 ps}

src/IDL-VHDL_Ref.txt

@@ -1,5 +1,5 @@
-READER_WRAPPER
+READER_INTERFACE
-##############
+################
 
 
 GENERAL
@@ -194,13 +194,13 @@ the <TYPENAME>_opt_latch is set to '1'.
 
 
 
-WRITER_WRAPPER
+WRITER_INTERFACE
-##############
+################
 
 GENERAL
 =======
 
-In General the writer_wrapper is a similar layout to the reader_wrapper with following modifications.
+In General the writer_interface is a similar layout to the reader_interface with following modifications.
 
 All "GET_*" stages are renamed to "WRITE_*". 
 The "FETCH" stage is renamed to "PUSH".
@@ -251,7 +251,7 @@ KEY_HOLDER
 GENERAL
 =======
 
-Generally the key_holder is a combination of both the reader_wrapper and writer_wrapper.
+Generally the key_holder is a combination of both the reader_interface and writer_interface.
 
 The port signals are predefined and fixed (no port signal generation).
 
@@ -260,21 +260,21 @@ The 'ALIGN_STREAM' stage is split into 'ALIGN_IN_STREAM' (for decode_stage) and
 (for encode_stage).
 
 The decode procedure (decode_stage stages) follows 2 different decoding procedures.
-The first - taken on a 'PUSH_DATA' opcode - follows the reader_wrapper procedure of the <TOPIC> type until 
+The first - taken on a 'PUSH_DATA' opcode - follows the reader_interface procedure of the <TOPIC> type until 
 the last declared member that is also member of the KeyHolder(<TYPENAME>)[6] Type (i.e. the last decalred 
 key of the type), after which the 'SKIP_PAYLOAD' stage is taken. 
 (Since the serialized key only uses the KeyHolder(<TYPENAME>) members, the rest is ignored)
-The second - taken on a 'PUSH_SERIALIZED_KEY' opcode - follows the reader_wrapper procedure of the 
+The second - taken on a 'PUSH_SERIALIZED_KEY' opcode - follows the reader_interface procedure of the 
 KeyHolder(<TYPENAME>) directly.
 Since the decode_stages for the second decoding procedure are a subset of the first decoding procedure,
 the same decode stages are used, and only the 'decode_stage_next' signal is set depending on the 
 'opcode_latch' signal. The 'GET_PAYLAOD_HEADER' stage selects the correct first decode stage.
 
 Similarly the encode procedure also follows 2 different encoding procedures.
-The first - taken on a 'READ_SERIALIZED_KEY' opcode - follows the write_wrapper procedure of the 
+The first - taken on a 'READ_SERIALIZED_KEY' opcode - follows the write_interface procedure of the 
 KeyHolder(<TYPENAME>) Type.
 The second - taken on a 'READ_KEY_HASH' opcode (if the key is not already calculated) - follows the
-write_wrapper procedure of the <TYPENAME>KeyHolder[7] Type. Note that this encoding is in PLAIN_CDR2 
+write_interface procedure of the <TYPENAME>KeyHolder[7] Type. Note that this encoding is in PLAIN_CDR2 
 Big Endian, meaning that types wich have an ALIGN_8 in PLAIN_CDR have a ALIGN_4 in PLAIN_CDR2.
 Both encoding procedures share the same encode_stages, and the 'encode_stage_next' signal is
 set depending on the 'opcode_latch' signal. On a 'READ_SERIALIZED_KEY' opcode the 

src/TEMPLATE_dds_top.vhd

@@ -112,7 +112,7 @@ architecture arch of dds_top is
     signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
     signal data_firo_ro : RTPS_OUT_DATA_TYPE;
     -- ###GENERATED START###
-        -- WRAPPER-USER SIGNALS
+        -- INTERFACE-USER SIGNALS
     -- ###GENERATED END###
     
 begin
@@ -552,7 +552,7 @@ begin
     -- ######GENERATED START######
     
     TYPENAME_reader_interface_if : if (NUM_READERS > 0) generate
-        TYPENAME_reader_wrapper_inst : entity work.TYPENAME_reader_wrapper(arch)
+        TYPENAME_reader_interface_inst : entity work.TYPENAME_reader_interface(arch)
             port map (
                 -- SYSTEM
                 clk                                 => clk,
@@ -629,7 +629,7 @@ begin
     end generate;
     
     TYPENAME_writer_interface_if : if (NUM_WRITERS > 0) generate
-        TYPENAME_writer_wrapper_inst : entity work.TYPENAME_writer_wrapper(arch)
+        TYPENAME_writer_interface_inst : entity work.TYPENAME_writer_interface(arch)
             port map (
                 -- SYSTEM
                 clk                         => clk,

src/TEMPLATE_reader_interface.vhd

@@ -8,7 +8,7 @@ use ieee.numeric_std.all;
 use work.rtps_package.all;
 use work.rtps_config_package.all;
 
-entity TYPENAME_reader_wrapper is
+entity TYPENAME_reader_interface is
     port (
         -- SYSTEM
         clk                                 : in std_logic;
@@ -87,7 +87,7 @@ entity TYPENAME_reader_wrapper is
     );
 end entity;
 
-architecture arch of TYPENAME_reader_wrapper is
+architecture arch of TYPENAME_reader_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/TEMPLATE_writer_interface.vhd

@@ -8,7 +8,7 @@ use ieee.numeric_std.all;
 use work.rtps_package.all;
 use work.rtps_config_package.all;
 
-entity TYPENAME_writer_wrapper is
+entity TYPENAME_writer_interface is
     generic (
         LITTLE_ENDIAN   : std_logic := '0'
     );
@@ -58,7 +58,7 @@ entity TYPENAME_writer_wrapper is
     );
 end entity;
 
-architecture arch of TYPENAME_writer_wrapper is
+architecture arch of TYPENAME_writer_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/TODO.txt

@@ -93,6 +93,8 @@
     - Under close inspection the IDL 4.2 specification states under 7.4.1.4.4.3.2
         "IDL defines the string type string consisting of a list of all possible 8-bit quantities except null."
       Which means that the bound of a bounded string does not count the NUL byte.
+* Currently we use one rtps_builtin_endpoint per participant. Meaning that if we want to compile 2 seperate participants we have to actually compile 2 different systems (e.g. in seperate Libraries for testing).
+  It would make sense to remove this restriction, rename the rtps_builtin_endpoint to something more generic like "discovery_module", and allow a way to set participant boundaries.
 
 * Fast-RTPS does not follow DDSI-RTPS Specification
     - Open Github Issue
@@ -315,20 +317,21 @@ DESIGN DECISIONS
 
 *   Since all code related to encoding/decoding the DATA stream is dependent on the IDL type 
     specification, we have to encapsule that code separately and link them as necessary. Two such
-    dynamic Entities are defined: KEY_HOLDER, and <TYPENAME>_WRAPPER.
+    dynamic Entities are defined: KEY_HOLDER, and <TYPENAME>_INTERFACE.
     The KEY_HOLDER Entity contains a Byte-Wide internal memory (In size equal to the maximum key size),
     that can be filled with PLAIN_CDR/PL_CDR DATA Streams, and Serialized Key Streams. 
     The Entity allows outputting the memory contents (Key) either in a KEY_HASH format (needs
     to instantiate a MD5 calculator), or in Serialized Key Format. The Entity uses the start/opcode/ack
     interface for operations (similar to the RTPS/DDS Interface).
-    The <TYPENAME>_WRAPPER entity has all type-components linked to ports and latched in registers/memory. 
+    The <TYPENAME>_INTERFACE entity has all type-components linked to ports and latched in registers/memory. 
     In output mode the entity is able to fill the registers/memory with a PLAIN_CDR/PL_CDR Data Stream, and 
     in input mode the registers are filled directly from the input ports and the Entity is able to produce
     a PLAIN_CDR/PL_CDR Data Stream from the registers/memory.
     Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints, 
-    but will be instantiated in a wrapper and linked through port mapping with the DDS Endpoints.
+    but will be instantiated in a seperate entity (Interface) and linked through port mapping with the 
-    X: Due to port mapping differences between DDS Reader and Writer the <TYPENAME>_WRAPPER is splitt into 
+    DDS Endpoints.
-    <TYPENAME>_READER_WRAPPER and <TYPENAME>_WRITER_WRAPPER.
+    X: Due to port mapping differences between DDS Reader and Writer the <TYPENAME>_INTERFACE is splitt into 
+    <TYPENAME>_READER_INTERFACE and <TYPENAME>_WRITER_INTERFACE.
     
 *   Due to the requirements of read_next_instance/take_next_instance of the DDS Reader, the Instances are
     inserted in numerical Key Hash order into the Instance Memory. This extra sorting logic is not needed

src/Tests/Level_1/L1_Type1_interface_test1.vhd

@@ -11,14 +11,14 @@ use work.rtps_config_package.all;
 use work.rtps_test_package.all;
 use work.Type2_package.all;
 
--- This testbench tests the Payload encoding/decoding of the TYPE1_wrapper entities.
+-- This testbench tests the Payload encoding/decoding of the TYPE1_interface entities.
--- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
+-- It does so by interconnecting the writer and reader interface, setting some inputs to the writer and checking if the reader returns the same data.
 -- This testbench tests only the Big Endian encoding/decoding.
 
-entity L1_Type1_wrapper_test1 is
+entity L1_Type1_interface_test1 is
 end entity;
 
-architecture testbench of L1_Type1_wrapper_test1 is
+architecture testbench of L1_Type1_interface_test1 is
     
     signal clk, reset : std_logic := '0';
     signal ready, valid, last_word : std_logic := '0';
@@ -29,7 +29,7 @@ architecture testbench of L1_Type1_wrapper_test1 is
     signal a_in, a_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    uut_w : entity work.Type1_writer_wrapper(arch)
+    uut_w : entity work.Type1_writer_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -66,7 +66,7 @@ begin
             encode_done                         => encode_done
         );
     
-    uut_r : entity work.Type1_reader_wrapper(arch)
+    uut_r : entity work.Type1_reader_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -146,7 +146,7 @@ begin
         end procedure;
     begin
         
-        SetAlertLogName("Type1_wrapper - Level 1 - (Big Endian) - Encoding/Decoding");
+        SetAlertLogName("Type1_interface - Level 1 - (Big Endian) - Encoding/Decoding");
         SetAlertEnable(FAILURE, TRUE);
         SetAlertEnable(ERROR, TRUE);
         SetAlertEnable(WARNING, TRUE);

src/Tests/Level_1/L1_Type1_interface_test2.vhd

@@ -11,14 +11,14 @@ use work.rtps_config_package.all;
 use work.rtps_test_package.all;
 use work.Type2_package.all;
 
--- This testbench tests the Payload encoding/decoding of the TYPE1_wrapper entities.
+-- This testbench tests the Payload encoding/decoding of the TYPE1_interface entities.
--- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
+-- It does so by interconnecting the writer and reader interface, setting some inputs to the writer and checking if the reader returns the same data.
 -- This testbench tests only the Little Endian encoding/decoding.
 
-entity L1_Type1_wrapper_test2 is
+entity L1_Type1_interface_test2 is
 end entity;
 
-architecture testbench of L1_Type1_wrapper_test2 is
+architecture testbench of L1_Type1_interface_test2 is
     
     signal clk, reset : std_logic := '0';
     signal ready, valid, last_word : std_logic := '0';
@@ -29,7 +29,7 @@ architecture testbench of L1_Type1_wrapper_test2 is
     signal a_in, a_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    uut_w : entity work.Type1_writer_wrapper(arch)
+    uut_w : entity work.Type1_writer_interface(arch)
         generic map (
             LITTLE_ENDIAN   => '1'
         )
@@ -69,7 +69,7 @@ begin
             encode_done                         => encode_done
         );
     
-    uut_r : entity work.Type1_reader_wrapper(arch)
+    uut_r : entity work.Type1_reader_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -149,7 +149,7 @@ begin
         end procedure;
     begin
         
-        SetAlertLogName("Type1_wrapper - Level 1 - (Little Endian) - Encoding/Decoding");
+        SetAlertLogName("Type1_interface - Level 1 - (Little Endian) - Encoding/Decoding");
         SetAlertEnable(FAILURE, TRUE);
         SetAlertEnable(ERROR, TRUE);
         SetAlertEnable(WARNING, TRUE);

src/Tests/Level_1/L1_Type1_key_holder_test1.vhd

@@ -12,7 +12,7 @@ use work.rtps_test_package.all;
 use work.Type2_package.all;
 
 -- This testbench tests the KEY_HOLDER commands of TYPE1.
--- It uses the writer_wrapper to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
+-- It uses the writer_interface to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
 -- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
 -- The payload is sent in Big Endian.
 
@@ -34,7 +34,7 @@ architecture testbench of L1_Type1_key_holder_test1 is
     signal a_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    Type1_writer_wrapper_inst : entity work.Type1_writer_wrapper(arch)
+    Type1_writer_interface_inst : entity work.Type1_writer_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,

src/Tests/Level_1/L1_Type1_key_holder_test2.vhd

@@ -12,7 +12,7 @@ use work.rtps_test_package.all;
 use work.Type2_package.all;
 
 -- This testbench tests the KEY_HOLDER commands of TYPE1.
--- It uses the writer_wrapper to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
+-- It uses the writer_interface to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
 -- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
 -- The payload is sent in Little Endian.
 
@@ -34,7 +34,7 @@ architecture testbench of L1_Type1_key_holder_test2 is
     signal a_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    Type1_writer_wrapper_inst : entity work.Type1_writer_wrapper(arch)
+    Type1_writer_interface_inst : entity work.Type1_writer_interface(arch)
         generic map (
             LITTLE_ENDIAN   => '1'
         )

src/Tests/Level_1/L1_Type2_interface_test1.vhd

@@ -11,14 +11,14 @@ use work.rtps_config_package.all;
 use work.rtps_test_package.all;
 use work.Type2_package.all;
 
--- This testbench tests the Payload encoding/decoding of the TYPE2_wrapper entities.
+-- This testbench tests the Payload encoding/decoding of the TYPE2_interface entities.
--- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
+-- It does so by interconnecting the writer and reader interface, setting some inputs to the writer and checking if the reader returns the same data.
 -- This testbench tests only the Big Endian encoding/decoding.
 
-entity L1_Type2_wrapper_test1 is
+entity L1_Type2_interface_test1 is
 end entity;
 
-architecture testbench of L1_Type2_wrapper_test1 is
+architecture testbench of L1_Type2_interface_test1 is
     
     signal clk, reset : std_logic := '0';
     signal ready, valid, last_word : std_logic := '0';
@@ -51,7 +51,7 @@ architecture testbench of L1_Type2_wrapper_test1 is
     signal TestString_r_in, TestString_w_in, TestString_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    uut_w : entity work.Type2_writer_wrapper(arch)
+    uut_w : entity work.Type2_writer_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -138,7 +138,7 @@ begin
             encode_done                         => encode_done
         );
     
-    uut_r : entity work.Type2_reader_wrapper(arch)
+    uut_r : entity work.Type2_reader_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -255,7 +255,7 @@ begin
         end procedure;
     begin
         
-        SetAlertLogName("Type2_wrapper - Level 1 - (Big Endian) - Encoding/Decoding");
+        SetAlertLogName("Type2_interface - Level 1 - (Big Endian) - Encoding/Decoding");
         SetAlertEnable(FAILURE, TRUE);
         SetAlertEnable(ERROR, TRUE);
         SetAlertEnable(WARNING, TRUE);

src/Tests/Level_1/L1_Type2_interface_test2.vhd

@@ -11,14 +11,14 @@ use work.rtps_config_package.all;
 use work.rtps_test_package.all;
 use work.Type2_package.all;
 
--- This testbench tests the Payload encoding/decoding of the TYPE2_wrapper entities.
+-- This testbench tests the Payload encoding/decoding of the TYPE2_interface entities.
--- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
+-- It does so by interconnecting the writer and reader interface, setting some inputs to the writer and checking if the reader returns the same data.
 -- This testbench tests only the Little Endian encoding/decoding.
 
-entity L1_Type2_wrapper_test2 is
+entity L1_Type2_interface_test2 is
 end entity;
 
-architecture testbench of L1_Type2_wrapper_test2 is
+architecture testbench of L1_Type2_interface_test2 is
     
     signal clk, reset : std_logic := '0';
     signal ready, valid, last_word : std_logic := '0';
@@ -51,7 +51,7 @@ architecture testbench of L1_Type2_wrapper_test2 is
     signal TestString_r_in, TestString_w_in, TestString_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    uut_w : entity work.Type2_writer_wrapper(arch)
+    uut_w : entity work.Type2_writer_interface(arch)
         generic map (
             LITTLE_ENDIAN   => '1'
         )
@@ -141,7 +141,7 @@ begin
             encode_done                         => encode_done
         );
     
-    uut_r : entity work.Type2_reader_wrapper(arch)
+    uut_r : entity work.Type2_reader_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,
@@ -258,7 +258,7 @@ begin
         end procedure;
     begin
         
-        SetAlertLogName("Type2_wrapper - Level 1 - (Little Endian) - Encoding/Decoding");
+        SetAlertLogName("Type2_interface - Level 1 - (Little Endian) - Encoding/Decoding");
         SetAlertEnable(FAILURE, TRUE);
         SetAlertEnable(ERROR, TRUE);
         SetAlertEnable(WARNING, TRUE);

src/Tests/Level_1/L1_Type2_key_holder_test1.vhd

@@ -12,7 +12,7 @@ use work.rtps_test_package.all;
 use work.Type2_package.all;
 
 -- This testbench tests the KEY_HOLDER commands of TYPE2.
--- It uses the writer_wrapper to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
+-- It uses the writer_interface to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
 -- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
 -- The payload is sent in Big Endian.
 
@@ -56,7 +56,7 @@ architecture testbench of L1_Type2_key_holder_test1 is
     signal TestString_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    Type2_writer_wrapper_inst : entity work.Type2_writer_wrapper(arch)
+    Type2_writer_interface_inst : entity work.Type2_writer_interface(arch)
         port map (
             clk                                 => clk,
             reset                               => reset,

src/Tests/Level_1/L1_Type2_key_holder_test2.vhd

@@ -12,7 +12,7 @@ use work.rtps_test_package.all;
 use work.Type2_package.all;
 
 -- This testbench tests the KEY_HOLDER commands of TYPE2.
--- It uses the writer_wrapper to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
+-- It uses the writer_interface to send a valid payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
 -- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
 -- The payload is sent in Little Endian.
 
@@ -56,7 +56,7 @@ architecture testbench of L1_Type2_key_holder_test2 is
     signal TestString_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
 begin
     
-    Type2_writer_wrapper_inst : entity work.Type2_writer_wrapper(arch)
+    Type2_writer_interface_inst : entity work.Type2_writer_interface(arch)
         generic map (
             LITTLE_ENDIAN   => '1'
         )

src/Tests/Level_2/L2_Testbench_Lib2.vhd

@@ -85,7 +85,7 @@ architecture arch of L2_Testbench_Lib2 is
     
 begin
     
-    Type1_writer_wrapper_w_inst : entity Testbench_Lib2.Type1_writer_wrapper(arch)
+    Type1_writer_interface_w_inst : entity Testbench_Lib2.Type1_writer_interface(arch)
         port map (
             -- SYSTEM
             clk                         => clk,

src/Tests/Level_2/L2_Testbench_Lib3.vhd

@@ -113,7 +113,7 @@ architecture arch of L2_Testbench_Lib3 is
     
 begin
     
-    Type1_reader_wrapper_r_inst : entity Testbench_Lib3.Type1_reader_wrapper(arch)
+    Type1_reader_interface_r_inst : entity Testbench_Lib3.Type1_reader_interface(arch)
         port map (
             -- SYSTEM
             clk                                 => clk,

src/Tests/Level_2/L2_testbench_Lib4.vhd

@@ -572,7 +572,7 @@ begin
     --#####################################################################
     
     
-    Type1_reader_wrapper_inst : entity work.Type1_reader_wrapper(arch)
+    Type1_reader_interface_inst : entity work.Type1_reader_interface(arch)
         port map (
             -- SYSTEM
             clk                                 => clk,
@@ -650,7 +650,7 @@ begin
         );
     
     
-    Type1_writer_wrapper_inst : entity work.Type1_writer_wrapper(arch)
+    Type1_writer_interface_inst : entity work.Type1_writer_interface(arch)
         port map (
             -- SYSTEM
             clk                         => clk,

src/Tests/Level_2/L2_testbench_Lib5.vhd

@@ -594,7 +594,7 @@ begin
     --#####################################################################
     
     
-    Type1_reader_wrapper_inst : entity work.Type1_reader_wrapper(arch)
+    Type1_reader_interface_inst : entity work.Type1_reader_interface(arch)
         port map (
             -- SYSTEM
             clk                                 => clk,
@@ -672,7 +672,7 @@ begin
         );
     
     
-    Type1_writer_wrapper_inst : entity work.Type1_writer_wrapper(arch)
+    Type1_writer_interface_inst : entity work.Type1_writer_interface(arch)
         port map (
             -- SYSTEM
             clk                         => clk,

src/Tests/Type1_reader_interface.vhd

@@ -9,7 +9,7 @@ use work.rtps_package.all;
 use work.rtps_config_package.all;
 use work.Type1_package.all;
 
-entity Type1_reader_wrapper is
+entity Type1_reader_interface is
     port (
         -- SYSTEM
         clk                                 : in std_logic;
@@ -89,7 +89,7 @@ entity Type1_reader_wrapper is
     );
 end entity;
 
-architecture arch of Type1_reader_wrapper is
+architecture arch of Type1_reader_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/Tests/Type1_writer_interface.vhd

@@ -9,7 +9,7 @@ use work.rtps_package.all;
 use work.rtps_config_package.all;
 use work.Type1_package.all;
 
-entity Type1_writer_wrapper is
+entity Type1_writer_interface is
     generic (
         LITTLE_ENDIAN   : std_logic := '0'
     );
@@ -60,7 +60,7 @@ entity Type1_writer_wrapper is
     );
 end entity;
 
-architecture arch of Type1_writer_wrapper is
+architecture arch of Type1_writer_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/Tests/Type2_reader_interface.vhd

@@ -9,7 +9,7 @@ use work.rtps_package.all;
 use work.rtps_config_package.all;
 use work.Type2_package.all;
 
-entity Type2_reader_wrapper is
+entity Type2_reader_interface is
     port (
         -- SYSTEM
         clk                                 : in std_logic;
@@ -126,7 +126,7 @@ entity Type2_reader_wrapper is
     );
 end entity;
 
-architecture arch of Type2_reader_wrapper is
+architecture arch of Type2_reader_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/Tests/Type2_writer_interface.vhd

@@ -9,7 +9,7 @@ use work.rtps_package.all;
 use work.rtps_config_package.all;
 use work.Type2_package.all;
 
-entity Type2_writer_wrapper is
+entity Type2_writer_interface is
     generic (
         LITTLE_ENDIAN   : std_logic := '0'
     );
@@ -110,7 +110,7 @@ entity Type2_writer_wrapper is
     );
 end entity;
 
-architecture arch of Type2_writer_wrapper is
+architecture arch of Type2_writer_interface is
     
     --*****TYPE DECLARATION*****
     -- FSM states. Explained below in detail

src/Tests/testbench.pro

@@ -29,8 +29,8 @@ analyze ../key_holder.vhd
 analyze ../key_hash_generator.vhd
 analyze test_key_hash_generator.vhd
 analyze Type1_package.vhd
-analyze Type1_reader_wrapper.vhd
+analyze Type1_reader_interface.vhd
-analyze Type1_writer_wrapper.vhd
+analyze Type1_writer_interface.vhd
 analyze Type1_key_holder.vhd
 analyze Level_2/L2_Testbench_Lib2.vhd
 analyze Type1_config.vhd
@@ -63,8 +63,8 @@ analyze ../key_holder.vhd
 analyze ../key_hash_generator.vhd
 analyze test_key_hash_generator.vhd
 analyze Type1_package.vhd
-analyze Type1_reader_wrapper.vhd
+analyze Type1_reader_interface.vhd
-analyze Type1_writer_wrapper.vhd
+analyze Type1_writer_interface.vhd
 analyze Type1_key_holder.vhd
 analyze Level_2/L2_Testbench_Lib3.vhd
 analyze Type1_config.vhd
@@ -97,8 +97,8 @@ analyze ../key_holder.vhd
 analyze ../key_hash_generator.vhd
 analyze test_key_hash_generator.vhd
 analyze Type1_package.vhd
-analyze Type1_reader_wrapper.vhd
+analyze Type1_reader_interface.vhd
-analyze Type1_writer_wrapper.vhd
+analyze Type1_writer_interface.vhd
 analyze Type1_key_holder.vhd
 analyze test_loopback.vhd
 analyze Level_2/L2_Testbench_Lib4.vhd
@@ -132,8 +132,8 @@ analyze ../key_holder.vhd
 analyze ../key_hash_generator.vhd
 analyze test_key_hash_generator.vhd
 analyze Type1_package.vhd
-analyze Type1_reader_wrapper.vhd
+analyze Type1_reader_interface.vhd
-analyze Type1_writer_wrapper.vhd
+analyze Type1_writer_interface.vhd
 analyze Type1_key_holder.vhd
 analyze test_loopback.vhd
 analyze Level_2/L2_Testbench_Lib5.vhd
@@ -168,12 +168,12 @@ analyze ../key_holder.vhd
 analyze ../key_hash_generator.vhd
 analyze test_key_hash_generator.vhd
 analyze Type1_package.vhd
-analyze Type1_reader_wrapper.vhd
+analyze Type1_reader_interface.vhd
-analyze Type1_writer_wrapper.vhd
+analyze Type1_writer_interface.vhd
 analyze Type1_key_holder.vhd
 analyze Type2_package.vhd
-analyze Type2_reader_wrapper.vhd
+analyze Type2_reader_interface.vhd
-analyze Type2_writer_wrapper.vhd
+analyze Type2_writer_interface.vhd
 analyze Type2_key_holder.vhd
 analyze test_key_holder.vhd
 analyze ScoreBoard_test_memory.vhd
@@ -242,12 +242,12 @@ analyze Level_0/L0_dds_reader_test4_arznriu.vhd
 analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
 analyze Level_0/L0_dds_reader_test6_arzkriu.vhd
 analyze Level_0/L0_dds_reader_test7_arzkriu.vhd
-analyze Level_1/L1_Type1_wrapper_test1.vhd
+analyze Level_1/L1_Type1_interface_test1.vhd
-analyze Level_1/L1_Type1_wrapper_test2.vhd
+analyze Level_1/L1_Type1_interface_test2.vhd
 analyze Level_1/L1_Type1_key_holder_test1.vhd
 analyze Level_1/L1_Type1_key_holder_test2.vhd
-analyze Level_1/L1_Type2_wrapper_test1.vhd
+analyze Level_1/L1_Type2_interface_test1.vhd
-analyze Level_1/L1_Type2_wrapper_test2.vhd
+analyze Level_1/L1_Type2_interface_test2.vhd
 analyze Level_1/L1_Type2_key_holder_test1.vhd
 analyze Level_1/L1_Type2_key_holder_test2.vhd
 analyze Level_2/L2_Type1_test1.vhd
@@ -319,12 +319,12 @@ simulate L0_dds_reader_test4_arznriu
 simulate L0_dds_reader_test5_arzkriu
 simulate L0_dds_reader_test6_arzkriu
 simulate L0_dds_reader_test7_arzkriu
-simulate L1_Type1_wrapper_test1
+simulate L1_Type1_interface_test1
-simulate L1_Type1_wrapper_test2
+simulate L1_Type1_interface_test2
 simulate L1_Type1_key_holder_test1
 simulate L1_Type1_key_holder_test2
-simulate L1_Type2_wrapper_test1
+simulate L1_Type2_interface_test1
-simulate L1_Type2_wrapper_test2
+simulate L1_Type2_interface_test2
 simulate L1_Type2_key_holder_test1
 simulate L1_Type2_key_holder_test2
 simulate L2_Type1_test1

syn/DE10-Nano/top.qsf

@@ -47,6 +47,10 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
 set_global_assignment -name SDC_FILE ../top.sdc
 set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
@@ -59,8 +63,8 @@ set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL
 set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_config.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_wrapper.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_interface.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_wrapper.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_interface.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/verbatim_key_hash_generator.vhd -hdl_version VHDL_2008
@@ -94,7 +98,3 @@ set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_ver
 set_global_assignment -name VHDL_FILE ../syn_config.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top