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* Updated Vivado Project

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* Synthesis fixes in RTPS Handler
This commit is contained in:
Greek 2020-05-27 17:55:54 +02:00
parent 052a4054b9
commit 41f41b6530
2 changed files with 19 additions and 31 deletions
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14
src/rtps_handler.vhd
View File

@ -218,7 +218,7 @@ architecture arch of rtps_handler is
-- 'endianness' argument.
function endian_swap( endianness : std_logic;
data :std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(data'reverse_range);
variable ret : std_logic_vector(data'range);
begin
-- Assert that Data Signal is Byte aligned
assert (data'length mod 8 = 0) severity failure;
@ -226,7 +226,7 @@ architecture arch of rtps_handler is
if (endianness = '1') then
-- Reverse byte Order
for i in 0 to (data'length/8)-1 loop
ret(i*8+8-1 downto i*8) := data((3-i)*8+8-1 downto (3-i)*8);
ret(i*8+8-1 downto i*8) := data(((data'length/8)-1-i)*8+8-1 downto ((data'length/8)-1-i)*8);
end loop;
-- Big Endian
else
@ -345,7 +345,7 @@ begin
flags_next <= flags;
src_entityid_next <= src_entityid;
user_endpoint_next <= user_endpoint;
builtin_endpoint_next <= builtin_endpoint_next;
builtin_endpoint_next <= builtin_endpoint;
return_stage_next <= return_stage;
numlocators_next <= numlocators;
payload_length_next <= payload_length;
@ -957,7 +957,7 @@ begin
-- Push Submessage Contents
stage_next <= PUSH_PAYLOAD;
-- Fix alignement
align_offset <= data_header_offset_latch;
align_offset_next <= data_header_offset_latch;
end if;
end if;
when PUSH_PAYLOAD =>
@ -974,7 +974,7 @@ begin
-- Begin parsing of next submessage
stage_next <= RTPS_SUB_HEADER;
-- Fix alignement
align_offset <= offset_latch;
align_offset_next <= offset_latch;
else
-- Push Normal (Endianness is not handled here)
output_sig <= aligned_data_in;
@ -997,7 +997,7 @@ begin
-- Begin parsing of next submessage
stage_next <= RTPS_SUB_HEADER;
-- Fix alignement
align_offset <= offset_latch;
align_offset_next <= offset_latch;
-- Submessage has still "unknown" Content
else
stage_next <= SKIP_SUB;
@ -1023,7 +1023,7 @@ begin
-- Begin parsing of next submessage
stage_next <= RTPS_SUB_HEADER;
-- Fix alignement
align_offset <= offset_latch;
align_offset_next <= offset_latch;
end if;
-- Latch Input for alignment purposes
align_sig_next <= data_in(23 downto 0);

28
syn/project_1.xpr
View File

@ -60,25 +60,19 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/ip_package.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/math_pkg.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/single_port_ram.vhd">
<File Path="$PPRDIR/../src/rtps_package.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/ipv4_in.vhd">
<File Path="$PPRDIR/../src/rtps_handler.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@ -86,9 +80,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ipv4_in_handler"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="with_frag"/>
<Option Name="TopModule" Val="rtps_handler"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
@ -108,9 +100,8 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ipv4_in_handler"/>
<Option Name="TopModule" Val="rtps_handler"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="with_frag"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@ -145,20 +136,16 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@ -169,6 +156,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>