* Updated Vivado Project
* Synthesis fixes in RTPS Handler
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@ -218,7 +218,7 @@ architecture arch of rtps_handler is
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-- 'endianness' argument.
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function endian_swap( endianness : std_logic;
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data :std_logic_vector) return std_logic_vector is
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variable ret : std_logic_vector(data'reverse_range);
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variable ret : std_logic_vector(data'range);
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begin
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-- Assert that Data Signal is Byte aligned
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assert (data'length mod 8 = 0) severity failure;
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@ -226,7 +226,7 @@ architecture arch of rtps_handler is
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if (endianness = '1') then
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-- Reverse byte Order
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for i in 0 to (data'length/8)-1 loop
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ret(i*8+8-1 downto i*8) := data((3-i)*8+8-1 downto (3-i)*8);
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ret(i*8+8-1 downto i*8) := data(((data'length/8)-1-i)*8+8-1 downto ((data'length/8)-1-i)*8);
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end loop;
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-- Big Endian
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else
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@ -345,7 +345,7 @@ begin
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flags_next <= flags;
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src_entityid_next <= src_entityid;
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user_endpoint_next <= user_endpoint;
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builtin_endpoint_next <= builtin_endpoint_next;
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builtin_endpoint_next <= builtin_endpoint;
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return_stage_next <= return_stage;
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numlocators_next <= numlocators;
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payload_length_next <= payload_length;
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@ -955,9 +955,9 @@ begin
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-- End of Data Header
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if (read_cnt = data_header_end) then
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-- Push Submessage Contents
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stage_next <= PUSH_PAYLOAD;
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stage_next <= PUSH_PAYLOAD;
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-- Fix alignement
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align_offset <= data_header_offset_latch;
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align_offset_next <= data_header_offset_latch;
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end if;
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end if;
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when PUSH_PAYLOAD =>
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@ -972,9 +972,9 @@ begin
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output_sig <= pad_signal(offset_latch, aligned_data_in);
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wr_sig <= '1';
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-- Begin parsing of next submessage
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stage_next <= RTPS_SUB_HEADER;
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stage_next <= RTPS_SUB_HEADER;
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-- Fix alignement
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align_offset <= offset_latch;
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align_offset_next <= offset_latch;
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else
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-- Push Normal (Endianness is not handled here)
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output_sig <= aligned_data_in;
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@ -995,9 +995,9 @@ begin
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-- End of Submessage
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elsif (read_cnt > sub_end) then
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-- Begin parsing of next submessage
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stage_next <= RTPS_SUB_HEADER;
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stage_next <= RTPS_SUB_HEADER;
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-- Fix alignement
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align_offset <= offset_latch;
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align_offset_next <= offset_latch;
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-- Submessage has still "unknown" Content
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else
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stage_next <= SKIP_SUB;
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@ -1021,9 +1021,9 @@ begin
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-- End of Submessage
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elsif (read_cnt = sub_end) then
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-- Begin parsing of next submessage
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stage_next <= RTPS_SUB_HEADER;
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stage_next <= RTPS_SUB_HEADER;
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-- Fix alignement
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align_offset <= offset_latch;
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align_offset_next <= offset_latch;
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end if;
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-- Latch Input for alignment purposes
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align_sig_next <= data_in(23 downto 0);
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@ -60,25 +60,19 @@
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../src/ip_package.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../src/math_pkg.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../src/single_port_ram.vhd">
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<File Path="$PPRDIR/../src/rtps_package.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../src/ipv4_in.vhd">
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<File Path="$PPRDIR/../src/rtps_handler.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@ -86,9 +80,7 @@
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="ipv4_in_handler"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopArchitecture" Val="with_frag"/>
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<Option Name="TopModule" Val="rtps_handler"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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@ -108,9 +100,8 @@
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="ipv4_in_handler"/>
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<Option Name="TopModule" Val="rtps_handler"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopArchitecture" Val="with_frag"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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@ -145,20 +136,16 @@
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<Runs Version="1" Minor="10">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@ -169,6 +156,7 @@
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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