diff --git a/src/TEMPLATE_key_holder.vhd b/src/TEMPLATE_key_holder.vhd
index 2dabe76..6e47c09 100644
--- a/src/TEMPLATE_key_holder.vhd
+++ b/src/TEMPLATE_key_holder.vhd
@@ -99,6 +99,7 @@ begin
     
     main_prc : process (all)
         variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
+        variable cnt2_ref   : std_logic_vector(1 downto 0);
     begin
         -- DEFAULT
         stage_next                  <= stage;
@@ -344,8 +345,10 @@ begin
             when PUSH =>
                 -- Push to Key Hash Generator
                 if (opcode_latch = READ_KEY_HASH) then
+                    -- XXX: Assumes data_out_latch is 32 bits (TODO)
+                    cnt2_ref    := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
                     -- Mark Last Word
-                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
+                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
                         last_word_in_kh <= '1';
                     end if;
                     
@@ -354,7 +357,7 @@ begin
                     -- Output Guard
                     if (ready_in_kh = '1') then
                         -- Last Byte
-                        if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
+                        if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
                             -- Reset
                             cnt_2_next  <= 0;
                             -- Alignment Operation in process
diff --git a/src/Tests/Type1_key_holder.vhd b/src/Tests/Type1_key_holder.vhd
index d7edef2..3fe197f 100644
--- a/src/Tests/Type1_key_holder.vhd
+++ b/src/Tests/Type1_key_holder.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -92,6 +95,7 @@ begin
     
     main_prc : process (all)
         variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
+        variable cnt2_ref   : std_logic_vector(1 downto 0);
     begin
         -- DEFAULT
         stage_next                  <= stage;
@@ -348,8 +352,10 @@ begin
             when PUSH =>
                 -- Push to Key Hash Generator
                 if (opcode_latch = READ_KEY_HASH) then
+                    -- XXX: Assumes data_out_latch is 32 bits (TODO)
+                    cnt2_ref    := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
                     -- Mark Last Word
-                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
+                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
                         last_word_in_kh <= '1';
                     end if;
                     
@@ -358,7 +364,7 @@ begin
                     -- Output Guard
                     if (ready_in_kh = '1') then
                         -- Last Byte
-                        if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
+                        if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
                             -- Reset
                             cnt_2_next  <= 0;
                             -- Alignment Operation in process
diff --git a/src/Tests/Type2_key_holder.vhd b/src/Tests/Type2_key_holder.vhd
index 6c7e28c..9a667c4 100644
--- a/src/Tests/Type2_key_holder.vhd
+++ b/src/Tests/Type2_key_holder.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -127,6 +130,7 @@ begin
     
     main_prc : process (all)
         variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
+        variable cnt2_ref   : std_logic_vector(1 downto 0);
     begin
         -- DEFAULT
         stage_next                  <= stage;
@@ -548,8 +552,10 @@ begin
             when PUSH =>
                 -- Push to Key Hash Generator
                 if (opcode_latch = READ_KEY_HASH) then
+                    -- XXX: Assumes data_out_latch is 32 bits (TODO)
+                    cnt2_ref    := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
                     -- Mark Last Word
-                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
+                    if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
                         last_word_in_kh <= '1';
                     end if;
                     
@@ -558,7 +564,7 @@ begin
                     -- Output Guard
                     if (ready_in_kh = '1') then
                         -- Last Byte
-                        if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
+                        if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
                             -- Reset
                             cnt_2_next  <= 0;
                             -- Alignment Operation in process