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Move key_holder inside the DDS Entities

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This commit is contained in:
Greek 2021-11-19 12:00:07 +01:00
parent e87d84ba24
commit 4830645a5a
38 changed files with 412 additions and 2512 deletions
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2
src/TEMPLATE_key_holder.vhd
View File

@ -6,7 +6,7 @@ use work.rtps_package.all;
use work.rtps_config_package.all;
use work.Type2_package.all;
architecture TYPE2 of key_holder is
architecture TYPENAME of key_holder is
--*****COMPONENT DECLARATION*****
component key_hash_generator is

93
src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd
View File

@ -71,22 +71,19 @@ architecture testbench of L0_dds_reader_test1_abzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -103,11 +100,9 @@ architecture testbench of L0_dds_reader_test1_abzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -165,18 +160,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1697,74 +1680,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd
View File

@ -70,22 +70,19 @@ architecture testbench of L0_dds_reader_test1_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -102,11 +99,9 @@ architecture testbench of L0_dds_reader_test1_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -164,18 +159,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1703,74 +1686,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd
View File

@ -70,22 +70,19 @@ architecture testbench of L0_dds_reader_test1_arzksiu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -102,11 +99,9 @@ architecture testbench of L0_dds_reader_test1_arzksiu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -164,18 +159,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1701,74 +1684,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd
View File

@ -49,22 +49,19 @@ architecture testbench of L0_dds_reader_test1_arznriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -81,11 +78,9 @@ architecture testbench of L0_dds_reader_test1_arznriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -143,18 +138,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1152,74 +1135,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd
View File

@ -71,22 +71,19 @@ architecture testbench of L0_dds_reader_test1_lbzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -103,11 +100,9 @@ architecture testbench of L0_dds_reader_test1_lbzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -165,18 +160,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1697,74 +1680,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd
View File

@ -71,22 +71,19 @@ architecture testbench of L0_dds_reader_test1_lrzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -103,11 +100,9 @@ architecture testbench of L0_dds_reader_test1_lrzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -165,18 +160,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1697,74 +1680,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test2_arpkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test2_arpkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -616,74 +599,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd
View File

@ -64,22 +64,19 @@ architecture testbench of L0_dds_reader_test3_arzkrio is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -96,11 +93,9 @@ architecture testbench of L0_dds_reader_test3_arzkrio is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -158,18 +153,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1489,74 +1472,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd
View File

@ -64,22 +64,19 @@ architecture testbench of L0_dds_reader_test3_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -96,11 +93,9 @@ architecture testbench of L0_dds_reader_test3_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -158,18 +153,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1488,74 +1471,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd
View File

@ -64,22 +64,19 @@ architecture testbench of L0_dds_reader_test3_arzkrto is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -96,11 +93,9 @@ architecture testbench of L0_dds_reader_test3_arzkrto is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -158,18 +153,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1488,74 +1471,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd
View File

@ -64,22 +64,19 @@ architecture testbench of L0_dds_reader_test3_arzkrtu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -96,11 +93,9 @@ architecture testbench of L0_dds_reader_test3_arzkrtu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -158,18 +153,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1488,74 +1471,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd
View File

@ -65,22 +65,19 @@ architecture testbench of L0_dds_reader_test3_arzksto is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -97,11 +94,9 @@ architecture testbench of L0_dds_reader_test3_arzksto is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -159,18 +154,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1507,74 +1490,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd
View File

@ -45,22 +45,19 @@ architecture testbench of L0_dds_reader_test3_arznriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -77,11 +74,9 @@ architecture testbench of L0_dds_reader_test3_arznriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -139,18 +134,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -848,74 +831,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test4_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test4_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -771,74 +754,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test4_arznriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test4_arznriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -640,74 +623,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test5_arzkriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test5_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_SAMPLE_REJECT);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test5_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -935,74 +918,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test6_arzkriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test6_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_SAMPLE_REJECT);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test6_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -705,74 +688,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_reader_test7_arzkriu.vhd
View File

@ -24,22 +24,19 @@ architecture testbench of L0_dds_reader_test7_arzkriu is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_SAMPLE_REJECT);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
@ -56,11 +53,9 @@ architecture testbench of L0_dds_reader_test7_arzkriu is
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
@ -118,18 +113,6 @@ begin
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -645,74 +628,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test1_afk.vhd
View File

@ -89,7 +89,6 @@ architecture testbench of L0_dds_writer_test1_afk is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
type RTPS_WRITER_TEST_TYPE is record
opcode : HISTORY_CACHE_OPCODE_TYPE;
cc : CACHE_CHANGE_TYPE;
@ -115,17 +114,15 @@ architecture testbench of L0_dds_writer_test1_afk is
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -134,11 +131,9 @@ architecture testbench of L0_dds_writer_test1_afk is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_TEST_TYPE := DEFAULT_DDS_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType;
@ -198,18 +193,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -2139,74 +2122,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test1_aik.vhd
View File

@ -89,23 +89,20 @@ architecture testbench of L0_dds_writer_test1_aik is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -114,11 +111,9 @@ architecture testbench of L0_dds_writer_test1_aik is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType;
@ -178,18 +173,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -2119,74 +2102,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test1_ain.vhd
View File

@ -62,23 +62,20 @@ architecture testbench of L0_dds_writer_test1_ain is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -87,11 +84,9 @@ architecture testbench of L0_dds_writer_test1_ain is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType;
@ -151,18 +146,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1043,74 +1026,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test1_lik.vhd
View File

@ -89,23 +89,20 @@ architecture testbench of L0_dds_writer_test1_lik is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -114,11 +111,9 @@ architecture testbench of L0_dds_writer_test1_lik is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType;
@ -178,18 +173,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -1891,74 +1874,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test2_aik.vhd
View File

@ -23,23 +23,20 @@ architecture testbench of L0_dds_writer_test2_aik is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -48,11 +45,9 @@ architecture testbench of L0_dds_writer_test2_aik is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType;
@ -112,18 +107,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -524,74 +507,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test3_aik.vhd
View File

@ -23,23 +23,20 @@ architecture testbench of L0_dds_writer_test3_aik is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -48,11 +45,9 @@ architecture testbench of L0_dds_writer_test3_aik is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id : AlertLogIDType;
@ -112,18 +107,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -651,74 +634,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test3_ain.vhd
View File

@ -23,23 +23,20 @@ architecture testbench of L0_dds_writer_test3_ain is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -48,11 +45,9 @@ architecture testbench of L0_dds_writer_test3_ain is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id : AlertLogIDType;
@ -112,18 +107,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -566,74 +549,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test4_aik.vhd
View File

@ -23,23 +23,20 @@ architecture testbench of L0_dds_writer_test4_aik is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK, CHECK_LIVELINESS);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -48,11 +45,9 @@ architecture testbench of L0_dds_writer_test4_aik is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, assert_id : AlertLogIDType;
@ -112,18 +107,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -661,74 +644,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

93
src/Tests/Level_0/L0_dds_writer_test5_afk.vhd
View File

@ -23,23 +23,20 @@ architecture testbench of L0_dds_writer_test5_afk is
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK);
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0';
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
@ -48,11 +45,9 @@ architecture testbench of L0_dds_writer_test5_afk is
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, rtps_cnt, kh_cnt : natural := 0;
signal dds_cnt, rtps_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, assert_id : AlertLogIDType;
@ -112,18 +107,6 @@ begin
cc_kind => cc_kind,
cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
@ -643,74 +626,6 @@ begin
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;

35
src/Tests/Level_2/L2_Testbench_Lib2.vhd
View File

@ -60,9 +60,6 @@ architecture arch of L2_Testbench_Lib2 is
signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_OK;
signal data_in_wr_dds, data_out_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal start_dds_kh, ack_dds_kh, valid_in_dds_kh, ready_in_dds_kh, last_word_in_dds_kh, ready_out_dds_kh, valid_out_dds_kh, last_word_out_dds_kh, abort_dds_kh : std_logic := '0';
signal opcode_dds_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal data_in_dds_kh, data_out_dds_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, get_data_dds_rtps, valid_out_dds_rtps, ready_out_dds_rtps, last_word_out_dds_rtps, liveliness_assertion_dds_rtps, data_available_dds_rtps : std_logic := '0';
signal data_out_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
@ -168,19 +165,6 @@ begin
cc_kind => cc_kind_dds_rtps,
cc_source_timestamp => cc_source_timestamp_dds_rtps,
cc_seq_nr => cc_seq_nr_dds_rtps,
-- TO/FROM KEY_HOLDER
start_kh => start_dds_kh,
opcode_kh => opcode_dds_kh,
ack_kh => ack_dds_kh,
data_in_kh => data_in_dds_kh,
valid_in_kh => valid_in_dds_kh,
ready_in_kh => ready_in_dds_kh,
last_word_in_kh => last_word_in_dds_kh,
data_out_kh => data_out_dds_kh,
valid_out_kh => valid_out_dds_kh,
ready_out_kh => ready_out_dds_kh,
last_word_out_kh => last_word_out_dds_kh,
abort_kh => abort_dds_kh,
-- TO/FROM USER ENTITY
start_dds => start_wr_dds,
ack_dds => ack_wr_dds,
@ -202,25 +186,6 @@ begin
status => status_wr_dds
);
key_holder_Type1_w_inst : entity Testbench_Lib2.key_holder(TYPE1)
port map (
clk => clk,
reset => reset,
start => start_dds_kh,
opcode => opcode_dds_kh,
ack => ack_dds_kh,
decode_error => open,
abort => abort_dds_kh,
data_in => data_out_dds_kh,
valid_in => valid_out_dds_kh,
ready_in => ready_out_dds_kh,
last_word_in => last_word_out_dds_kh,
data_out => data_in_dds_kh,
valid_out => valid_in_dds_kh,
ready_out => ready_in_dds_kh,
last_word_out => last_word_in_dds_kh
);
rtps_writer_w_inst : entity Testbench_Lib2.rtps_writer(arch)
generic map (
ID => 0,

38
src/Tests/Level_2/L2_Testbench_Lib3.vhd
View File

@ -92,11 +92,7 @@ architecture arch of L2_Testbench_Lib3 is
signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE := OK;
signal data_in_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_dds_kh, ack_dds_kh, valid_in_dds_kh, ready_in_dds_kh, last_word_in_dds_kh, ready_out_dds_kh, valid_out_dds_kh, last_word_out_dds_kh, abort_dds_kh : std_logic := '0';
signal opcode_dds_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal data_in_dds_kh, data_out_dds_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
--
signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE := (others => (others => '0'));
@ -216,19 +212,6 @@ begin
valid_in_rtps => valid_in_dds_rtps,
ready_in_rtps => ready_in_dds_rtps,
last_word_in_rtps => last_word_in_dds_rtps,
-- TO/FROM KEY_HOLDER
start_kh => start_dds_kh,
opcode_kh => opcode_dds_kh,
ack_kh => ack_dds_kh,
data_in_kh => data_in_dds_kh,
valid_in_kh => valid_in_dds_kh,
ready_in_kh => ready_in_dds_kh,
last_word_in_kh => last_word_in_dds_kh,
data_out_kh => data_out_dds_kh,
valid_out_kh => valid_out_dds_kh,
ready_out_kh => ready_out_dds_kh,
last_word_out_kh => last_word_out_dds_kh,
abort_kh => abort_dds_kh,
-- TO USER ENTITY
start_dds => start_wr_dds,
ack_dds => ack_wr_dds,
@ -265,25 +248,6 @@ begin
status => status_wr_dds
);
key_holder_Type1_r_inst : entity Testbench_Lib3.key_holder(TYPE1)
port map (
clk => clk,
reset => reset,
start => start_dds_kh,
opcode => opcode_dds_kh,
ack => ack_dds_kh,
decode_error => open,
abort => abort_dds_kh,
data_in => data_out_dds_kh,
valid_in => valid_out_dds_kh,
ready_in => ready_out_dds_kh,
last_word_in => last_word_out_dds_kh,
data_out => data_in_dds_kh,
valid_out => valid_in_dds_kh,
ready_out => ready_in_dds_kh,
last_word_out => last_word_in_dds_kh
);
rtps_reader_r_inst : entity Testbench_Lib3.rtps_reader(arch)
generic map (
ID => 0,

4
src/Tests/Level_2/L2_Type1_test1.vhd
View File

@ -82,7 +82,7 @@ architecture testbench of L2_Type1_test1 is
begin
Lib2_inst : entity work.L2_Testbench_Lib2(arch)
Lib2_inst : entity Testbench_Lib2.L2_Testbench_Lib2(arch)
port map (
-- SYSTEM
clk => clk,
@ -154,7 +154,7 @@ begin
free => open
);
Lib3_inst : entity work.L2_Testbench_Lib3(arch)
Lib3_inst : entity Testbench_Lib3.L2_Testbench_Lib3(arch)
port map (
-- SYSTEM
clk => clk,

15
src/Tests/Type1_config.vhd Normal file
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@ -0,0 +1,15 @@
configuration key_holder_conf1 of dds_writer is
for arch
for key_holder_inst : key_holder
use entity work.key_holder(TYPE1);
end for;
end for;
end configuration;
configuration key_holder_conf2 of dds_reader is
for arch
for key_holder_inst : key_holder
use entity work.key_holder(TYPE1);
end for;
end for;
end configuration;

15
src/Tests/test_config.vhd Normal file
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@ -0,0 +1,15 @@
configuration key_holder_conf1 of dds_writer is
for arch
for key_holder_inst : key_holder
use entity work.key_holder(test);
end for;
end for;
end configuration;
configuration key_holder_conf2 of dds_reader is
for arch
for key_holder_inst : key_holder
use entity work.key_holder(test);
end for;
end for;
end configuration;

152
src/Tests/test_key_holder.vhd Normal file
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@ -0,0 +1,152 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rtps_package.all;
use work.rtps_config_package.all;
architecture test of key_holder is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,SKIP_PAYLOAD,GET_KEY_HASH,PUSH_KEY_HASH);
-- ###GENERATED END###
-- *MAIN PROCESS*
signal stage, stage_next : STAGE_TYPE := IDLE;
signal cnt, cnt_next : natural range 0 to 5 := 0;
signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL;
begin
main_prc : process (all)
begin
-- DEFAULT
stage_next <= stage;
key_hash_next <= key_hash;
cnt_next <= cnt;
ready_in <= '0';
valid_out <= '0';
last_word_out <= '0';
decode_error <= '0';
ack <= '0';
data_out <= (others => '0');
case (stage) is
when IDLE =>
if (start = '1') then
case (opcode) is
when PUSH_DATA =>
ack <= '1';
stage_next <= GET_KEY_HASH;
cnt_next <= 0;
-- Reset
key_hash_next <= HANDLE_NIL;
when PUSH_SERIALIZED_KEY =>
ack <= '1';
stage_next <= GET_KEY_HASH;
cnt_next <= 0;
-- Reset
key_hash_next <= HANDLE_NIL;
when READ_KEY_HASH =>
ack <= '1';
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
when READ_SERIALIZED_KEY =>
ack <= '1';
stage_next <= PUSH_KEY_HASH;
cnt_next <= 0;
when others =>
null;
end case;
end if;
when GET_KEY_HASH =>
ready_in <= '1';
-- Input Guard
if (valid_in = '1') then
key_hash_next(cnt) <= not data_in;
if (cnt = 3) then
if (last_word_in = '1') then
stage_next <= IDLE;
else
stage_next <= SKIP_PAYLOAD;
end if;
else
assert (last_word_in /= '1') report "Test Key Holder expects a Payload of at least 4 Words" severity FAILURE;
cnt_next <= cnt + 1;
end if;
end if;
when SKIP_PAYLOAD =>
-- Skip Read
ready_in <= '1';
-- EXIT
if (last_word_in = '1' and valid_in = '1') then
stage_next <= IDLE;
end if;
when PUSH_KEY_HASH =>
case (cnt) is
-- Key Hash 1/4
when 0 =>
data_out <= key_hash(0);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 2/4
when 1 =>
data_out <= key_hash(1);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 3/4
when 2 =>
data_out <= key_hash(2);
valid_out <= '1';
-- Output Guard
if (ready_out = '1') then
cnt_next <= cnt + 1;
end if;
-- Key Hash 4/4
when 3 =>
data_out <= key_hash(3);
valid_out <= '1';
last_word_out <= '1';
-- Output Guard
if (ready_out = '1') then
-- DONE
stage_next <= IDLE;
end if;
when others =>
null;
end case;
when others =>
null;
end case;
-- ABORT
if (abort = '1' and stage /= IDLE) then
stage_next <= IDLE;
end if;
end process;
sync_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
stage <= IDLE;
cnt <= 0;
key_hash <= HANDLE_NIL;
else
stage <= stage_next;
cnt <= cnt_next;
key_hash <= key_hash_next;
end if;
end if;
end process;
end architecture;

8
src/Tests/testbench.pro
View File

@ -24,6 +24,8 @@ analyze Type1_package.vhd
analyze Type1_reader_wrapper.vhd
analyze Type1_writer_wrapper.vhd
analyze Type1_key_holder.vhd
analyze Level_2/L2_Testbench_Lib2.vhd
analyze Type1_config.vhd
library Testbench_Lib3
analyze ../math_pkg.vhd
@ -48,6 +50,8 @@ analyze Type1_package.vhd
analyze Type1_reader_wrapper.vhd
analyze Type1_writer_wrapper.vhd
analyze Type1_key_holder.vhd
analyze Level_2/L2_Testbench_Lib3.vhd
analyze Type1_config.vhd
# Compile
@ -78,6 +82,7 @@ analyze Type2_package.vhd
analyze Type2_reader_wrapper.vhd
analyze Type2_writer_wrapper.vhd
analyze Type2_key_holder.vhd
analyze test_key_holder.vhd
analyze ScoreBoard_test_memory.vhd
analyze ScoreBoard_builtin_endpoint.vhd
analyze Level_0/L0_rtps_handler_test1.vhd
@ -149,9 +154,8 @@ analyze Level_1/L1_Type2_wrapper_test1.vhd
analyze Level_1/L1_Type2_wrapper_test2.vhd
analyze Level_1/L1_Type2_key_holder_test1.vhd
analyze Level_1/L1_Type2_key_holder_test2.vhd
analyze Level_2/L2_Testbench_Lib2.vhd
analyze Level_2/L2_Testbench_Lib3.vhd
analyze Level_2/L2_Type1_test1.vhd
analyze test_config.vhd
simulate L0_rtps_handler_test1
simulate L0_rtps_handler_test2

68
src/dds_reader.vhd
View File

@ -42,19 +42,6 @@ entity dds_reader is
valid_in_rtps : in std_logic;
ready_in_rtps : out std_logic;
last_word_in_rtps : in std_logic;
-- TO/FROM KEY_HOLDER
start_kh : out std_logic;
opcode_kh : out KEY_HOLDER_OPCODE_TYPE;
ack_kh : in std_logic;
data_in_kh : in std_logic_vector(WORD_WIDTH-1 downto 0);
valid_in_kh : in std_logic;
ready_in_kh : out std_logic;
last_word_in_kh : in std_logic;
data_out_kh : out std_logic_vector(WORD_WIDTH-1 downto 0);
valid_out_kh : out std_logic;
ready_out_kh : in std_logic;
last_word_out_kh : out std_logic;
abort_kh : out std_logic;
-- TO USER ENTITY
start_dds : in std_logic;
ack_dds : out std_logic;
@ -94,6 +81,31 @@ end entity;
architecture arch of dds_reader is
--*****COMPONENT DECLARATION*****
component key_holder is
port (
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
-- CONTROL
start : in std_logic;
opcode : in KEY_HOLDER_OPCODE_TYPE;
ack : out std_logic;
decode_error : out std_logic;
abort : in std_logic;
-- INPUT
ready_in : out std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in : in std_logic;
-- OUTPUT
ready_out : in std_logic;
valid_out : out std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out : out std_logic
);
end component;
--*****CONSTANT DECLARATION*****
-- NOTE: Because we need to first determine the Instance before making the ACCEPT/REJECT/DROP decision
-- we need to latch the cache change first, calculate the Key Hash if necessary, fetch the associated
@ -284,7 +296,7 @@ architecture arch of dds_reader is
addr => (others => '0')
);
--*****SIGNAL DECLARATION
--*****SIGNAL DECLARATION*****
-- *SAMPLE MEMORY CONNECTION SIGNALS*
signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sample_read : std_logic := '0';
@ -309,6 +321,11 @@ architecture arch of dds_reader is
signal inst_ready_out, inst_valid_out : std_logic := '0';
signal inst_abort_read : std_logic := '0';
-- *KEY HOLDER CONNECTION SIGNALS*
signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic := '0';
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
-- *MAIN PROCESS*
-- FSM state
signal stage, stage_next : STAGE_TYPE := IDLE;
@ -560,6 +577,29 @@ begin
--*****COMPONENT INSTANTIATION*****
key_holder_inst : key_holder
port map (
-- SYSTEM
clk => clk,
reset => reset,
-- CONTROL
start => start_kh,
opcode => opcode_kh,
ack => ack_kh,
decode_error => open,
abort => abort_kh,
-- INPUT
ready_in => ready_out_kh,
valid_in => valid_out_kh,
data_in => data_out_kh,
last_word_in => last_word_out_kh,
-- OUTPUT
ready_out => ready_in_kh,
valid_out => valid_in_kh,
data_out => data_in_kh,
last_word_out => last_word_in_kh
);
sample_mem_ctrl_inst : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH,

68
src/dds_writer.vhd
View File

@ -46,19 +46,6 @@ entity dds_writer is
cc_kind : out CACHE_CHANGE_KIND_TYPE;
cc_source_timestamp : out TIME_TYPE;
cc_seq_nr : out SEQUENCENUMBER_TYPE;
-- TO/FROM KEY_HOLDER
start_kh : out std_logic;
opcode_kh : out KEY_HOLDER_OPCODE_TYPE;
ack_kh : in std_logic;
data_in_kh : in std_logic_vector(WORD_WIDTH-1 downto 0);
valid_in_kh : in std_logic;
ready_in_kh : out std_logic;
last_word_in_kh : in std_logic;
data_out_kh : out std_logic_vector(WORD_WIDTH-1 downto 0);
valid_out_kh : out std_logic;
ready_out_kh : in std_logic;
last_word_out_kh : out std_logic;
abort_kh : out std_logic;
-- TO/FROM USER ENTITY
start_dds : in std_logic;
ack_dds : out std_logic;
@ -83,6 +70,31 @@ end entity;
architecture arch of dds_writer is
--*****COMPONENT DECLARATION*****
component key_holder is
port (
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
-- CONTROL
start : in std_logic;
opcode : in KEY_HOLDER_OPCODE_TYPE;
ack : out std_logic;
decode_error : out std_logic;
abort : in std_logic;
-- INPUT
ready_in : out std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in : in std_logic;
-- OUTPUT
ready_out : in std_logic;
valid_out : out std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out : out std_logic
);
end component;
--*****CONSTANT DECLARATION*****
-- *SAMPLE MEMORY*
-- 4-Byte Word Size of a Sample Info Entry in Memory
@ -243,7 +255,7 @@ architecture arch of dds_writer is
addr => (others => '0')
);
--*****SIGNAL DECLARATION
--*****SIGNAL DECLARATION*****
-- *SAMPLE MEMORY CONNECTION SIGNALS*
signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sample_read : std_logic := '0';
@ -268,6 +280,11 @@ architecture arch of dds_writer is
signal inst_ready_out, inst_valid_out : std_logic := '0';
signal inst_abort_read : std_logic := '0';
-- *KEY HOLDER CONNECTION SIGNALS*
signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic := '0';
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
-- *MAIN PROCESS*
-- FSM state
signal stage, stage_next : STAGE_TYPE := IDLE;
@ -465,6 +482,29 @@ begin
--*****COMPONENT INSTANTIATION*****
key_holder_inst : key_holder
port map (
-- SYSTEM
clk => clk,
reset => reset,
-- CONTROL
start => start_kh,
opcode => opcode_kh,
ack => ack_kh,
decode_error => open,
abort => abort_kh,
-- INPUT
ready_in => ready_out_kh,
valid_in => valid_out_kh,
data_in => data_out_kh,
last_word_in => last_word_out_kh,
-- OUTPUT
ready_out => ready_in_kh,
valid_out => valid_in_kh,
data_out => data_in_kh,
last_word_out => last_word_in_kh
);
sample_mem_ctrl_inst : entity work.mem_ctrl(arch)
generic map (
ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH,

8
src/key_holder.vhd
View File

@ -17,14 +17,14 @@ entity key_holder is
decode_error : out std_logic;
abort : in std_logic;
-- INPUT
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
valid_in : in std_logic;
ready_in : out std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in : in std_logic;
-- OUTPUT
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
valid_out : out std_logic;
ready_out : in std_logic;
valid_out : out std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out : out std_logic
);
end entity;