greek64/rtps-fpga
2
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add synthesis Test6

Browse Source
This commit is contained in:
Greek 2021-12-08 20:56:22 +01:00 committed by Greek64
parent 1fdf2198ba
commit 4841d0a6bb
3 changed files with 157 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
syn/DE10-Nano/top.qsf
View File

@ -47,9 +47,7 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
set_global_assignment -name SDC_FILE ../top.sdc
set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
@ -96,4 +94,7 @@ set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_ver
set_global_assignment -name VHDL_FILE ../syn_config.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

151
syn/test6.vhd Normal file
View File

@ -0,0 +1,151 @@
-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_package.all;
-- Test synthesis of array indexing
entity test6 is
port (
clk : in std_logic;
reset : in std_logic;
input1 : in TEST_ENUM;
input2 : in TEST_ENUM;
input3 : in TEST_ENUM;
input4 : in std_logic;
input5 : in std_logic;
output : out std_logic
);
end entity;
architecture arch of test6 is
type STAGE_TYPE is (IN1, IN2, IN3);
signal stage : STAGE_TYPE;
begin
-- process (all)
-- variable tmp_bool : boolean;
-- begin
-- if rising_edge(clk) then
-- if (reset = '1') then
-- output <= '0';
-- else
-- tmp_bool := TRUE;
--
-- case (input1) is
-- when A =>
-- if (input4 = '1') then
-- tmp_bool := FALSE;
-- end if;
-- when B =>
-- if (input5 = '1') then
-- tmp_bool := FALSE;
-- end if;
-- when C =>
-- tmp_bool := FALSE;
-- when others =>
-- null;
-- end case;
--
-- case (input2) is
-- when C =>
-- if (input4 = '1') then
-- tmp_bool := FALSE;
-- end if;
-- when others =>
-- null;
-- end case;
--
-- case (input3) is
-- when A =>
-- tmp_bool := FALSE;
-- when D =>
-- if (input4 = '0' and input5 = '1') then
-- tmp_bool := FALSE;
-- end if;
-- when others =>
-- null;
-- end case;
--
-- if (tmp_bool) then
-- output <= '1';
-- else
-- output <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
process (all)
begin
if rising_edge(clk) then
if (reset = '1') then
output <= '0';
stage <= IN1;
else
case (stage) is
when IN1 =>
-- DEFAULT
stage <= IN2;
case (input1) is
when A =>
if (input4 = '1') then
output <= '0';
stage <= IN1;
end if;
when B =>
if (input5 = '1') then
output <= '0';
stage <= IN1;
end if;
when C =>
output <= '0';
stage <= IN1;
when others =>
null;
end case;
when IN2 =>
-- DEFAULT
stage <= IN3;
case (input2) is
when C =>
if (input4 = '1') then
output <= '0';
stage <= IN1;
end if;
when others =>
null;
end case;
when IN3 =>
-- DEFAULT
stage <= IN1;
output <= '1';
case (input3) is
when A =>
output <= '0';
stage <= IN1;
when D =>
if (input4 = '0' and input5 = '1') then
output <= '0';
stage <= IN1;
end if;
when others =>
null;
end case;
end case;
end if;
end if;
end process;
end architecture;

2
syn/test_package.vhd
View File

@ -31,6 +31,8 @@ package test_package is
function gen_domain_ids (user_id : USER_DOMAIN_ID_TYPE) return DOMAIN_ID_TYPE;
type TEST_ENUM is (A, B, C, D, E);
end package;