diff --git a/src/Tests/Level_2/L2_testbench_Lib4.vhd b/src/Tests/Level_2/L2_testbench_Lib4.vhd
index 56ff44c..6a2ebcb 100644
--- a/src/Tests/Level_2/L2_testbench_Lib4.vhd
+++ b/src/Tests/Level_2/L2_testbench_Lib4.vhd
@@ -8,7 +8,6 @@ use ieee.numeric_std.all;
 use work.rtps_package.all;
 use work.user_config.all;
 use work.rtps_config_package.all;
-use work.rtps_test_package.all;
 use work.Type1_package.all;
 
 entity L2_Testbench_Lib4 is
diff --git a/src/Tests/test_loopback.vhd b/src/Tests/test_loopback.vhd
index ff2fffb..0cb6ea4 100644
--- a/src/Tests/test_loopback.vhd
+++ b/src/Tests/test_loopback.vhd
@@ -7,7 +7,6 @@ use ieee.numeric_std.all;
 
 use work.rtps_package.all;
 use work.rtps_config_package.all;
-use work.rtps_test_package.all;
 
 entity test_loopback is
     port (
@@ -106,7 +105,7 @@ begin
         case (stage) is
             -- Get the Instance Handle for the target Topic Instance
             when INITIALIZE =>
-                id_w    <= int(1, CDR_LONG_WIDTH);
+                id_w    <= std_logic_vector(to_unsigned(1, CDR_LONG_WIDTH));
                 case (cnt) is
                     when 0 =>
                         start_w     <= '1';
@@ -161,7 +160,7 @@ begin
                         end if;
                     when 3 =>
                         if (valid_r = '1') then
-                            assert (id_r = int(1,CDR_LONG_WIDTH)) severity FAILURE;
+                            assert (id_r = std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH))) severity FAILURE;
                             long_next   <= a_r;
                             stage_next  <= PROCESS_MESSAGE;
                         end if;
@@ -170,11 +169,11 @@ begin
                 end case;
             when PROCESS_MESSAGE =>
                 -- Add 1k to Message
-                long_next   <= std_logic_vector(unsigned(long) + unsigned(int(1000, CDR_LONG_WIDTH)));
+                long_next   <= std_logic_vector(unsigned(long) + to_unsigned(1000, CDR_LONG_WIDTH));
                 stage_next  <= WRITE;
                 cnt_next    <= 0;    
             when WRITE =>
-                id_w    <= int(2, CDR_LONG_WIDTH);
+                id_w    <= std_logic_vector(to_unsigned(2, CDR_LONG_WIDTH));
                 a_w     <= long;
                 case (cnt) is
                     when 0 =>
diff --git a/src/mem_ctrl.vhd b/src/mem_ctrl.vhd
index 5a066ac..fb01e51 100644
--- a/src/mem_ctrl.vhd
+++ b/src/mem_ctrl.vhd
@@ -84,7 +84,7 @@ begin
                     elsif ((ready_in_sig and valid_in and read) = '0' and delay_line(1) = '1') then
                         delay_cnt   <= delay_cnt - 1;
                     end if;
-                else
+                else -- READ_LATENCY = 1
                     delay_line(0)  <= ready_in_sig and valid_in and read;
                     
                     if ((ready_in_sig and valid_in and read) = '1' and delay_line(0) = '0') then