Added DATA_AVAILABLE_STATUS, and SAMPLE_REJECTED_STATUS in DDS Reader
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607273e1c4
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@ -274,6 +274,12 @@ architecture arch of history_cache is
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signal inst_data_variant : std_logic := '0';
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signal abort_khg : std_logic := '0';
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signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
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signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0');
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signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0');
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signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := (others =>'0');
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signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE := (others => (others => '0'));
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--*****ALIAS DECLARATION*****
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alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1;
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alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next;
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@ -373,7 +379,7 @@ begin
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begin
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-- Default
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stage_next <= stage;
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res_rtps <= UNDEFINED;
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res_rtps <= UNDEFINED;
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sample_addr_next <= sample_addr;
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sample_write_data <= (others => '0');
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sample_ren <= '0';
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@ -382,7 +388,7 @@ begin
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payload_write_data <= (others => '0');
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payload_ren <= '0';
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payload_wen <= '0';
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ready_in_rtps <= '0';
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ready_in_rtps <= '0';
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newest_sample_next <= newest_sample;
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empty_payload_list_head_next <= empty_payload_list_head;
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empty_sample_list_head_next <= empty_sample_list_head;
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@ -441,11 +447,16 @@ begin
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is_first_instance_sample_next <= is_first_instance_sample;
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dynamic_next_instance_next <= dynamic_next_instance;
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last_read_ts_next <= last_read_ts;
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sample_rej_cnt_next <= sample_rej_cnt;
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sample_rej_cnt_change_next <= sample_rej_cnt_change;
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sample_rej_last_reason_next <= sample_rej_last_reason;
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sample_rej_last_inst_next <= sample_rej_last_inst;
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ack_dds <= '0';
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inst_data_variant <= '0';
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done_dds <= '0';
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abort_khg <= '0';
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return_code_dds <= RETCODE_UNSUPPORTED;
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status_sig_next <= status_sig;
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case (stage) is
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when IDLE =>
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@ -596,6 +607,9 @@ begin
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key_hash_next <= instance_handle_in;
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stage_next <= FIND_NEXT_INSTANCE;
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cnt_next <= 0;
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when GET_SAMPLE_REJECTED_STATUS =>
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ack_dds <= '1';
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stage_next <= GET_SAMPLE_REJECTED_STATUS;
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when others =>
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ack_dds <= '1';
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stage_next <= UNKNOWN_OPERATION;
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@ -874,6 +888,12 @@ begin
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-- Reject Change
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res_rtps <= REJECTED;
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stage_next <= IDLE;
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-- Update Sample Reject Status
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '1';
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sample_rej_cnt_next <= sample_rej_cnt + 1;
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sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
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sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT;
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sample_rej_last_inst_next <= key_hash;
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else
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-- Accept Change (Remove Oldest Instance Sample)
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remove_oldest_inst_sample_next <= '1';
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@ -886,6 +906,12 @@ begin
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-- Reject Change
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res_rtps <= REJECTED;
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stage_next <= IDLE;
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-- Update Sample Reject Status
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '1';
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sample_rej_cnt_next <= sample_rej_cnt + 1;
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sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
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sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
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sample_rej_last_inst_next <= key_hash;
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else
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-- Accept Change (Remove Oldest Sample)
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remove_oldest_sample_next <= '1';
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@ -905,14 +931,26 @@ begin
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-- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full)
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if (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then
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-- Reject Change
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res_rtps <= REJECTED;
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res_rtps <= REJECTED;
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stage_next <= IDLE;
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-- Update Sample Reject Status
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '1';
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sample_rej_cnt_next <= sample_rej_cnt + 1;
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sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
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sample_rej_last_reason_next <= REJECTED_BY_INSTANCES_LIMIT;
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sample_rej_last_inst_next <= key_hash;
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-- RESOURCE_LIMITS_QOS (MAX_SAMPLES)
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elsif (empty_sample_list_head = empty_sample_list_tail) then
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if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then
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-- Reject Change
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res_rtps <= REJECTED;
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res_rtps <= REJECTED;
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stage_next <= IDLE;
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-- Update Sample Reject Status
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '1';
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sample_rej_cnt_next <= sample_rej_cnt + 1;
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sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
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sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
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sample_rej_last_inst_next <= key_hash;
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else
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-- Accept Change (Remove Oldest Sample)
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remove_oldest_sample_next <= '1';
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@ -1264,6 +1302,9 @@ begin
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newest_sample_next <= empty_sample_list_head;
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end if;
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-- Signal Data Available
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status_sig_next(DATA_AVAILABLE_STATUS) <= '1';
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-- NOTE: added_new_instance and remove_oldest_sample are NOT mutual exclusive, but Instance Removal takes precedence.
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-- New Instance was added, and Instance Memory is Full
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@ -1528,6 +1569,13 @@ begin
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when 1 =>
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res_rtps <= REJECTED;
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stage_next <= IDLE;
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-- TODO: Add a new Reject Status? (E.g. REJECTED_BY_PAYLOAD_LIMIT?, or UNSPECIFIED REJECT?)
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-- Update Sample Reject Status
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '1';
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sample_rej_cnt_next <= sample_rej_cnt + 1;
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sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
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sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
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sample_rej_last_inst_next <= key_hash;
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when others =>
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null;
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end case;
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@ -2127,6 +2175,9 @@ begin
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end if;
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end if;
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-- Reset Data Available Status
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status_sig_next(DATA_AVAILABLE_STATUS) <= '0';
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-- Sample not marked as Read
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if (sample_status_info(READ_FLAG) /= '1') then
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-- Mark Sample as Read
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@ -2445,6 +2496,51 @@ begin
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null;
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end case;
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end if;
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when GET_SAMPLE_REJECTED_STATUS =>
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if (ready_out_dds = '1') then
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cnt_next <= cnt + 1;
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valid_out_dds <= '1';
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case (cnt) is
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-- Total Count
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when 0 =>
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data_out_dds <= sample_rej_cnt;
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-- Total Count Change
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when 1 =>
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data_out_dds <= sample_rej_cnt_change;
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-- Reset
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sample_rej_cnt_change_next <= (others => '0');
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-- Last Reason
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when 2 =>
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data_out_dds <= sample_rej_last_reason;
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-- Reset
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sample_rej_last_reason <= NOT_REJECTED;
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-- Last Instance Handle 1/4
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when 3 =>
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data_out_dds <= sample_rej_last_inst(0);
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-- Last Instance Handle 2/4
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when 4 =>
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data_out_dds <= sample_rej_last_inst(1);
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-- Last Instance Handle 3/4
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when 5 =>
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data_out_dds <= sample_rej_last_inst(2);
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-- Last Instance Handle 4/4
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when 6 =>
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data_out_dds <= sample_rej_last_inst(3);
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last_word_out_dds <= '1';
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-- Return Code
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when 7 =>
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done_dds <= '1';
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return_code_dds <= RETCODE_OK;
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-- Reset
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status_sig_next(SAMPLE_REJECTED_STATUS) <= '0';
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-- DONE
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stage_next <= IDLE;
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when others =>
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null;
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end case;
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end if;
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when others =>
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null;
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end case;
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