From 49f3c3eb65c6e1a35849b6b96e6fb797833902a1 Mon Sep 17 00:00:00 2001 From: Greek Date: Sun, 18 Apr 2021 15:50:53 +0200 Subject: [PATCH] Change DDS Reader - User Interface The si_last Signal was replaced with eoc (End of Collection) The eoc signal is pulled high after the last si_valid. --- .../Level_0/L0_dds_reader_test1_abzkriu.vhd | 24 +- .../Level_0/L0_dds_reader_test1_arzkriu.vhd | 24 +- .../Level_0/L0_dds_reader_test1_arzksiu.vhd | 24 +- .../Level_0/L0_dds_reader_test1_arznriu.vhd | 24 +- .../Level_0/L0_dds_reader_test1_lbzkriu.vhd | 24 +- .../Level_0/L0_dds_reader_test1_lrzkriu.vhd | 24 +- src/dds_reader.vhd | 223 ++++++++++-------- 7 files changed, 196 insertions(+), 171 deletions(-) diff --git a/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd index 5601147..c7aa81f 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd @@ -65,7 +65,7 @@ architecture testbench of L0_dds_reader_test1_abzkriu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -82,7 +82,7 @@ architecture testbench of L0_dds_reader_test1_abzkriu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -107,7 +107,7 @@ architecture testbench of L0_dds_reader_test1_abzkriu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -201,7 +201,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -297,7 +297,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -1226,11 +1226,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -1239,12 +1234,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -1253,13 +1249,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd index 6257cd9..8e20d5a 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd @@ -64,7 +64,7 @@ architecture testbench of L0_dds_reader_test1_arzkriu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -81,7 +81,7 @@ architecture testbench of L0_dds_reader_test1_arzkriu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -106,7 +106,7 @@ architecture testbench of L0_dds_reader_test1_arzkriu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -200,7 +200,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -296,7 +296,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -1235,11 +1235,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -1248,12 +1243,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -1262,13 +1258,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd index 23c7e7e..55c5900 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd @@ -64,7 +64,7 @@ architecture testbench of L0_dds_reader_test1_arzksiu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -81,7 +81,7 @@ architecture testbench of L0_dds_reader_test1_arzksiu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -106,7 +106,7 @@ architecture testbench of L0_dds_reader_test1_arzksiu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -200,7 +200,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -296,7 +296,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -1230,11 +1230,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -1243,12 +1238,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -1257,13 +1253,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd index f6238c8..c86f5b4 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd @@ -24,7 +24,7 @@ architecture testbench of L0_dds_reader_test1_arznriu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -41,7 +41,7 @@ architecture testbench of L0_dds_reader_test1_arznriu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -66,7 +66,7 @@ architecture testbench of L0_dds_reader_test1_arznriu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -160,7 +160,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -256,7 +256,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -785,11 +785,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -798,12 +793,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -812,13 +808,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd index e2708b5..77c62a8 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd @@ -65,7 +65,7 @@ architecture testbench of L0_dds_reader_test1_lbzkriu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -82,7 +82,7 @@ architecture testbench of L0_dds_reader_test1_lbzkriu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -107,7 +107,7 @@ architecture testbench of L0_dds_reader_test1_lbzkriu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -201,7 +201,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -297,7 +297,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -1225,11 +1225,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -1238,12 +1233,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -1252,13 +1248,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd index 60fa217..98007f6 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd @@ -65,7 +65,7 @@ architecture testbench of L0_dds_reader_test1_lrzkriu is constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); @@ -82,7 +82,7 @@ architecture testbench of L0_dds_reader_test1_lrzkriu is signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, si_last, abort_kh : std_logic := '0'; + signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0'; signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; @@ -107,7 +107,7 @@ architecture testbench of L0_dds_reader_test1_lrzkriu is shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, last_id, valid_id : AlertLogIDType; + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -201,7 +201,7 @@ begin si_absolute_generation_rank => si_absolute_generation_rank, si_valid_data => si_valid_data, si_valid => si_valid, - si_last => si_last, + eoc => eoc, status => status ); @@ -297,7 +297,7 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - last_id <= GetAlertLogID("Last Sample", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); @@ -1226,11 +1226,6 @@ begin AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (dds_cnt = col.len-1) then - AffirmIf(last_id, si_last = '1', "Last Signal not pulled High"); - else - AffirmIf(last_id, si_last = '0', "Last Signal pulled High"); - end if; if (si_valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; @@ -1239,12 +1234,13 @@ begin AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_cnt <= dds_cnt + 1; end if; end if; end if; + AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); when CHECK_DATA => if (valid_out_dds = '1') then AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); @@ -1253,13 +1249,17 @@ begin AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE - dds_stage <= IDLE; + dds_stage <= WAIT_EOC; else dds_stage <= CHECK_SI; dds_cnt <= dds_cnt + 1; end if; end if; end if; + when WAIT_EOC => + if (eoc = '1') then + dds_stage <= IDLE; + end if; end case; end if; diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index ac9ed45..0497fcd 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -84,7 +84,7 @@ entity dds_reader is si_absolute_generation_rank : out std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0); si_valid_data : out std_logic; si_valid : out std_logic; - si_last : out std_logic; + eoc : out std_logic; -- Communication Status status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) ); @@ -351,6 +351,8 @@ architecture arch of dds_reader is signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- General Purpose Sample Pointer signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + -- General Purpose Sample Pointer + signal sample_addr_latch_5, sample_addr_latch_5_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- General Purpose Instance Pointer signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- General Purpose Instance Pointer @@ -413,6 +415,8 @@ architecture arch of dds_reader is signal dynamic_next_instance, dynamic_next_instance_next : std_logic := '0'; -- Signal containing the number of currently stale Instances signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES))-1 := 0; + -- Test signal used for testbench synchronisation + signal idle_sig : std_logic := '0'; -- *COMMUNICATION STATUS* signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); @@ -442,7 +446,6 @@ architecture arch of dds_reader is signal si_absolute_generation_rank_sig, si_absolute_generation_rank_sig_next : unsigned(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); signal si_valid_data_sig, si_valid_data_sig_next : std_logic := '0'; signal si_valid_sig, si_valid_sig_next : std_logic := '0'; - signal si_last_sig, si_last_sig_next : std_logic := '0'; -- *INSTANCE MEMORY PROCESS* -- Instance Memory FSM state @@ -475,14 +478,16 @@ architecture arch of dds_reader is --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; - alias first_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; - alias first_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; + alias sel_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; + alias sel_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2; alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2_next; alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3; alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3_next; - alias second_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; - alias second_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; + alias sample_p1 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; + alias sample_p1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; + alias sample_p2 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5; + alias sample_p2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5_next; alias cur_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1; alias cur_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1_next; alias next_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; @@ -596,7 +601,6 @@ begin si_absolute_generation_rank <= std_logic_vector(si_absolute_generation_rank_sig); si_valid_data <= si_valid_data_sig; si_valid <= si_valid_sig; - si_last <= si_last_sig; status <= status_sig; -- *Main State Machine* @@ -657,6 +661,7 @@ begin sample_addr_latch_2_next <= sample_addr_latch_2; sample_addr_latch_3_next <= sample_addr_latch_3; sample_addr_latch_4_next <= sample_addr_latch_4; + sample_addr_latch_5_next <= sample_addr_latch_5; writer_pos_next <= writer_pos; key_hash_next <= key_hash; sample_status_info_next <= sample_status_info; @@ -675,7 +680,6 @@ begin si_absolute_generation_rank_sig_next <= si_absolute_generation_rank_sig; si_valid_data_sig_next <= si_valid_data_sig; si_valid_sig_next <= si_valid_sig; - si_last_sig_next <= si_last_sig; sample_state_next <= sample_state; view_state_next <= view_state; instance_state_next <= instance_state; @@ -739,6 +743,8 @@ begin last_word_out_kh <= '0'; valid_out_dds <= '0'; last_word_out_dds <= '0'; + idle_sig <= '0'; + eoc <= '0'; data_out_dds <= (others => '0'); data_out_kh <= (others => '0'); writer_bitmap <= ZERO_WRITER_BITMAP_ARRAY; @@ -751,6 +757,7 @@ begin case (stage) is when IDLE => + idle_sig <= '1'; -- Reset remove_oldest_inst_sample_next <= '0'; remove_oldest_sample_next <= '0'; @@ -871,8 +878,9 @@ begin max_samples_latch_next <= unsigned(max_samples_dds); -- Reset - first_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - second_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; single_sample_next <= '0'; single_instance_next <= '0' when WITH_KEY else '1'; collection_cnt_next <= (others => '0'); @@ -887,7 +895,6 @@ begin si_generation_rank_sig_next <= (others => '0'); si_valid_data_sig_next <= '0'; si_valid_sig_next <= '0'; - si_last_sig_next <= '0'; si_absolute_generation_rank_sig_next <= (others => '0'); si_disposed_generation_count_sig_next <= (others => '0'); si_no_writers_generation_count_sig_next <= (others => '0'); @@ -1470,7 +1477,7 @@ begin cur_inst_next <= inst_addr_base; -- TIME_BASED_FILTER QOS - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and time <= inst_data.ignore_deadline) then + if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and time < inst_data.ignore_deadline) then -- Drop Change done_rtps <= '1'; ret_rtps <= OK; @@ -2495,13 +2502,24 @@ begin end if; if (is_take = '1') then + -- cur_inst has no more samples in collection if (si_sample_rank_sig = 0) then + -- Skipped Sample available + if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= sample_p2; + else + cur_sample_next <= sample_p1; + end if; cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + else + cur_sample_next <= sample_p1; end if; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; -- Continue Processing - cur_sample_next <= second_sample; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; + stage_next <= GET_NEXT_SAMPLE; + cnt_next <= 0; elsif (is_lifespan_check = '1') then -- Reached End of Samples if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -2756,9 +2774,9 @@ begin else -- Select Sample collection_cnt_next <= collection_cnt + 1; - first_sample_next <= cur_sample; + sel_sample_next <= cur_sample; -- Latch Next Sample (For resume purposes) - second_sample_next <= next_sample; + sample_p1_next <= next_sample; si_sample_rank_sig_next <= si_sample_rank_sig - 1; cnt_next <= cnt + 4; --Skip all Instance Related States end if; @@ -2786,6 +2804,10 @@ begin -- Skip Sample cnt_next <= 18; sample_abort_read <= '1'; + -- Latch first skipped Sample + if (sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) then + sample_p2_next <= cur_sample; + end if; else -- Get Instance Data next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); @@ -2794,9 +2816,9 @@ begin else -- Select Sample collection_cnt_next <= collection_cnt + 1; - first_sample_next <= cur_sample; + sel_sample_next <= cur_sample; -- Latch Next Sample (For resume purposes) - second_sample_next <= next_sample; + sample_p1_next <= next_sample; -- First Instance Sample -- NOTE: This state only enters with a sample rank of 0 and cur_inst set, when the @@ -2892,9 +2914,9 @@ begin collection_cnt_max_next <= collection_cnt + 1; si_sample_rank_sig_next <= (others => '0'); cur_inst_next <= next_inst; - first_sample_next <= cur_sample; + sel_sample_next <= cur_sample; -- Latch Next Sample (For resume purposes) - second_sample_next <= next_sample; + sample_p1_next <= next_sample; cnt_next <= cnt + 1; else if (WITH_KEY) then @@ -3012,27 +3034,49 @@ begin end if; -- Exit State when 18 => - -- Reached End of Samples - if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- Exit Condition (Sample Selected) - if (first_sample = cur_sample) then - -- Sample not marked as Read - if (sample_status_info(SSI_READ_FLAG) /= '1') then - -- Mark Sample as Read - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= sample_status_info; - sample_write_data(SSI_READ_FLAG) <= '1'; - -- Memory Control Flow Guard - if (sample_ready_in = '1') then + -- Exit Condition (Sample Selected) + if (sel_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + -- Sample not marked as Read + if (sample_status_info(SSI_READ_FLAG) /= '1') then + -- Mark Sample as Read + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_write_data <= sample_status_info; + sample_write_data(SSI_READ_FLAG) <= '1'; + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + -- Pre-Calculation already done for selected Instance (Or not necessary) + if (si_sample_rank_sig /= 0 or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FINALIZE_SAMPLE_INFO; cnt_next <= 0; + else + -- Calculate Instance Sample Ranks + cur_sample_next <= next_sample; + stage_next <= PRE_CALCULATE; + cnt_next <= 0; end if; - else - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; end if; else + -- Pre-Calculation already done for selected Instance (Or not necessary) + if (si_sample_rank_sig /= 0 or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= FINALIZE_SAMPLE_INFO; + cnt_next <= 0; + else + -- Calculate Instance Sample Ranks + cur_sample_next <= next_sample; + stage_next <= PRE_CALCULATE; + cnt_next <= 0; + end if; + end if; + + -- First Sample Selected + if (collection_cnt = 1) then + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + end if; + else + -- End of Samples + if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then -- Collection Empty if (collection_cnt = 0) then -- READ_NEXT_INSTANCE/TAKE_NEXT_INSTANCE Operation @@ -3047,47 +3091,19 @@ begin stage_next <= IDLE; end if; else - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= IDLE; - end if; - end if; - else - cur_sample_next <= next_sample; - cnt_next <= 0; - - -- Exit Condition (Sample Selected) - if (first_sample = cur_sample) then - -- Sample not marked as Read - if (sample_status_info(SSI_READ_FLAG) /= '1') then - -- Mark Sample as Read - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= sample_status_info; - sample_write_data(SSI_READ_FLAG) <= '1'; - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - -- Pre-Calculation already done for selected Instance (Or not necessary) - if (si_sample_rank_sig /= 0 or collection_cnt_max = max_samples_latch) then - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; - else - -- Calculate Instance Sample Ranks - stage_next <= PRE_CALCULATE; - cnt_next <= 0; - end if; - end if; - else - -- Pre-Calculation already done for selected Instance (Or not necessary) - if (si_sample_rank_sig /= 0 or collection_cnt_max = max_samples_latch) then - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; - else - -- Calculate Instance Sample Ranks - stage_next <= PRE_CALCULATE; - cnt_next <= 0; + -- Mark End of Collection + eoc <= '1'; + stage_next <= IDLE; + -- Consecutive Instance Sample Order of multiple Instances + if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0' and single_sample = '0') then + -- Unmark Instances + unmark_instances_flag_next <= '1'; end if; end if; + else + -- Continue Searching + cur_sample_next <= next_sample; + cnt_next <= 0; end if; end if; when others => @@ -3358,8 +3374,6 @@ begin if (not WITH_KEY or inst_op_done = '1') then -- Instance Data valid if (not WITH_KEY or (inst_addr_base = cur_inst and check_mask(current_imf,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) then - done_dds <= '1'; - return_code_dds <= RETCODE_OK; -- Sample Info View State if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then @@ -3394,11 +3408,6 @@ begin si_valid_data_sig_next <= '0'; end if; - -- Collection End - if (collection_cnt = max_samples_latch or second_sample = SAMPLE_MEMORY_MAX_ADDRESS or (si_sample_rank_sig = 0 and single_instance = '1')) then - si_last_sig_next <= '1'; - end if; - si_valid_sig_next <= '1'; cnt_next <= 1; else @@ -3449,14 +3458,8 @@ begin -- Consecutive Instance Sample Order of multiple Instances if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0' and single_sample = '0') then - -- Completed Collection - if (si_last_sig = '1') then - -- Unmark Instances - unmark_instances_flag_next <= '1'; - else - -- Mark Instance - status_info_update(ISI_MARK_FLAG) <= '1'; - end if; + -- Mark Instance + status_info_update(ISI_MARK_FLAG) <= '1'; end if; -- Instance is NOT_VIEWED and sample is from last generation of Instance @@ -3474,9 +3477,17 @@ begin end if; -- End of Collection - if (si_last_sig = '1') then + if (collection_cnt = max_samples_latch or (sample_p1 = SAMPLE_MEMORY_MAX_ADDRESS and sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) or (si_sample_rank_sig = 0 and single_instance = '1')) then + -- Mark End of Collection + eoc <= '1'; + -- Consecutive Instance Sample Order of multiple Instances + if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0' and single_sample = '0') then + -- Unmark Instances + unmark_instances_flag_next <= '1'; + end if; + if (is_take = '1') then - cur_sample_next <= first_sample; + cur_sample_next <= sel_sample; stage_next <= REMOVE_SAMPLE; cnt_next <= 0; is_take_next <= '0'; -- Return to IDLE from REMOVE @@ -3487,18 +3498,28 @@ begin else if (is_take = '1') then -- Remove Sample - cur_sample_next <= first_sample; + cur_sample_next <= sel_sample; stage_next <= REMOVE_SAMPLE; cnt_next <= 0; else -- cur_inst has no more samples in collection if (si_sample_rank_sig = 0) then + -- Skipped Sample available + if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= sample_p2; + else + cur_sample_next <= sample_p1; + end if; cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + else + cur_sample_next <= sample_p1; end if; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; -- Continue Processing - cur_sample_next <= second_sample; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; + stage_next <= GET_NEXT_SAMPLE; + cnt_next <= 0; end if; end if; end if; @@ -3706,6 +3727,10 @@ begin cur_inst_next <= inst_addr_base; stage_next <= GET_NEXT_SAMPLE; cnt_next <= 0; + -- Reset + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; else -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. inst_op_start <= '1'; @@ -5884,7 +5909,6 @@ begin remove_oldest_inst_sample <= '0'; si_valid_data_sig <= '0'; si_valid_sig <= '0'; - si_last_sig <= '0'; is_take <= '0'; single_instance <= '0'; single_sample <= '0'; @@ -5895,6 +5919,7 @@ begin sample_addr_latch_2 <= (others => '0'); sample_addr_latch_3 <= (others => '0'); sample_addr_latch_4 <= (others => '0'); + sample_addr_latch_5 <= (others => '0'); payload_addr_latch_1 <= (others => '0'); payload_addr_latch_2 <= (others => '0'); inst_addr_latch_1 <= (others => '0'); @@ -5965,7 +5990,6 @@ begin remove_oldest_inst_sample <= remove_oldest_inst_sample_next; si_valid_data_sig <= si_valid_data_sig_next; si_valid_sig <= si_valid_sig_next; - si_last_sig <= si_last_sig_next; is_take <= is_take_next; single_instance <= single_instance_next; single_sample <= single_sample_next; @@ -5976,6 +6000,7 @@ begin sample_addr_latch_2 <= sample_addr_latch_2_next; sample_addr_latch_3 <= sample_addr_latch_3_next; sample_addr_latch_4 <= sample_addr_latch_4_next; + sample_addr_latch_5 <= sample_addr_latch_5_next; payload_addr_latch_1 <= payload_addr_latch_1_next; payload_addr_latch_2 <= payload_addr_latch_2_next; inst_addr_latch_1 <= inst_addr_latch_1_next;