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REMOVE_WRITER DDS Operation generates Samples

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The REMOVE_WRITER DDS Operation of DDS Reader now generates Samples if
the Instance State changes.
Updated testbench.
Added checks for DATA_AVAILABLE communication status.
This commit is contained in:
Greek 2021-04-30 12:53:43 +02:00
parent 996c1fe962
commit 4fc9029554
30 changed files with 2732 additions and 622 deletions
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50
sim/L0_dds_reader_test1_abzkriu.do
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32
sim/L0_dds_reader_test1_arzkriu.do
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sim/L0_dds_reader_test1_arzksiu.do
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sim/L0_dds_reader_test1_arznriu.do
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@ -74,7 +74,7 @@ add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/s
add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_absolute_generation_rank
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/si_valid_data
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/si_valid
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/si_last
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/eoc
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/get_data_dds
add wave -noupdate -group DDS -divider OUTPUT
add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/ready_out_dds
@ -120,6 +120,18 @@ add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_rea
add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/next_payload
add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_inst
add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/next_inst
add wave -noupdate -divider MISC
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/trigger_sample_gen
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/wait_for_sample_removal
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/sample_p1
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/sample_p2
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt_max
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_generation_rank
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_generation_rank
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/max_samples_latch
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/single_instance
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/is_take
add wave -noupdate -divider TESTBENCH
add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_start
add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_stage
@ -143,21 +155,11 @@ add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/valid_ou
add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/ready_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/last_word_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/abort_kh
add wave -noupdate -divider MISC
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/first_sample
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt_max
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_generation_rank
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_generation_rank
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/second_sample
add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/max_samples_latch
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/single_instance
add wave -noupdate /l0_dds_reader_test1_arznriu/uut/is_take
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {94698 ps} 0} {{Cursor 2} {115175000 ps} 1}
WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1}
quietly wave cursor active 1
configure wave -namecolwidth 174
configure wave -valuecolwidth 209
configure wave -namecolwidth 187
configure wave -valuecolwidth 206
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
@ -170,4 +172,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {940034 ps}
WaveRestoreZoom {76925214 ps} {77858935 ps}

50
sim/L0_dds_reader_test1_lbzkriu.do
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sim/L0_dds_reader_test1_lrzkriu.do
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3
sim/modelsim.ini
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@ -19,8 +19,7 @@ others = $MODEL_TECH/../modelsim.ini
default = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/default.lib
osvvm = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/osvvm.lib
Level0-rtps_handler = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Level0-rtps_handler.lib
Level0-rtps_builtin_endpoint = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Level0-rtps_builtin_endpoint.lib
Testbench-Lib = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench-Lib.lib
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.

7
src/REF.txt
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@ -589,15 +589,16 @@ STATUS INFO
-----------
31............24..............16..............8...............0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+---------------------------------------------------+-+-+-+-+-+
| UNUSED |M|V|L|W|D|
+---------------------------------------------------+-+-+-+-+-+
+-------------------------------------------------+-+-+-+-+-+-+
| UNUSED |G|M|V|L|W|D|
+-------------------------------------------------+-+-+-+-+-+-+
D...NOT_ALIVE_DISPOSED
W...NOT_ALIVE_NO_WRITERS
L...LIVELINESS FLAG
V...VIEW STATE
M...MARK
G...GENERATE SAMPLE
WRITER
------

5
src/TODO.txt
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@ -59,6 +59,7 @@
* Can a Participant unmatch an Endpoint by marking it's announcing sequence number in a GAP message?
* Is DEADLINE per-INSTANCE or per-INSTANCE-and-WRITER?
- Since the matching is per-WRITER the assumption would be per-INSTANCE-and-WRITER
- It is per-INSTANCE
* Only a sub-part of the DDS QOS are actually relevant for the RTPS. Should I remove the QoS Specifications from the RTPS Package?
* What happens if we get a sample with a source timestamp earlier than the last sample that was accessed by the DataReader when using DESTINATION ORDER BY_SOURCE_TIMESTAMP? Is the smaple dropped?
* The spec does not define the serialized Key (KEY=1 DATA MESSAGE)
@ -79,6 +80,8 @@
* If a Keyed Reader receives a DATA Message with no Key hash and no Payload, it will drop it since there is no way to determine the instance (And the SN will never be accepted).
* If a Best Effort Remote Reader sends a ACKNACK, he will indirectly receive a lease deadline and may timeout (DoS Attack)
* Since the Instance Handle has to be Unique but also orderable, we could use the actual Instance Memory Base Address. Since the Instances are in a list, we also have implicitly an order to all registered Instances. [It may be necessary to add a PREV pointer to the IMF to better support the read_previous_isntance operation]
* Does the DEADLINE_QOS apply also to NOT_ALIVE Instances? (Current implementation makes no distinction)
* Does TIME_BASED_FILTER also apply to meta-samples (DISPOSED, NO_WRITERS)? That is an easy way to not get convergent state in different DDS Readers. What do other implementations do?
* Fast-RTPS does not follow DDSI-RTPS Specification
- Open Github Issue
@ -365,6 +368,8 @@ DESIGN DECISIONS
valid and does not have to be recalculated.
This is the only case in which a Dispose Sample can be missed/dropped, and may lead to different
Data Readers having different Generation Counters (depending on their reception order).
NOTE: The NOT_ALIVE Samples are always added to the end of the list, not depending on their TS. This
is the only exception in which samples TS does not follow their list order.
PROTOCOL UNCOMPLIANCE
=====================

461
src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd
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src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd
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@ -18,6 +18,10 @@ use work.rtps_test_package.all;
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: SAMPLE WITH ALIGNED PAYLOAD
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
@ -106,7 +110,7 @@ architecture testbench of L0_dds_reader_test1_arzkriu is
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
-- *FUNCTION DECLARATION*
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
@ -206,9 +210,11 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
@ -275,6 +281,23 @@ begin
end if;
end procedure;
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;
begin
SetAlertLogName("dds_reader - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Level 0 - RTPS Handling");
@ -300,12 +323,14 @@ begin
valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := gen_key_hash;
kh2 := gen_key_hash;
kh3 := gen_key_hash;
kh4 := gen_key_hash;
kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh5 := gen_key_hash;
@ -318,6 +343,8 @@ begin
-- ISTATE: -
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -340,10 +367,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, 0, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -366,10 +396,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VAILDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -381,6 +414,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
@ -399,6 +438,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -409,10 +454,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S2+, 0, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
-- TEST: DISPOSE SAMPLE [KNOWN INSTANCE]
-- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
@ -428,10 +476,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, 0, 0
-- ISTATE: I1:DISPOSED
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -449,10 +500,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE
-- WRITER: W0:I1, W1:I2
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -472,10 +526,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, I3S1
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO);
@ -485,6 +542,12 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, I3S1
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -495,10 +558,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S2+, I2S1+, I3S1, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -516,6 +582,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I2S1+, I3S1, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -526,10 +598,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I2S1+, I3S1, 0, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
@ -540,10 +615,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -561,6 +639,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
@ -572,10 +656,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
@ -589,10 +676,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, I4S1
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -604,6 +694,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, I4S1
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -614,10 +710,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, 0
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -635,13 +734,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, 0
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh4;
cc.payload := gen_payload(kh4,10);
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(9,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -653,16 +758,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh2;
cc.payload := gen_payload(kh2,10);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(10,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE]
@ -674,13 +782,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(11,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
@ -692,8 +806,18 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -704,10 +828,61 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.src_timestamp := check_time;
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S1, I4S2, I2S2-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- NOTE: We read the current KH4 Samples, so that we can easiy remove the new KH4 Sample
Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := READ_INSTANCE;
dds.max_samples := 2;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S1, I4S2, I2S2-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.src_timestamp := check_time;
Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE_INSTANCE;
@ -716,30 +891,38 @@ begin
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_dds;
wait_on_dds;
-- MEM: I3S1, I3S2, I4S2, 0
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S3-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
-- NOTE: We read the current KH4 Sample, so that we can easiy remove the new KH4 Sample
Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := READ_INSTANCE;
dds.opcode := TAKE_INSTANCE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.sstate := NOT_READ_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := HANDLE_NIL;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(12,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
-- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH]
@ -755,16 +938,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I3S1, I3S2, I4S2, I4S3-
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S4-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(10,0);
cc.src_timestamp := gen_duration(13,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
@ -777,26 +963,59 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S4-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.max_samples := 2;
dds.sstate := NOT_READ_SAMPLE_STATE;
dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
-- MEM: I3S1, I3S2, I4S2, 0
wait_on_idle;
-- MEM: I3S2, I4S2, 0, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh3;
cc.payload := gen_payload(kh3,10);
cc.src_timestamp := gen_duration(14,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 2;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,30);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(15,0);
-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE
@ -808,13 +1027,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,20);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(16,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -827,10 +1052,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I3S1, I3S2, I4S2, I1S1+
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, I1S1+
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1, W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -842,20 +1070,23 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1, W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(10,0);
cc.src_timestamp := gen_duration(17,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (ACCEPTED)", INFO);
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
@ -863,16 +1094,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1,I4 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(11,0);
cc.src_timestamp := gen_duration(18,0);
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER]
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
@ -885,16 +1119,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(12,0);
cc.src_timestamp := gen_duration(19,0);
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER]
@ -906,16 +1143,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.payload := gen_payload(kh2,5);
cc.src_timestamp := gen_duration(13,0);
cc.src_timestamp := gen_duration(20,0);
-- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE]
@ -927,16 +1167,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(14,0);
cc.src_timestamp := gen_duration(21,0);
Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -948,16 +1191,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, 0, 0, 0
-- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(14,0);
cc.src_timestamp := gen_duration(22,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -969,13 +1215,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, 0, 0, 0
-- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(15,0);
cc.src_timestamp := gen_duration(23,0);
-- TEST: FILTER SAMPLE [KNOWN INSTANCE]
-- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -990,16 +1242,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(16,0);
cc.src_timestamp := gen_duration(24,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION]
@ -1011,16 +1266,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh2;
cc.payload := gen_payload(kh2,10);
cc.src_timestamp := gen_duration(17,0);
cc.src_timestamp := gen_duration(25,0);
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE]
@ -1035,10 +1293,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, I2S1, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1050,16 +1311,19 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(18,0);
cc.src_timestamp := gen_duration(26,0);
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -1071,20 +1335,23 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, 0, 0, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(19,0);
cc.src_timestamp := gen_duration(27,0);
-- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO);
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
@ -1094,16 +1361,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(20,0);
cc.src_timestamp := gen_duration(28,0);
-- TEST: FILTER SAMPLE [UNKNOWN INSTANCE]
@ -1115,6 +1385,12 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
@ -1135,16 +1411,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I1S4-, I1S5-, I3S3, 0
wait_on_idle;
-- MEM: I1S4-, I1S5-, I3S4, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.payload := gen_payload(kh2,5);
cc.src_timestamp := gen_duration(21,0);
cc.src_timestamp := gen_duration(29,0);
Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -1156,10 +1435,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I1S4-, I1S5-, I3S3, I2S2-
wait_on_idle;
-- MEM: I1S4-, I1S5-, I3S4, I2S2-
-- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1171,16 +1453,19 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(22,0);
cc.src_timestamp := gen_duration(30,0);
-- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE]
@ -1194,10 +1479,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I4S1-, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1209,6 +1497,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I4S1-, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);

379
src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd
View File

@ -18,6 +18,10 @@ use work.rtps_test_package.all;
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: SAMPLE WITH ALIGNED PAYLOAD
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
@ -106,7 +110,7 @@ architecture testbench of L0_dds_reader_test1_arzksiu is
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
-- *FUNCTION DECLARATION*
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
@ -206,9 +210,11 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
@ -275,6 +281,23 @@ begin
end if;
end procedure;
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;
begin
SetAlertLogName("dds_reader - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS, ACCESS SCOPE Instance, Unordered) - Level 0 - RTPS Handling");
@ -300,12 +323,14 @@ begin
valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := gen_key_hash;
kh2 := gen_key_hash;
kh3 := gen_key_hash;
kh4 := gen_key_hash;
kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh5 := gen_key_hash;
@ -318,6 +343,8 @@ begin
-- ISTATE: -
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -340,10 +367,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, 0, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -366,10 +396,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VAILDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -381,6 +414,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
@ -399,6 +438,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I1S2+, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -409,10 +454,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S2+, 0, 0, 0
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
-- TEST: DISPOSE SAMPLE [KNOWN INSTANCE]
-- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
@ -428,10 +476,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, 0, 0
-- ISTATE: I1:DISPOSED
-- WRITER: W0:I1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -449,10 +500,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE
-- WRITER: W0:I1, W1:I2
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -472,10 +526,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, I3S1
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO);
@ -485,6 +542,12 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I1S3-, I2S1+, I3S1
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -495,10 +558,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I1S2+, I2S1+, I3S1, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -516,6 +582,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2+, I2S1+, I3S1, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -526,10 +598,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I2S1+, I3S1, 0, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
@ -540,10 +615,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -561,6 +639,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I1, W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
@ -572,10 +656,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W1:I2,I3, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
@ -589,10 +676,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, I4S1
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -604,6 +694,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I2S1+, I3S1, I3S2, I4S1
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
@ -614,10 +710,13 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, 0
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -635,13 +734,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, 0
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh4;
cc.payload := gen_payload(kh4,10);
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(9,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -653,16 +758,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh2;
cc.payload := gen_payload(kh2,10);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(10,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE]
@ -674,13 +782,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(11,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
@ -692,8 +806,18 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE
-- WRITER: W1:I2,I3,I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -704,10 +828,61 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S1, I3S2, I4S1, I4S2
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.src_timestamp := check_time;
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S1, I4S2, I2S2-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- NOTE: We read the current KH4 Samples, so that we can easiy remove the new KH4 Sample
Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := READ_INSTANCE;
dds.max_samples := 2;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S1, I4S2, I2S2-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.src_timestamp := check_time;
Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE_INSTANCE;
@ -716,30 +891,38 @@ begin
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_dds;
wait_on_dds;
-- MEM: I3S1, I3S2, I4S2, 0
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S3-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
-- NOTE: We read the current KH4 Sample, so that we can easiy remove the new KH4 Sample
Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := READ_INSTANCE;
dds.opcode := TAKE_INSTANCE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.sstate := NOT_READ_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
dds.inst := kh4;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER
-- WRITER: W2:I3
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := HANDLE_NIL;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(12,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
-- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH]
@ -755,16 +938,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I3S1, I3S2, I4S2, I4S3-
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S4-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(10,0);
cc.src_timestamp := gen_duration(13,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
@ -777,26 +963,59 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I2S2-, I4S4-
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.max_samples := 2;
dds.sstate := NOT_READ_SAMPLE_STATE;
dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
-- MEM: I3S1, I3S2, I4S2, 0
wait_on_idle;
-- MEM: I3S2, I4S2, 0, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh3;
cc.payload := gen_payload(kh3,10);
cc.src_timestamp := gen_duration(14,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 2;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,30);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(15,0);
-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE
@ -808,13 +1027,19 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, 0
-- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,20);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(16,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -827,10 +1052,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: I3S1, I3S2, I4S2, I1S1+
wait_on_idle;
-- MEM: I3S2, I4S2, I3S3, I1S1+
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1, W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -842,20 +1070,23 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1, W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(10,0);
cc.src_timestamp := gen_duration(17,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (ACCEPTED)", INFO);
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
@ -863,16 +1094,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1,I4 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(11,0);
cc.src_timestamp := gen_duration(18,0);
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER]
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
@ -885,16 +1119,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(12,0);
cc.src_timestamp := gen_duration(19,0);
-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER]
@ -906,16 +1143,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.payload := gen_payload(kh2,5);
cc.src_timestamp := gen_duration(13,0);
cc.src_timestamp := gen_duration(20,0);
-- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE]
@ -927,16 +1167,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W0:I1 W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(14,0);
cc.src_timestamp := gen_duration(21,0);
Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -948,16 +1191,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, 0, 0, 0
-- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(14,0);
cc.src_timestamp := gen_duration(22,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -969,13 +1215,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, 0, 0, 0
-- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(15,0);
cc.src_timestamp := gen_duration(23,0);
-- TEST: FILTER SAMPLE [KNOWN INSTANCE]
-- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -990,16 +1242,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(16,0);
cc.src_timestamp := gen_duration(24,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION]
@ -1011,16 +1266,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh2;
cc.payload := gen_payload(kh2,10);
cc.src_timestamp := gen_duration(17,0);
cc.src_timestamp := gen_duration(25,0);
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE]
@ -1035,10 +1293,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S2-, I1S3-, I2S1, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1050,16 +1311,19 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(18,0);
cc.src_timestamp := gen_duration(26,0);
Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -1071,20 +1335,23 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, 0, 0, 0
-- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh1;
cc.payload := gen_payload(kh1,5);
cc.src_timestamp := gen_duration(19,0);
cc.src_timestamp := gen_duration(27,0);
-- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO);
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
@ -1094,16 +1361,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := ALIVE_FILTERED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(20,0);
cc.src_timestamp := gen_duration(28,0);
-- TEST: FILTER SAMPLE [UNKNOWN INSTANCE]
@ -1115,6 +1385,12 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
@ -1133,13 +1409,19 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, 0, 0
-- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE
-- WRITER: W0:I2, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.instance := kh2;
cc.payload := gen_payload(kh2,5);
cc.src_timestamp := gen_duration(21,0);
cc.src_timestamp := gen_duration(29,0);
Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -1151,10 +1433,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S4-, I1S5-, I2S2-, 0
-- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1166,16 +1451,19 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE
-- WRITER: W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.instance := kh4;
cc.payload := gen_payload(kh4,5);
cc.src_timestamp := gen_duration(22,0);
cc.src_timestamp := gen_duration(30,0);
-- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE]
@ -1189,10 +1477,13 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I4S1-, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -1204,6 +1495,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: I4S1-, 0, 0, 0
-- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED
-- WRITER: W1:I4, W2:I1,I3
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);

263
src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd
View File

@ -17,6 +17,8 @@ use work.rtps_test_package.all;
-- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
-- TEST: REMOVE_WRITER [KNOWN WRITER]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: SAMPLE WITH ALIGNED PAYLOAD
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
@ -87,7 +89,7 @@ architecture testbench of L0_dds_reader_test1_arznriu is
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
-- *FUNCTION DECLARATION*
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
@ -187,9 +189,11 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1: INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
@ -256,6 +260,23 @@ begin
end if;
end procedure;
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;
begin
SetAlertLogName("dds_reader - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyless, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Level 0 - RTPS Handling");
@ -281,6 +302,7 @@ begin
valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := gen_key_hash;
@ -294,6 +316,8 @@ begin
-- ISTATE: -
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -314,10 +338,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
@ -334,12 +361,18 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,18);
cc.src_timestamp := gen_duration(2,0);
cc.src_timestamp := gen_duration(3,0);
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]
@ -353,15 +386,18 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1, S2
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(3,0);
cc.src_timestamp := gen_duration(4,0);
-- TEST: ADD SAMPLE ON MAX_SAMPLES
@ -373,6 +409,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1, S2
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
@ -385,14 +427,17 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.src_timestamp := gen_duration(3,0);
cc.src_timestamp := gen_duration(5,0);
-- TEST: DISPOSE SAMPLE
@ -406,14 +451,17 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S3-, 0
-- ISTATE: DISPOSED
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.src_timestamp := gen_duration(4,0);
cc.src_timestamp := gen_duration(6,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
@ -425,11 +473,17 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S3-, 0
-- ISTATE: DISPOSED
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE_FILTERED;
cc.src_timestamp := gen_duration(4,0);
cc.src_timestamp := gen_duration(7,0);
-- TEST: FILTER SAMPLE
-- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
@ -444,10 +498,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S3-, S4-
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -459,15 +516,18 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,30);
cc.src_timestamp := gen_duration(5,0);
cc.src_timestamp := gen_duration(8,0);
Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -479,15 +539,18 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S5++, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(6,0);
cc.src_timestamp := gen_duration(9,0);
-- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL
@ -499,6 +562,12 @@ begin
rtps.ret_code := REJECTED;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S5++, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
@ -509,6 +578,12 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S5++, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
@ -521,11 +596,64 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
---------------------------------------------------------------------------
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(10,0);
Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCPETED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S6, 0
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(11,0);
Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCPETED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S6, S7
-- ISTATE: ALIVE
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- TEST: REMOVE_WRITER [KNOWN WRITER]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
@ -535,18 +663,60 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
-- MEM: S6-, 0
wait_on_idle;
-- MEM: S6, S7
-- ISTATE: NO_WRITERS
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := TRUE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.src_timestamp := check_time;
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: S7, S8-
-- ISTATE: NO_WRITERS
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := TAKE;
dds.max_samples := 1;
dds.sstate := ANY_SAMPLE_STATE;
dds.istate := ANY_INSTANCE_STATE;
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: S8-, 0
-- ISTATE: NO_WRITERS
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
-- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE_FILTERED;
cc.src_timestamp := gen_duration(7,0);
cc.src_timestamp := gen_duration(12,0);
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 1] (IGNORED)", INFO);
Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 1] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
@ -556,10 +726,15 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
-- MEM: S6-, S7-
wait_on_idle;
-- MEM: S8-, S9-
-- ISTATE: ALIVE
-- WRITER: W1
--------------------------------------------------------------------------------------
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -571,14 +746,17 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: ALIVE
-- WRITER: W1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(13,0);
-- TEST: UNREGISTER SAMPLE [UNKNOWN WRITER]
@ -590,11 +768,17 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: ALIVE
-- WRITER: W1
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(14,0);
-- TEST: UNREGISTER SAMPLE [KNOWN WRITER]
@ -608,14 +792,17 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
-- MEM: S7-, 0
wait_on_idle;
-- MEM: S10-, 0
-- ISTATE: NO_WRITERS
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(15,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -627,11 +814,17 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S10-, 0
-- ISTATE: NO_WRITERS
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_DISPOSED;
cc.src_timestamp := gen_duration(8,0);
cc.src_timestamp := gen_duration(16,0);
-- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE]
@ -645,10 +838,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
-- MEM: S7-, S8-
wait_on_idle;
-- MEM: S10-, S11-
-- ISTATE: DISPOSED
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -660,14 +856,17 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: DISPOSED
-- WRITER: W0
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := NOT_ALIVE_UNREGISTERED;
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(17,0);
-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE]
@ -679,15 +878,18 @@ begin
rtps.ret_code := OK;
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: 0, 0
-- ISTATE: DISPOSED
-- WRITER: -
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,6);
cc.src_timestamp := gen_duration(9,0);
cc.src_timestamp := gen_duration(18,0);
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT]
@ -701,15 +903,18 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
-- MEM: S9, 0
wait_on_idle;
-- MEM: S12, 0
-- ISTATE: ALIVE
-- WRITER: W2
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(5,0);
cc.src_timestamp := gen_duration(19,0);
-- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ]
@ -723,10 +928,13 @@ begin
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
-- MEM: S9, S10
wait_on_idle;
-- MEM: S12, S13
-- ISTATE: ALIVE
-- WRITER: W1, W2
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0");
-- VALIDATE STATE
Log("DDS Operation READ [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO);
@ -738,7 +946,12 @@ begin
dds.vstate := ANY_VIEW_STATE;
start_dds;
wait_on_dds;
wait_on_idle;
-- MEM: S12, S13
-- ISTATE: ALIVE
-- WRITER: W1, W2
AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);

462
src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd
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File diff suppressed because it is too large Load Diff

461
src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd
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File diff suppressed because it is too large Load Diff

8
src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd
View File

@ -164,9 +164,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -238,15 +238,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

6
src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd
View File

@ -204,9 +204,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -278,15 +278,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

10
src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd
View File

@ -204,9 +204,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -278,15 +278,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;
@ -317,10 +319,10 @@ begin
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh5 := gen_key_hash;

6
src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd
View File

@ -204,9 +204,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -278,15 +278,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

6
src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd
View File

@ -204,9 +204,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -278,15 +278,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

6
src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd
View File

@ -205,9 +205,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -279,15 +279,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

6
src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd
View File

@ -185,9 +185,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -259,15 +259,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

8
src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd
View File

@ -164,9 +164,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -238,15 +238,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

8
src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd
View File

@ -164,9 +164,9 @@ begin
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
@ -238,15 +238,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

4
src/Tests/Level_0/L0_dds_reader_test5_arzkriu.vhd
View File

@ -238,15 +238,17 @@ begin
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
variable first : boolean := TRUE;
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
elsif (not first) then
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
first := FALSE;
end loop;
end procedure;

4
src/Tests/Level_0/dds_reader_tests.txt
View File

@ -4,6 +4,10 @@
-- TEST: REMOVE_WRITER [UNKNOWN WRITER]
-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)]
-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)]
-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition]
-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions]
-- TEST: SAMPLE WITH ALIGNED PAYLOAD
-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT]

122
src/Tests/testbench.pro
View File

@ -2,7 +2,7 @@
include ../OSVVM/osvvm.pro
# Compile
library Level0-rtps_handler
library Testbench-Lib
analyze ../math_pkg.vhd
analyze ../rtps_package.vhd
analyze test_config.vhd
@ -20,65 +20,65 @@ analyze ../rtps_reader.vhd
analyze ../rtps_writer.vhd
analyze ../dds_writer.vhd
analyze ../dds_reader.vhd
#analyze Level_0/L0_rtps_handler_test1.vhd
#analyze Level_0/L0_rtps_handler_test2.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test1.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test2.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test3.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test4.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test5.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test6.vhd
#analyze Level_0/L0_rtps_builtin_endpoint_test7.vhd
#analyze Level_0/L0_rtps_out_test1.vhd
#analyze Level_1/L1_rtps_builtin_endpoint_test1.vhd
#analyze Level_0/L0_mem_ctrl_test1.vhd
#analyze Level_0/L0_rtps_reader_test1_vrk.vhd
#analyze Level_0/L0_rtps_reader_test1_vbk.vhd
#analyze Level_0/L0_rtps_reader_test2_vrk.vhd
#analyze Level_0/L0_rtps_reader_test2_trk.vhd
#analyze Level_0/L0_rtps_reader_test2_vbk.vhd
#analyze Level_0/L0_rtps_reader_test2_tbk.vhd
#analyze Level_0/L0_rtps_reader_test2_vrn.vhd
#analyze Level_0/L0_rtps_reader_test3_a.vhd
#analyze Level_0/L0_rtps_reader_test3_m.vhd
#analyze Level_1/L1_rtps_reader_test1_vrk.vhd
#analyze Level_1/L1_rtps_reader_test1_trk.vhd
#analyze Level_0/L0_rtps_writer_test1_vrkdp.vhd
#analyze Level_0/L0_rtps_writer_test1_vbkdp.vhd
#analyze Level_1/L1_rtps_writer_test1_vrkdp.vhd
#analyze Level_1/L1_rtps_writer_test1_trkdp.vhd
#analyze Level_1/L1_rtps_writer_test1_tbkdp.vhd
#analyze Level_1/L1_rtps_writer_test1_vbkdp.vhd
#analyze Level_1/L1_rtps_writer_test1_vrndp.vhd
#analyze Level_1/L1_rtps_writer_test1_vrksp.vhd
#analyze Level_1/L1_rtps_writer_test1_vrkdn.vhd
#analyze Level_1/L1_rtps_writer_test1_trkdn.vhd
#analyze Level_1/L1_rtps_writer_test2_vrkdn.vhd
#analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd
#analyze Level_0/L0_dds_writer_test1_aik.vhd
#analyze Level_0/L0_dds_writer_test1_ain.vhd
#analyze Level_0/L0_dds_writer_test1_lik.vhd
#analyze Level_0/L0_dds_writer_test1_afk.vhd
#analyze Level_0/L0_dds_writer_test2_aik.vhd
#analyze Level_0/L0_dds_writer_test3_aik.vhd
#analyze Level_0/L0_dds_writer_test3_ain.vhd
#analyze Level_0/L0_dds_writer_test4_aik.vhd
#analyze Level_0/L0_dds_writer_test5_afk.vhd
#analyze Level_0/L0_dds_reader_test1_arzkriu.vhd
#analyze Level_0/L0_dds_reader_test1_lrzkriu.vhd
#analyze Level_0/L0_dds_reader_test1_lbzkriu.vhd
#analyze Level_0/L0_dds_reader_test1_abzkriu.vhd
#analyze Level_0/L0_dds_reader_test1_arznriu.vhd
#analyze Level_0/L0_dds_reader_test1_arzksiu.vhd
#analyze Level_0/L0_dds_reader_test2_arpkriu.vhd
#analyze Level_0/L0_dds_reader_test3_arzkriu.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrio.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrtu.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrto.vhd
#analyze Level_0/L0_dds_reader_test3_arznriu.vhd
#analyze Level_0/L0_dds_reader_test3_arzksto.vhd
#analyze Level_0/L0_dds_reader_test4_arzkriu.vhd
#analyze Level_0/L0_dds_reader_test4_arznriu.vhd
analyze Level_0/L0_rtps_handler_test1.vhd
analyze Level_0/L0_rtps_handler_test2.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test1.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test2.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test3.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test4.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test5.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test6.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test7.vhd
analyze Level_0/L0_rtps_out_test1.vhd
analyze Level_1/L1_rtps_builtin_endpoint_test1.vhd
analyze Level_0/L0_mem_ctrl_test1.vhd
analyze Level_0/L0_rtps_reader_test1_vrk.vhd
analyze Level_0/L0_rtps_reader_test1_vbk.vhd
analyze Level_0/L0_rtps_reader_test2_vrk.vhd
analyze Level_0/L0_rtps_reader_test2_trk.vhd
analyze Level_0/L0_rtps_reader_test2_vbk.vhd
analyze Level_0/L0_rtps_reader_test2_tbk.vhd
analyze Level_0/L0_rtps_reader_test2_vrn.vhd
analyze Level_0/L0_rtps_reader_test3_a.vhd
analyze Level_0/L0_rtps_reader_test3_m.vhd
analyze Level_1/L1_rtps_reader_test1_vrk.vhd
analyze Level_1/L1_rtps_reader_test1_trk.vhd
analyze Level_0/L0_rtps_writer_test1_vrkdp.vhd
analyze Level_0/L0_rtps_writer_test1_vbkdp.vhd
analyze Level_1/L1_rtps_writer_test1_vrkdp.vhd
analyze Level_1/L1_rtps_writer_test1_trkdp.vhd
analyze Level_1/L1_rtps_writer_test1_tbkdp.vhd
analyze Level_1/L1_rtps_writer_test1_vbkdp.vhd
analyze Level_1/L1_rtps_writer_test1_vrndp.vhd
analyze Level_1/L1_rtps_writer_test1_vrksp.vhd
analyze Level_1/L1_rtps_writer_test1_vrkdn.vhd
analyze Level_1/L1_rtps_writer_test1_trkdn.vhd
analyze Level_1/L1_rtps_writer_test2_vrkdn.vhd
analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd
analyze Level_0/L0_dds_writer_test1_aik.vhd
analyze Level_0/L0_dds_writer_test1_ain.vhd
analyze Level_0/L0_dds_writer_test1_lik.vhd
analyze Level_0/L0_dds_writer_test1_afk.vhd
analyze Level_0/L0_dds_writer_test2_aik.vhd
analyze Level_0/L0_dds_writer_test3_aik.vhd
analyze Level_0/L0_dds_writer_test3_ain.vhd
analyze Level_0/L0_dds_writer_test4_aik.vhd
analyze Level_0/L0_dds_writer_test5_afk.vhd
analyze Level_0/L0_dds_reader_test1_arzkriu.vhd
analyze Level_0/L0_dds_reader_test1_lrzkriu.vhd
analyze Level_0/L0_dds_reader_test1_lbzkriu.vhd
analyze Level_0/L0_dds_reader_test1_abzkriu.vhd
analyze Level_0/L0_dds_reader_test1_arznriu.vhd
analyze Level_0/L0_dds_reader_test1_arzksiu.vhd
analyze Level_0/L0_dds_reader_test2_arpkriu.vhd
analyze Level_0/L0_dds_reader_test3_arzkriu.vhd
analyze Level_0/L0_dds_reader_test3_arzkrio.vhd
analyze Level_0/L0_dds_reader_test3_arzkrtu.vhd
analyze Level_0/L0_dds_reader_test3_arzkrto.vhd
analyze Level_0/L0_dds_reader_test3_arznriu.vhd
analyze Level_0/L0_dds_reader_test3_arzksto.vhd
analyze Level_0/L0_dds_reader_test4_arzkriu.vhd
analyze Level_0/L0_dds_reader_test4_arznriu.vhd
analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
#simulate L0_rtps_handler_test1
@ -140,4 +140,4 @@ analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
#simulate L0_dds_reader_test3_arzksto
#simulate L0_dds_reader_test4_arzkriu
#simulate L0_dds_reader_test4_arznriu
simulate L0_dds_reader_test5_arzkriu
#simulate L0_dds_reader_test5_arzkriu

392
src/dds_reader.vhd
View File

@ -209,10 +209,10 @@ architecture arch of dds_reader is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE, RETURN_DDS, RETURN_RTPS, ADD_SAMPLE_INFO, ADD_PAYLOAD_ADDRESS, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH,
FILTER_STAGE, UPDATE_INSTANCE, FINALIZE_PAYLOAD, PRE_SAMPLE_FINALIZE, FIND_POS, FIX_POINTERS, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_OLDEST_INST_SAMPLE,
REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, REMOVE_WRITER, REMOVE_STALE_INSTANCE, GET_NEXT_SAMPLE, PRE_CALCULATE, FINALIZE_SAMPLE_INFO,
GET_PAYLOAD, FIND_NEXT_INSTANCE, CHECK_INSTANCE, CHECK_LIFESPAN, GET_SAMPLE_REJECTED_STATUS, GET_REQUESTED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY,
RESET_PAYLOAD_MEMORY);
FILTER_STAGE, UPDATE_INSTANCE, FINALIZE_PAYLOAD, PRE_SAMPLE_FINALIZE, FIND_POS, FIX_POINTERS, FINALIZE_SAMPLE, GENERATE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE,
FIND_OLDEST_INST_SAMPLE, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, REMOVE_WRITER, REMOVE_STALE_INSTANCE, GET_NEXT_SAMPLE, PRE_CALCULATE, FINALIZE_SAMPLE_INFO,
GET_PAYLOAD, FIND_NEXT_INSTANCE, CHECK_INSTANCE, CHECK_LIFESPAN, PROCESS_PENDING_SAMPLE_GENERATION, GET_SAMPLE_REJECTED_STATUS, GET_REQUESTED_DEADLINE_MISSED_STATUS,
CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY);
-- Instance Memory FSM states. Explained below in detail
type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE,
REMOVE_INSTANCE, UNMARK_INSTANCES, RESET_MEMORY);
@ -424,6 +424,10 @@ architecture arch of dds_reader is
signal newer_inst_sample, newer_inst_sample_next : std_logic := '0';
-- Denotes if a new Instance is added
signal new_inst, new_inst_next : std_logic := '0';
-- Triggers Sample Generation
signal trigger_sample_gen, trigger_sample_gen_next : std_logic := '0';
-- Waits for Sample Removal (MAX_SAMPLES Limit lift) to trigger Sample Generation
signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic := '0';
-- *COMMUNICATION STATUS*
signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
@ -629,6 +633,7 @@ begin
-- FIND_POS Find Sample List position based on DESTINATION_ORDER_QOS
-- FIX_POINTERS Update the List Pointers of the inserted Sample neighbours (First Step of Sample Addition Finalization)
-- FINALIZE_SAMPLE Update inserted sample and list pointers. (Second Step of Sample Addition Finalization)
-- GENERATE_SAMPLE Generate a NOT_ALIVE_NO_WRITERS Sample
-- GET_OLDEST_SAMPLE_INSTANCE Fetch the Instance Data of the oldest sample
-- FIND_OLDEST_INST_SAMPLE Find the oldest sample of a specific Instance
-- REMOVE_SAMPLE Remove sample and linked payload
@ -643,6 +648,7 @@ begin
-- FIND_NEXT_INSTANCE Find next Instance that passes requested masks
-- CHECK_INSTANCE Check if selected Instance passes requested masks
-- CHECK_LIFESPAN Check and remove samples with expired Lifespans
-- PROCESS_PENDING_SAMPLE_GENERATION Iterate through the Instances and Generate Samples where required
-- GET_SAMPLE_REJECTED_STATUS Return Sample Rejected Status
-- GET_REQUESTED_DEADLINE_MISSED_STATUS Return Requested Deadline Missed Status
-- CHECK_DEADLINE Check and Mark Instances with missed Deadlines
@ -728,6 +734,8 @@ begin
no_w_gen_cnt_latch_next <= no_w_gen_cnt_latch;
newer_inst_sample_next <= newer_inst_sample;
new_inst_next <= new_inst;
trigger_sample_gen_next <= trigger_sample_gen;
wait_for_sample_removal_next <= wait_for_sample_removal;
-- DEFAULT Unregistered
inst_opcode <= NOP;
opcode_kh <= NOP;
@ -809,6 +817,52 @@ begin
stage_next <= CHECK_LIFESPAN;
cnt_next <= 0;
end if;
-- Sample Generation
elsif (trigger_sample_gen = '1') then
-- Synthesis Guard
if (WITH_KEY) then
stage_next <= PROCESS_PENDING_SAMPLE_GENERATION;
cnt_next <= 0;
else
-- RESOURCE_LIMITS_QOS (MAX_SAMPLES)
if (empty_sample_list_head = empty_sample_list_tail) then
if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then
wait_for_sample_removal_next <= '1';
-- Reset
trigger_sample_gen_next <= '0';
-- DONE
stage_next <= IDLE;
else
-- Reset
trigger_sample_gen_next <= '0';
-- Update Instance
inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0';
inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1;
-- Accept Change (Remove Oldest Sample)
remove_oldest_sample_next <= '1';
cur_sample_next <= empty_sample_list_head;
cur_inst_next <= inst_addr_base;
stage_next <= GENERATE_SAMPLE;
cnt_next <= 0;
end if;
else
-- Reset
trigger_sample_gen_next <= '0';
-- Update Instance
inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0';
inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1;
cur_sample_next <= empty_sample_list_head;
cur_inst_next <= inst_addr_base;
stage_next <= GENERATE_SAMPLE;
cnt_next <= 0;
end if;
end if;
-- RTPS Operation
elsif (start_rtps = '1') then
case (opcode_rtps) is
@ -872,6 +926,8 @@ begin
-- NOT_ALIVE_NO_WRITERS Transition
if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then
trigger_sample_gen_next <= '1';
inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1';
inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
end if;
@ -1537,7 +1593,7 @@ begin
end if;
end if;
when FILTER_STAGE =>
-- Precondition: cur_sample set, inst_data set (IMF_IGNORE_DEADLINE_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG)
-- Precondition: cur_sample set, inst_data set (IMF_STATUS_FLAG, IMF_IGNORE_DEADLINE_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG)
-- Wait for Instance Search to finish
if (not WITH_KEY or inst_op_done = '1') then
@ -1556,6 +1612,20 @@ begin
done_rtps <= '1';
ret_rtps <= OK;
stage_next <= IDLE;
-- Pending Sample Generation
-- NOTE: If there is a Pending Sample Generation and we reach this stage, the limiting factor is still here and the Sample will be rejected.
-- In order to have a valid sample rejected status it makes sense to let the sample be rejected "naturally".
--elsif (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then
-- -- Reject Change
-- done_rtps <= '1';
-- ret_rtps <= REJECTED;
-- stage_next <= IDLE;
-- -- Update Sample Reject Status
-- status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
-- sample_rej_cnt_next <= sample_rej_cnt + 1;
-- sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
-- sample_rej_last_reason_next <= REJECTED_BY_PENDING_SAMPLE_GENERATION;
-- sample_rej_last_inst_next <= key_hash;
-- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE)
elsif (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then
if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then
@ -2409,6 +2479,183 @@ begin
when others =>
null;
end case;
when GENERATE_SAMPLE =>
-- Precondition: cur_sample set, cur_inst set, inst_data set (IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG)
case (cnt) is
-- GET Next Sample (Empty List)
when 0 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET;
sample_read <= '1';
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Sample Status Info
when 1 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET;
sample_write_data <= (SSI_UNREGISTERED_FLAG => '1', others => '0');
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Timestamp 1/2
when 2 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET;
sample_write_data <= std_logic_vector(time(0));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Timestamp 2/2
when 3 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1;
sample_write_data <= std_logic_vector(time(1));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Lifespan 1/2
when 4 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET;
sample_write_data <= std_logic_vector(TIME_INVALID(0));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Lifespan 2/2
when 5 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1;
sample_write_data <= std_logic_vector(TIME_INVALID(1));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Payload Pointer
when 6 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET;
sample_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Instance Pointer
when 7 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET;
sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Disposed Generation Count
when 8 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET;
sample_write_data <= std_logic_vector(inst_data.disposed_gen_cnt);
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET No Writers Generation Count
when 9 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET;
sample_write_data <= std_logic_vector(inst_data.no_writers_gen_cnt);
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Previous Sample Pointer
when 10 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET;
sample_write_data <= std_logic_vector(resize(newest_sample,WORD_WIDTH));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- SET Next Sample Pointer
when 11 =>
sample_valid_in <= '1';
sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET;
sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
assert (newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE;
cnt_next <= cnt + 1;
end if;
-- SET Next Sample Pointer (Previous Sample)
when 12 =>
sample_valid_in <= '1';
sample_addr <= newest_sample + SMF_NEXT_ADDR_OFFSET;
sample_write_data <= std_logic_vector(resize(empty_sample_list_head,WORD_WIDTH));
-- Memory Flow Control Guard
if (sample_ready_in = '1') then
cnt_next <= cnt + 1;
end if;
-- READ Next Address (Empty List)
when 13 =>
sample_ready_out <= '1';
-- Memory Flow Control Guard
if (sample_valid_out = '1') then
-- Update Sample List Pointer
newest_sample_next <= cur_sample;
empty_sample_list_head_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH);
-- Signal Data Available
status_sig_next <= status_sig or DATA_AVAILABLE_STATUS;
if (WITH_KEY and remove_oldest_inst_sample = '1') then
assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE;
cur_sample_next <= oldest_sample;
stage_next <= FIND_OLDEST_INST_SAMPLE;
cnt_next <= 0;
elsif (remove_oldest_sample = '1') then
assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE;
-- Synthesis Guard
if (WITH_KEY) then
stage_next <= GET_OLDEST_SAMPLE_INSTANCE;
cnt_next <= 0;
else
cur_sample_next <= oldest_sample;
stage_next <= REMOVE_SAMPLE;
cnt_next <= 0;
end if;
elsif (trigger_sample_gen = '1') then
-- Continue
stage_next <= PROCESS_PENDING_SAMPLE_GENERATION;
cnt_next <= 1;
else
-- DONE
stage_next <= IDLE;
end if;
end if;
when others =>
null;
end case;
when GET_OLDEST_SAMPLE_INSTANCE =>
-- Synthesis Guard
if (WITH_KEY) then
@ -2709,7 +2956,7 @@ begin
null;
end case;
when POST_SAMPLE_REMOVE =>
-- Precondition: inst_data set (IMF_SAMPLE_CNT_FLAG, IMF_WRITER_BITMAP_FLAG)
-- Precondition: inst_data set (IMF_SAMPLE_CNT_FLAG, IMF_WRITER_BITMAP_FLAG, IMF_STATUS_FLAG)
-- Memory Operation Guard
if (not WITH_KEY or inst_op_done = '1') then
@ -2728,6 +2975,16 @@ begin
inst_data_next2.sample_cnt <= inst_data.sample_cnt - 1;
end if;
if (wait_for_sample_removal = '1' or inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then
trigger_sample_gen_next <= '1';
-- Reset
wait_for_sample_removal_next <= '0';
end if;
-- Reset
remove_oldest_inst_sample_next <= '0';
remove_oldest_sample_next <= '0';
if (is_take = '1') then
-- cur_inst has no more samples in collection
if (si_sample_rank_sig = 0) then
@ -2759,6 +3016,10 @@ begin
stage_next <= CHECK_LIFESPAN;
cnt_next <= 0;
end if;
elsif (trigger_sample_gen = '1') then
-- Continue
stage_next <= PROCESS_PENDING_SAMPLE_GENERATION;
cnt_next <= 1;
else
-- DONE
stage_next <= IDLE;
@ -2810,8 +3071,10 @@ begin
-- NOT_ALIVE_NO_WRITERS Transition
if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then
trigger_sample_gen_next <= '1';
status_info_update <= inst_data.status_info;
status_info_update(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '1';
inst_op_start <= '1';
inst_opcode <= UPDATE_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG;
@ -4201,6 +4464,117 @@ begin
when others =>
null;
end case;
when PROCESS_PENDING_SAMPLE_GENERATION =>
-- Synthesis Guard
if (WITH_KEY) then
-- Wait for Instance Data
if (inst_op_done = '1') then
case (cnt) is
when 0 =>
inst_op_start <= '1';
inst_opcode <= GET_FIRST_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG;
cnt_next <= cnt + 2;
when 1 =>
-- Continue
inst_op_start <= '1';
inst_opcode <= GET_NEXT_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG;
cnt_next <= cnt + 1;
when 2 =>
-- Instance Found
if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then
-- Sample needs to be Generated
if (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then
-- GET Required Instance Data
inst_op_start <= '1';
inst_opcode <= GET_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG;
inst_addr_update <= inst_addr_base;
cnt_next <= cnt + 1;
else
-- Continue
inst_op_start <= '1';
inst_opcode <= GET_NEXT_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG;
end if;
else
-- Reset
trigger_sample_gen_next <= '0';
-- DONE
stage_next <= IDLE;
end if;
when 3 =>
-- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE)
if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then
if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Continue
inst_op_start <= '1';
inst_opcode <= GET_NEXT_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG;
cnt_next <= 2;
else
-- Accept Change (Remove Oldest Instance Sample)
remove_oldest_inst_sample_next <= '1';
-- Update Instance
inst_op_start <= '1';
inst_opcode <= UPDATE_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG;
sample_cnt <= inst_data.sample_cnt + 1;
status_info_update <= inst_data.status_info;
status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0';
cur_sample_next <= empty_sample_list_head;
cur_inst_next <= inst_addr_base;
stage_next <= GENERATE_SAMPLE;
cnt_next <= 0;
end if;
-- RESOURCE_LIMITS_QOS (MAX_SAMPLES)
elsif (empty_sample_list_head = empty_sample_list_tail) then
if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then
wait_for_sample_removal_next <= '1';
-- Reset
trigger_sample_gen_next <= '0';
-- DONE
stage_next <= IDLE;
else
-- Accept Change (Remove Oldest Sample)
remove_oldest_sample_next <= '1';
-- Update Instance
inst_op_start <= '1';
inst_opcode <= UPDATE_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG;
sample_cnt <= inst_data.sample_cnt + 1;
status_info_update <= inst_data.status_info;
status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0';
cur_sample_next <= empty_sample_list_head;
cur_inst_next <= inst_addr_base;
stage_next <= GENERATE_SAMPLE;
cnt_next <= 0;
end if;
else
-- Update Instance
inst_op_start <= '1';
inst_opcode <= UPDATE_INSTANCE;
inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG;
sample_cnt <= inst_data.sample_cnt + 1;
status_info_update <= inst_data.status_info;
status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0';
cur_sample_next <= empty_sample_list_head;
cur_inst_next <= inst_addr_base;
stage_next <= GENERATE_SAMPLE;
cnt_next <= 0;
end if;
when others =>
null;
end case;
end if;
end if;
when GET_SAMPLE_REJECTED_STATUS =>
case (cnt) is
-- Return Code
@ -4517,7 +4891,7 @@ begin
current_imf_next <= inst_mem_fields;
inst_data_next <= ZERO_INSTANCE_DATA;
-- No Instances avialable
-- No Instances available
if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then
inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS;
else
@ -6159,6 +6533,8 @@ begin
pre_calculated <= '0';
newer_inst_sample <= '0';
new_inst <= '0';
trigger_sample_gen <= '0';
wait_for_sample_removal <= '0';
dis_gen_cnt_latch <= (others => '0');
no_w_gen_cnt_latch <= (others => '0');
current_imf <= (others => '0');
@ -6244,6 +6620,8 @@ begin
pre_calculated <= pre_calculated_next;
newer_inst_sample <= newer_inst_sample_next;
new_inst <= new_inst_next;
trigger_sample_gen <= trigger_sample_gen_next;
wait_for_sample_removal <= wait_for_sample_removal_next;
dis_gen_cnt_latch <= dis_gen_cnt_latch_next;
no_w_gen_cnt_latch <= no_w_gen_cnt_latch_next;
current_imf <= current_imf_next;

1
src/rtps_config_package.vhd
View File

@ -66,6 +66,7 @@ package rtps_config_package is
constant ISI_LIVELINESS_FLAG : natural := 2;
constant ISI_VIEW_FLAG : natural := 3; -- Reader Only
constant ISI_MARK_FLAG : natural := 4; -- Reader Only
constant ISI_GENERATE_SAMPLE_FLAG : natural := 5; -- Reader Only
-- Remote Endpoint Flags
constant READER_FLAGS_WIDTH : natural := 16;

1
src/rtps_package.vhd
View File

@ -177,6 +177,7 @@ package rtps_package is
constant REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(3,CDR_ENUMERATION_WIDTH));
-- Extension
constant REJECTED_BY_PAYOAD_MEMORY_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(255,CDR_ENUMERATION_WIDTH));
constant REJECTED_BY_PENDING_SAMPLE_GENERATION : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(256,CDR_ENUMERATION_WIDTH));
-- *QOS POLICY ID* (DDS)
constant INVALID_QOS_POLICY_ID : std_logic_vector(QOS_POLICY_ID_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(0,QOS_POLICY_ID_WIDTH));